| blob | d14f9b3deb78f2a581d6aee6ca923850bb66cea3 |
1 [options]\r
2 \r
3 version: 1.343\r
4 file_version: 1.332\r
5 project_name: "test"\r
6 full_library_folder: "c:\program files\freepcb\lib"\r
7 CAM_folder: ""\r
8 ses_file_path: ""\r
9 SMT_connect_copper: "0"\r
10 dsn_flags: "0"\r
11 dsn_bounds_poly: "0"\r
12 dsn_signals_poly: "0"\r
13 autosave_interval: 0\r
14 netlist_import_flags: 451\r
15 units: MIL\r
16 \r
17 visible_grid_spacing: 5080000.000000\r
18 visible_grid_item: 100MIL\r
19 visible_grid_item: 125MIL\r
20 visible_grid_item: 200MIL\r
21 visible_grid_item: 250MIL\r
22 visible_grid_item: 400MIL\r
23 visible_grid_item: 500MIL\r
24 visible_grid_item: 1000MIL\r
25 visible_grid_item: 1MM\r
26 visible_grid_item: 2MM\r
27 visible_grid_item: 2.5MM\r
28 visible_grid_item: 4MM\r
29 visible_grid_item: 5MM\r
30 visible_grid_item: 10MM\r
31 visible_grid_item: 20MM\r
32 visible_grid_item: 25MM\r
33 visible_grid_item: 40MM\r
34 visible_grid_item: 50MM\r
35 visible_grid_item: 100MM\r
36 \r
37 placement_grid_spacing: 2540000.000000\r
38 placement_grid_item: 10MIL\r
39 placement_grid_item: 20MIL\r
40 placement_grid_item: 25MIL\r
41 placement_grid_item: 40MIL\r
42 placement_grid_item: 50MIL\r
43 placement_grid_item: 100MIL\r
44 placement_grid_item: 200MIL\r
45 placement_grid_item: 250MIL\r
46 placement_grid_item: 400MIL\r
47 placement_grid_item: 500MIL\r
48 placement_grid_item: 1000MIL\r
49 placement_grid_item: 0.1MM\r
50 placement_grid_item: 0.2MM\r
51 placement_grid_item: 0.25MM\r
52 placement_grid_item: 0.4MM\r
53 placement_grid_item: 0.5MM\r
54 placement_grid_item: 1MM\r
55 placement_grid_item: 2MM\r
56 placement_grid_item: 2.5MM\r
57 placement_grid_item: 4MM\r
58 placement_grid_item: 5MM\r
59 placement_grid_item: 10MM\r
60 \r
61 routing_grid_spacing: 508000.000000\r
62 routing_grid_item: 1MIL\r
63 routing_grid_item: 2MIL\r
64 routing_grid_item: 2.5MIL\r
65 routing_grid_item: 3.33330709MIL\r
66 routing_grid_item: 4MIL\r
67 routing_grid_item: 5MIL\r
68 routing_grid_item: 6.66665354MIL\r
69 routing_grid_item: 10MIL\r
70 routing_grid_item: 12.5MIL\r
71 routing_grid_item: 16.66665354MIL\r
72 routing_grid_item: 20MIL\r
73 routing_grid_item: 25MIL\r
74 routing_grid_item: 40MIL\r
75 routing_grid_item: 50MIL\r
76 routing_grid_item: 0.01MM\r
77 routing_grid_item: 0.02MM\r
78 routing_grid_item: 0.04MM\r
79 routing_grid_item: 0.05MM\r
80 routing_grid_item: 0.1MM\r
81 routing_grid_item: 0.2MM\r
82 routing_grid_item: 0.25MM\r
83 routing_grid_item: 0.4MM\r
84 routing_grid_item: 0.5MM\r
85 routing_grid_item: 1MM\r
86 routing_grid_item: 2MM\r
87 routing_grid_item: 2.5MM\r
88 routing_grid_item: 4MM\r
89 routing_grid_item: 5MM\r
90 routing_grid_item: 10MM\r
91 \r
92 snap_angle: 45\r
93 \r
94 fp_visible_grid_spacing: 5080000.000000\r
95 fp_visible_grid_item: 100MIL\r
96 fp_visible_grid_item: 125MIL\r
97 fp_visible_grid_item: 200MIL\r
98 fp_visible_grid_item: 250MIL\r
99 fp_visible_grid_item: 400MIL\r
100 fp_visible_grid_item: 500MIL\r
101 fp_visible_grid_item: 1000MIL\r
102 fp_visible_grid_item: 1MM\r
103 fp_visible_grid_item: 2MM\r
104 fp_visible_grid_item: 2.5MM\r
105 fp_visible_grid_item: 4MM\r
106 fp_visible_grid_item: 5MM\r
107 fp_visible_grid_item: 10MM\r
108 fp_visible_grid_item: 20MM\r
109 fp_visible_grid_item: 25MM\r
110 fp_visible_grid_item: 40MM\r
111 fp_visible_grid_item: 50MM\r
112 fp_visible_grid_item: 100MM\r
113 \r
114 fp_placement_grid_spacing: 2540000.000000\r
115 fp_placement_grid_item: 10MIL\r
116 fp_placement_grid_item: 20MIL\r
117 fp_placement_grid_item: 25MIL\r
118 fp_placement_grid_item: 40MIL\r
119 fp_placement_grid_item: 50MIL\r
120 fp_placement_grid_item: 100MIL\r
121 fp_placement_grid_item: 200MIL\r
122 fp_placement_grid_item: 250MIL\r
123 fp_placement_grid_item: 400MIL\r
124 fp_placement_grid_item: 500MIL\r
125 fp_placement_grid_item: 1000MIL\r
126 fp_placement_grid_item: 0.1MM\r
127 fp_placement_grid_item: 0.2MM\r
128 fp_placement_grid_item: 0.25MM\r
129 fp_placement_grid_item: 0.4MM\r
130 fp_placement_grid_item: 0.5MM\r
131 fp_placement_grid_item: 1MM\r
132 fp_placement_grid_item: 2MM\r
133 fp_placement_grid_item: 2.5MM\r
134 fp_placement_grid_item: 4MM\r
135 fp_placement_grid_item: 5MM\r
136 fp_placement_grid_item: 10MM\r
137 \r
138 fp_snap_angle: 45\r
139 \r
140 fill_clearance: 254000\r
141 mask_clearance: 203200\r
142 thermal_width: 254000\r
143 min_silkscreen_width: 127000\r
144 board_outline_width: 127000\r
145 hole_clearance: 381000\r
146 pilot_diameter: 254000\r
147 annular_ring_for_pins: 177800\r
148 annular_ring_for_vias: 127000\r
149 shrink_paste_mask: 0\r
150 cam_flags: 1\r
151 cam_layers: 15732735\r
152 cam_drill_file: 1\r
153 cam_units: 2\r
154 cam_n_x: 1\r
155 cam_n_y: 1\r
156 cam_space_x: 0\r
157 cam_space_y: 0\r
158 \r
159 report_options: 0\r
160 drc_check_unrouted: 0\r
161 drc_trace_width: 254000\r
162 drc_pad_pad: 254000\r
163 drc_pad_trace: 254000\r
164 drc_trace_trace: 254000\r
165 drc_hole_copper: 381000\r
166 drc_annular_ring_pins: 177800\r
167 drc_annular_ring_vias: 127000\r
168 drc_board_edge_copper: 635000\r
169 drc_board_edge_hole: 635000\r
170 drc_hole_hole: 635000\r
171 drc_copper_copper: 254000\r
172 \r
173 default_trace_width: 254000\r
174 default_via_pad_width: 711200\r
175 default_via_hole_width: 355600\r
176 n_width_menu: 7\r
177 width_menu_item: 1 152400 711200 355600\r
178 width_menu_item: 2 203200 711200 355600\r
179 width_menu_item: 3 254000 711200 355600\r
180 width_menu_item: 4 304800 711200 355600\r
181 width_menu_item: 5 381000 711200 355600\r
182 width_menu_item: 6 508000 711200 355600\r
183 width_menu_item: 7 635000 711200 355600\r
184 \r
185 n_copper_layers: 2\r
186 layer_info: "selection" 0 255 255 255 1\r
187 layer_info: "background" 1 0 0 0 1\r
188 layer_info: "visible grid" 2 255 255 255 1\r
189 layer_info: "highlight" 3 255 255 255 1\r
190 layer_info: "DRC error" 4 255 128 64 1\r
191 layer_info: "board outline" 5 0 0 255 1\r
192 layer_info: "rat line" 6 255 0 255 1\r
193 layer_info: "top silk" 7 255 255 0 1\r
194 layer_info: "bottom silk" 8 255 192 192 1\r
195 layer_info: "top sm cutout" 9 160 160 160 1\r
196 layer_info: "bot sm cutout" 10 95 95 95 1\r
197 layer_info: "thru pad" 11 0 0 255 1\r
198 layer_info: "top copper" 12 0 255 0 1\r
199 layer_info: "bottom copper" 13 255 0 0 1\r
200 \r
201 [footprints]\r
202 \r
203 name: "14DIP300"\r
204 author: "Ivex"\r
205 source: "DIGIKEY CATALOG NO. 941, PAGE 64"\r
206 units: MIL\r
207 sel_rect: -58 -35 658 335\r
208 ref_text: 50 -100 150 270 7\r
209 centroid: 0 300 150\r
210 outline_polyline: 7 -50 50\r
211 next_corner: 650 50 0\r
212 next_corner: 650 250 0\r
213 next_corner: -50 250 0\r
214 close_polyline: 0\r
215 outline_polyline: 7 -50 100\r
216 next_corner: 0 100 0\r
217 next_corner: 0 200 0\r
218 next_corner: -50 200 0\r
219 close_polyline: 0\r
220 n_pins: 14\r
221 pin: "1" 28 0 0 0\r
222 top_pad: 2 55 27 27 0\r
223 inner_pad: 1 55 27 27 0\r
224 bottom_pad: 2 55 27 27 0\r
225 pin: "2" 28 100 0 0\r
226 top_pad: 1 55 27 27 0\r
227 inner_pad: 1 55 27 27 0\r
228 bottom_pad: 1 55 27 27 0\r
229 pin: "3" 28 200 0 0\r
230 top_pad: 1 55 27 27 0\r
231 inner_pad: 1 55 27 27 0\r
232 bottom_pad: 1 55 27 27 0\r
233 pin: "4" 28 300 0 0\r
234 top_pad: 1 55 27 27 0\r
235 inner_pad: 1 55 27 27 0\r
236 bottom_pad: 1 55 27 27 0\r
237 pin: "5" 28 400 0 0\r
238 top_pad: 1 55 27 27 0\r
239 inner_pad: 1 55 27 27 0\r
240 bottom_pad: 1 55 27 27 0\r
241 pin: "6" 28 500 0 0\r
242 top_pad: 1 55 27 27 0\r
243 inner_pad: 1 55 27 27 0\r
244 bottom_pad: 1 55 27 27 0\r
245 pin: "7" 28 600 0 0\r
246 top_pad: 1 55 27 27 0\r
247 inner_pad: 1 55 27 27 0\r
248 bottom_pad: 1 55 27 27 0\r
249 pin: "8" 28 600 300 0\r
250 top_pad: 1 55 27 27 0\r
251 inner_pad: 1 55 27 27 0\r
252 bottom_pad: 1 55 27 27 0\r
253 pin: "9" 28 500 300 0\r
254 top_pad: 1 55 27 27 0\r
255 inner_pad: 1 55 27 27 0\r
256 bottom_pad: 1 55 27 27 0\r
257 pin: "10" 28 400 300 0\r
258 top_pad: 1 55 27 27 0\r
259 inner_pad: 1 55 27 27 0\r
260 bottom_pad: 1 55 27 27 0\r
261 pin: "11" 28 300 300 0\r
262 top_pad: 1 55 27 27 0\r
263 inner_pad: 1 55 27 27 0\r
264 bottom_pad: 1 55 27 27 0\r
265 pin: "12" 28 200 300 0\r
266 top_pad: 1 55 27 27 0\r
267 inner_pad: 1 55 27 27 0\r
268 bottom_pad: 1 55 27 27 0\r
269 pin: "13" 28 100 300 0\r
270 top_pad: 1 55 27 27 0\r
271 inner_pad: 1 55 27 27 0\r
272 bottom_pad: 1 55 27 27 0\r
273 pin: "14" 28 0 300 0\r
274 top_pad: 1 55 27 27 0\r
275 inner_pad: 1 55 27 27 0\r
276 bottom_pad: 1 55 27 27 0\r
277 \r
278 name: "1X2HDR-100"\r
279 author: "Ivex"\r
280 source: "PRINTED CIRCUIT DESIGN METHODS PAGE 411"\r
281 units: MIL\r
282 sel_rect: -33 -33 33 133\r
283 ref_text: 50 0 160 0 7\r
284 centroid: 0 0 50\r
285 n_pins: 2\r
286 pin: "1" 28 0 0 0\r
287 top_pad: 2 50 25 25 0\r
288 inner_pad: 1 50 25 25 0\r
289 bottom_pad: 2 50 25 25 0\r
290 pin: "2" 28 0 100 0\r
291 top_pad: 1 50 25 25 0\r
292 inner_pad: 1 50 25 25 0\r
293 bottom_pad: 1 50 25 25 0\r
294 \r
295 name: "RC07"\r
296 author: "Ivex"\r
297 source: "DIGITAL PRINTED CIRCUIT DESIGN & DRAFTING, PAGE 408"\r
298 units: MIL\r
299 sel_rect: -45 -57 545 57\r
300 ref_text: 50 250 99 0 7\r
301 centroid: 0 250 0\r
302 outline_polyline: 7 109 49\r
303 next_corner: 391 49 0\r
304 next_corner: 391 -49 0\r
305 next_corner: 109 -49 0\r
306 close_polyline: 0\r
307 n_pins: 2\r
308 pin: "1" 35 0 0 0\r
309 top_pad: 1 75 37 37 0\r
310 inner_pad: 1 75 37 37 0\r
311 bottom_pad: 1 75 37 37 0\r
312 pin: "2" 35 500 0 0\r
313 top_pad: 1 75 37 37 0\r
314 inner_pad: 1 75 37 37 0\r
315 bottom_pad: 1 75 37 37 0\r
316 \r
317 [board]\r
318 \r
319 [solder_mask_cutouts]\r
320 \r
321 \r
322 [parts]\r
323 \r
324 part: Vclk\r
325 ref_text: 1270000 177800 0 0 4064000\r
326 package: "1X2HDR-100"\r
327 shape: "1X2HDR-100"\r
328 pos: -4241800 838200 0 0 0\r
329 \r
330 part: Vd\r
331 ref_text: 1270000 177800 0 0 4064000\r
332 package: "1X2HDR-100"\r
333 shape: "1X2HDR-100"\r
334 pos: -4241800 8458200 0 0 0\r
335 \r
336 part: V$XX1$Vdd\r
337 ref_text: 1270000 177800 0 0 4064000\r
338 package: "1X2HDR-100"\r
339 shape: "1X2HDR-100"\r
340 pos: -4241800 16078200 0 0 0\r
341 \r
342 part: V$XX1$Vss\r
343 ref_text: 1270000 177800 0 0 4064000\r
344 package: "1X2HDR-100"\r
345 shape: "1X2HDR-100"\r
346 pos: -4241800 23698200 0 0 0\r
347 \r
348 part: X_IC_0_CD4007\r
349 ref_text: 1270000 177800 270 -2540000 3810000\r
350 package: "14DIP300"\r
351 shape: "14DIP300"\r
352 pos: -21386800 31369000 0 0 0\r
353 \r
354 part: X_IC_1_CD4007\r
355 ref_text: 1270000 177800 270 -2540000 3810000\r
356 package: "14DIP300"\r
357 shape: "14DIP300"\r
358 pos: -21386800 44069000 0 0 0\r
359 \r
360 part: X_IC_2_CD4007\r
361 ref_text: 1270000 177800 270 -2540000 3810000\r
362 package: "14DIP300"\r
363 shape: "14DIP300"\r
364 pos: -21386800 56769000 0 0 0\r
365 \r
366 part: X_IC_3_CD4007\r
367 ref_text: 1270000 177800 270 -2540000 3810000\r
368 package: "14DIP300"\r
369 shape: "14DIP300"\r
370 pos: -21386800 69469000 0 0 0\r
371 \r
372 part: X_IC_4_CD4007\r
373 ref_text: 1270000 177800 270 -2540000 3810000\r
374 package: "14DIP300"\r
375 shape: "14DIP300"\r
376 pos: -21386800 82169000 0 0 0\r
377 \r
378 part: X_IC_5_CD4007\r
379 ref_text: 1270000 177800 270 -2540000 3810000\r
380 package: "14DIP300"\r
381 shape: "14DIP300"\r
382 pos: -21386800 94869000 0 0 0\r
383 \r
384 part: X_IC_6_CD4007\r
385 ref_text: 1270000 177800 270 -2540000 3810000\r
386 package: "14DIP300"\r
387 shape: "14DIP300"\r
388 pos: -21386800 107569000 0 0 0\r
389 \r
390 part: X_IC_7_CD4007\r
391 ref_text: 1270000 177800 270 -2540000 3810000\r
392 package: "14DIP300"\r
393 shape: "14DIP300"\r
394 pos: -26466800 889000 0 0 0\r
395 \r
396 part: X_IC_8_CD4007\r
397 ref_text: 1270000 177800 270 -2540000 3810000\r
398 package: "14DIP300"\r
399 shape: "14DIP300"\r
400 pos: -26466800 13589000 0 0 0\r
401 \r
402 part: X_IC_9_CD4007\r
403 ref_text: 1270000 177800 270 -2540000 3810000\r
404 package: "14DIP300"\r
405 shape: "14DIP300"\r
406 pos: -44246800 26289000 0 0 0\r
407 \r
408 part: RX$Xff$XMaster$XXlatch$RP\r
409 ref_text: 1270000 177800 0 6350000 2514600\r
410 package: "RC07"\r
411 shape: "RC07"\r
412 pos: -39497000 39547800 0 0 0\r
413 \r
414 part: RX$Xff$XMaster$XXlatch$RN\r
415 ref_text: 1270000 177800 0 6350000 2514600\r
416 package: "RC07"\r
417 shape: "RC07"\r
418 pos: -39497000 47167800 0 0 0\r
419 \r
420 part: RX$Xff$XMaster$X_Xlatch$RP\r
421 ref_text: 1270000 177800 0 6350000 2514600\r
422 package: "RC07"\r
423 shape: "RC07"\r
424 pos: -39497000 54787800 0 0 0\r
425 \r
426 part: RX$Xff$XMaster$X_Xlatch$RN\r
427 ref_text: 1270000 177800 0 6350000 2514600\r
428 package: "RC07"\r
429 shape: "RC07"\r
430 pos: -39497000 62407800 0 0 0\r
431 \r
432 part: RX$Xff$XMaster$XXgatetop$RP\r
433 ref_text: 1270000 177800 0 6350000 2514600\r
434 package: "RC07"\r
435 shape: "RC07"\r
436 pos: -39497000 70027800 0 0 0\r
437 \r
438 part: RX$Xff$XMaster$XXgatetop$RN\r
439 ref_text: 1270000 177800 0 6350000 2514600\r
440 package: "RC07"\r
441 shape: "RC07"\r
442 pos: -39497000 77647800 0 0 0\r
443 \r
444 part: RX$Xff$XMaster$XXgatebot$RP\r
445 ref_text: 1270000 177800 0 6350000 2514600\r
446 package: "RC07"\r
447 shape: "RC07"\r
448 pos: -39497000 85267800 0 0 0\r
449 \r
450 part: RX$Xff$XMaster$XXgatebot$RN\r
451 ref_text: 1270000 177800 0 6350000 2514600\r
452 package: "RC07"\r
453 shape: "RC07"\r
454 pos: -39497000 92887800 0 0 0\r
455 \r
456 part: RX$Xff$XMaster$XXstiD$XXinv$RP\r
457 ref_text: 1270000 177800 0 6350000 2514600\r
458 package: "RC07"\r
459 shape: "RC07"\r
460 pos: -39497000 100507800 0 0 0\r
461 \r
462 part: RX$Xff$XMaster$XXstiD$XXinv$RN\r
463 ref_text: 1270000 177800 0 6350000 2514600\r
464 package: "RC07"\r
465 shape: "RC07"\r
466 pos: -39497000 108127800 0 0 0\r
467 \r
468 part: RX$Xff$XSlave$XXlatch$RP\r
469 ref_text: 1270000 177800 0 6350000 2514600\r
470 package: "RC07"\r
471 shape: "RC07"\r
472 pos: -39497000 115747800 0 0 0\r
473 \r
474 part: RX$Xff$XSlave$XXlatch$RN\r
475 ref_text: 1270000 177800 0 6350000 2514600\r
476 package: "RC07"\r
477 shape: "RC07"\r
478 pos: -44577000 1447800 0 0 0\r
479 \r
480 part: RX$Xff$XSlave$X_Xlatch$RP\r
481 ref_text: 1270000 177800 0 6350000 2514600\r
482 package: "RC07"\r
483 shape: "RC07"\r
484 pos: -44577000 9067800 0 0 0\r
485 \r
486 part: RX$Xff$XSlave$X_Xlatch$RN\r
487 ref_text: 1270000 177800 0 6350000 2514600\r
488 package: "RC07"\r
489 shape: "RC07"\r
490 pos: -44577000 16687800 0 0 0\r
491 \r
492 part: RX$Xff$XSlave$XXgatetop$RP\r
493 ref_text: 1270000 177800 0 6350000 2514600\r
494 package: "RC07"\r
495 shape: "RC07"\r
496 pos: -57277000 39547800 0 0 0\r
497 \r
498 part: RX$Xff$XSlave$XXgatetop$RN\r
499 ref_text: 1270000 177800 0 6350000 2514600\r
500 package: "RC07"\r
501 shape: "RC07"\r
502 pos: -57277000 47167800 0 0 0\r
503 \r
504 part: RX$Xff$XSlave$XXgatebot$RP\r
505 ref_text: 1270000 177800 0 6350000 2514600\r
506 package: "RC07"\r
507 shape: "RC07"\r
508 pos: -57277000 54787800 0 0 0\r
509 \r
510 part: RX$Xff$XSlave$XXgatebot$RN\r
511 ref_text: 1270000 177800 0 6350000 2514600\r
512 package: "RC07"\r
513 shape: "RC07"\r
514 pos: -57277000 62407800 0 0 0\r
515 \r
516 part: RX$Xff$XSlave$XXstiD$XXinv$RP\r
517 ref_text: 1270000 177800 0 6350000 2514600\r
518 package: "RC07"\r
519 shape: "RC07"\r
520 pos: -57277000 70027800 0 0 0\r
521 \r
522 part: RX$Xff$XSlave$XXstiD$XXinv$RN\r
523 ref_text: 1270000 177800 0 6350000 2514600\r
524 package: "RC07"\r
525 shape: "RC07"\r
526 pos: -57277000 77647800 0 0 0\r
527 \r
528 part: RX$Xff$XXstiCLK$XXinv$RP\r
529 ref_text: 1270000 177800 0 6350000 2514600\r
530 package: "RC07"\r
531 shape: "RC07"\r
532 pos: -57277000 85267800 0 0 0\r
533 \r
534 part: RX$Xff$XXstiCLK$XXinv$RN\r
535 ref_text: 1270000 177800 0 6350000 2514600\r
536 package: "RC07"\r
537 shape: "RC07"\r
538 pos: -57277000 92887800 0 0 0\r
539 \r
540 [nets]\r
541 \r
542 net: "Xff$XSlave$Q_storage" 3 2 0 0 0 0 1\r
543 pin: 1 X_IC_5_CD4007.3\r
544 pin: 2 RX$Xff$XSlave$XXgatetop$RP.2\r
545 pin: 3 RX$Xff$XSlave$XXgatetop$RN.1\r
546 connect: 1 2 1 1 0\r
547 vtx: 1 -57277000 47167800 11 0 0 0 0\r
548 seg: 1 6 0 0 0\r
549 vtx: 2 -44577000 39547800 11 0 0 0 0\r
550 connect: 2 1 0 1 0\r
551 vtx: 1 -44577000 39547800 11 0 0 0 0\r
552 seg: 1 6 0 0 0\r
553 vtx: 2 -16306800 94869000 11 0 0 0 0\r
554 \r
555 net: "Xff$XMaster$X_Xlatch$NP" 3 2 0 0 0 0 1\r
556 pin: 1 X_IC_1_CD4007.1\r
557 pin: 2 X_IC_1_CD4007.13\r
558 pin: 3 RX$Xff$XMaster$X_Xlatch$RP.1\r
559 connect: 1 1 0 1 0\r
560 vtx: 1 -18846800 51689000 11 0 0 0 0\r
561 seg: 1 6 0 0 0\r
562 vtx: 2 -21386800 44069000 11 0 0 0 0\r
563 connect: 2 2 1 1 0\r
564 vtx: 1 -39497000 54787800 11 0 0 0 0\r
565 seg: 1 6 0 0 0\r
566 vtx: 2 -18846800 51689000 11 0 0 0 0\r
567 \r
568 net: "D" 3 2 0 0 0 0 1\r
569 pin: 1 Vd.1\r
570 pin: 2 X_IC_2_CD4007.3\r
571 pin: 3 X_IC_4_CD4007.6\r
572 connect: 1 2 1 1 0\r
573 vtx: 1 -8686800 82169000 11 0 0 0 0\r
574 seg: 1 6 0 0 0\r
575 vtx: 2 -16306800 56769000 11 0 0 0 0\r
576 connect: 2 1 0 1 0\r
577 vtx: 1 -16306800 56769000 11 0 0 0 0\r
578 seg: 1 6 0 0 0\r
579 vtx: 2 -4241800 8458200 11 0 0 0 0\r
580 \r
581 net: "Xff$XMaster$XXgatebot$NI" 2 1 0 0 0 0 1\r
582 pin: 1 X_IC_3_CD4007.4\r
583 pin: 2 X_IC_3_CD4007.8\r
584 connect: 1 1 0 1 0\r
585 vtx: 1 -6146800 77089000 11 0 0 0 0\r
586 seg: 1 6 0 0 0\r
587 vtx: 2 -13766800 69469000 11 0 0 0 0\r
588 \r
589 net: "Xff$XSlave$XXgatebot$NI" 2 1 0 0 0 0 1\r
590 pin: 1 X_IC_8_CD4007.4\r
591 pin: 2 X_IC_8_CD4007.8\r
592 connect: 1 1 0 1 0\r
593 vtx: 1 -11226800 21209000 11 0 0 0 0\r
594 seg: 1 6 0 0 0\r
595 vtx: 2 -18846800 13589000 11 0 0 0 0\r
596 \r
597 net: "Xff$XSlave$XXlatch$NN" 2 1 0 0 0 0 1\r
598 pin: 1 X_IC_5_CD4007.9\r
599 pin: 2 RX$Xff$XSlave$XXlatch$RN.2\r
600 connect: 1 1 0 1 0\r
601 vtx: 1 -31877000 1447800 11 0 0 0 0\r
602 seg: 1 6 0 0 0\r
603 vtx: 2 -8686800 102489000 11 0 0 0 0\r
604 \r
605 net: "Xff$_CLK" 4 3 0 0 0 0 1\r
606 pin: 1 X_IC_2_CD4007.6\r
607 pin: 2 X_IC_3_CD4007.3\r
608 pin: 3 RX$Xff$XXstiCLK$XXinv$RP.2\r
609 pin: 4 RX$Xff$XXstiCLK$XXinv$RN.1\r
610 connect: 1 1 0 1 0\r
611 vtx: 1 -16306800 69469000 11 0 0 0 0\r
612 seg: 1 6 0 0 0\r
613 vtx: 2 -8686800 56769000 11 0 0 0 0\r
614 connect: 2 3 2 1 0\r
615 vtx: 1 -57277000 92887800 11 0 0 0 0\r
616 seg: 1 6 0 0 0\r
617 vtx: 2 -44577000 85267800 11 0 0 0 0\r
618 connect: 3 2 1 1 0\r
619 vtx: 1 -44577000 85267800 11 0 0 0 0\r
620 seg: 1 6 0 0 0\r
621 vtx: 2 -16306800 69469000 11 0 0 0 0\r
622 \r
623 net: "Xff$XMaster$XXlatch$NI" 2 1 0 0 0 0 1\r
624 pin: 1 X_IC_0_CD4007.4\r
625 pin: 2 X_IC_0_CD4007.8\r
626 connect: 1 1 0 1 0\r
627 vtx: 1 -6146800 38989000 11 0 0 0 0\r
628 seg: 1 6 0 0 0\r
629 vtx: 2 -13766800 31369000 11 0 0 0 0\r
630 \r
631 net: "Xff$XMaster$XXgatetop$NI" 2 1 0 0 0 0 1\r
632 pin: 1 X_IC_2_CD4007.4\r
633 pin: 2 X_IC_2_CD4007.8\r
634 connect: 1 1 0 1 0\r
635 vtx: 1 -6146800 64389000 11 0 0 0 0\r
636 seg: 1 6 0 0 0\r
637 vtx: 2 -13766800 56769000 11 0 0 0 0\r
638 \r
639 net: "Xff$XSlave$_Q_storage" 3 2 0 0 0 0 1\r
640 pin: 1 X_IC_6_CD4007.6\r
641 pin: 2 RX$Xff$XSlave$XXgatebot$RP.2\r
642 pin: 3 RX$Xff$XSlave$XXgatebot$RN.1\r
643 connect: 1 2 1 1 0\r
644 vtx: 1 -57277000 62407800 11 0 0 0 0\r
645 seg: 1 6 0 0 0\r
646 vtx: 2 -44577000 54787800 11 0 0 0 0\r
647 connect: 2 1 0 1 0\r
648 vtx: 1 -44577000 54787800 11 0 0 0 0\r
649 seg: 1 6 0 0 0\r
650 vtx: 2 -8686800 107569000 11 0 0 0 0\r
651 \r
652 net: "Xff$XSlave$XXlatch$NP" 3 2 0 0 0 0 1\r
653 pin: 1 X_IC_5_CD4007.1\r
654 pin: 2 X_IC_5_CD4007.13\r
655 pin: 3 RX$Xff$XSlave$XXlatch$RP.1\r
656 connect: 1 1 0 1 0\r
657 vtx: 1 -18846800 102489000 11 0 0 0 0\r
658 seg: 1 6 0 0 0\r
659 vtx: 2 -21386800 94869000 11 0 0 0 0\r
660 connect: 2 2 1 1 0\r
661 vtx: 1 -39497000 115747800 11 0 0 0 0\r
662 seg: 1 6 0 0 0\r
663 vtx: 2 -18846800 102489000 11 0 0 0 0\r
664 \r
665 net: "_Q" 3 2 0 0 0 0 1\r
666 pin: 1 X_IC_5_CD4007.6\r
667 pin: 2 RX$Xff$XSlave$X_Xlatch$RP.2\r
668 pin: 3 RX$Xff$XSlave$X_Xlatch$RN.1\r
669 connect: 1 2 1 1 0\r
670 vtx: 1 -44577000 16687800 11 0 0 0 0\r
671 seg: 1 6 0 0 0\r
672 vtx: 2 -31877000 9067800 11 0 0 0 0\r
673 connect: 2 2 0 1 0\r
674 vtx: 1 -44577000 16687800 11 0 0 0 0\r
675 seg: 1 6 0 0 0\r
676 vtx: 2 -8686800 94869000 11 0 0 0 0\r
677 \r
678 net: "Xff$XSlave$XXgatetop$NI" 2 1 0 0 0 0 1\r
679 pin: 1 X_IC_7_CD4007.4\r
680 pin: 2 X_IC_7_CD4007.8\r
681 connect: 1 1 0 1 0\r
682 vtx: 1 -11226800 8509000 11 0 0 0 0\r
683 seg: 1 6 0 0 0\r
684 vtx: 2 -18846800 889000 11 0 0 0 0\r
685 \r
686 net: "Xff$XSlave$X_Xlatch$NN" 2 1 0 0 0 0 1\r
687 pin: 1 X_IC_6_CD4007.9\r
688 pin: 2 RX$Xff$XSlave$X_Xlatch$RN.2\r
689 connect: 1 1 0 1 0\r
690 vtx: 1 -31877000 16687800 11 0 0 0 0\r
691 seg: 1 6 0 0 0\r
692 vtx: 2 -8686800 115189000 11 0 0 0 0\r
693 \r
694 net: "Xff$XMaster$XXgatebot$NN" 2 1 0 0 0 0 1\r
695 pin: 1 X_IC_3_CD4007.9\r
696 pin: 2 RX$Xff$XMaster$XXgatebot$RN.2\r
697 connect: 1 1 0 1 0\r
698 vtx: 1 -26797000 92887800 11 0 0 0 0\r
699 seg: 1 6 0 0 0\r
700 vtx: 2 -8686800 77089000 11 0 0 0 0\r
701 \r
702 net: "Xff$XMaster$XXstiD$NTI_Out" 2 1 0 0 0 0 1\r
703 pin: 1 X_IC_4_CD4007.8\r
704 pin: 2 RX$Xff$XMaster$XXstiD$XXinv$RN.2\r
705 connect: 1 1 0 1 0\r
706 vtx: 1 -26797000 108127800 11 0 0 0 0\r
707 seg: 1 6 0 0 0\r
708 vtx: 2 -6146800 89789000 11 0 0 0 0\r
709 \r
710 net: "Xff$XSlave$XXgatebot$NN" 2 1 0 0 0 0 1\r
711 pin: 1 X_IC_8_CD4007.9\r
712 pin: 2 RX$Xff$XSlave$XXgatebot$RN.2\r
713 connect: 1 1 0 1 0\r
714 vtx: 1 -44577000 62407800 11 0 0 0 0\r
715 seg: 1 6 0 0 0\r
716 vtx: 2 -13766800 21209000 11 0 0 0 0\r
717 \r
718 net: "Xff$XSlave$X_Xlatch$NP" 3 2 0 0 0 0 1\r
719 pin: 1 X_IC_6_CD4007.1\r
720 pin: 2 X_IC_6_CD4007.13\r
721 pin: 3 RX$Xff$XSlave$X_Xlatch$RP.1\r
722 connect: 1 1 0 1 0\r
723 vtx: 1 -18846800 115189000 11 0 0 0 0\r
724 seg: 1 6 0 0 0\r
725 vtx: 2 -21386800 107569000 11 0 0 0 0\r
726 connect: 2 2 0 1 0\r
727 vtx: 1 -44577000 9067800 11 0 0 0 0\r
728 seg: 1 6 0 0 0\r
729 vtx: 2 -21386800 107569000 11 0 0 0 0\r
730 \r
731 net: "Xff$XMaster$XXlatch$NN" 2 1 0 0 0 0 1\r
732 pin: 1 X_IC_0_CD4007.9\r
733 pin: 2 RX$Xff$XMaster$XXlatch$RN.2\r
734 connect: 1 1 0 1 0\r
735 vtx: 1 -26797000 47167800 11 0 0 0 0\r
736 seg: 1 6 0 0 0\r
737 vtx: 2 -8686800 38989000 11 0 0 0 0\r
738 \r
739 net: "Xff$XMaster$XXstiD$PTI_Out" 2 1 0 0 0 0 1\r
740 pin: 1 X_IC_4_CD4007.13\r
741 pin: 2 RX$Xff$XMaster$XXstiD$XXinv$RP.1\r
742 connect: 1 1 0 1 0\r
743 vtx: 1 -39497000 100507800 11 0 0 0 0\r
744 seg: 1 6 0 0 0\r
745 vtx: 2 -18846800 89789000 11 0 0 0 0\r
746 \r
747 net: "Xff$XMaster$XXgatebot$NP" 3 2 0 0 0 0 1\r
748 pin: 1 X_IC_3_CD4007.1\r
749 pin: 2 X_IC_3_CD4007.13\r
750 pin: 3 RX$Xff$XMaster$XXgatebot$RP.1\r
751 connect: 1 1 0 1 0\r
752 vtx: 1 -18846800 77089000 11 0 0 0 0\r
753 seg: 1 6 0 0 0\r
754 vtx: 2 -21386800 69469000 11 0 0 0 0\r
755 connect: 2 2 1 1 0\r
756 vtx: 1 -39497000 85267800 11 0 0 0 0\r
757 seg: 1 6 0 0 0\r
758 vtx: 2 -18846800 77089000 11 0 0 0 0\r
759 \r
760 net: "Xff$XSlave$XXstiD$NTI_Out" 2 1 0 0 0 0 1\r
761 pin: 1 X_IC_4_CD4007.5\r
762 pin: 2 RX$Xff$XSlave$XXstiD$XXinv$RN.2\r
763 connect: 1 1 0 1 0\r
764 vtx: 1 -44577000 77647800 11 0 0 0 0\r
765 seg: 1 6 0 0 0\r
766 vtx: 2 -11226800 82169000 11 0 0 0 0\r
767 \r
768 net: "Xff$XSlave$XXgatebot$NP" 3 2 0 0 0 0 1\r
769 pin: 1 X_IC_8_CD4007.1\r
770 pin: 2 X_IC_8_CD4007.13\r
771 pin: 3 RX$Xff$XSlave$XXgatebot$RP.1\r
772 connect: 1 1 0 1 0\r
773 vtx: 1 -23926800 21209000 11 0 0 0 0\r
774 seg: 1 6 0 0 0\r
775 vtx: 2 -26466800 13589000 11 0 0 0 0\r
776 connect: 2 2 1 1 0\r
777 vtx: 1 -57277000 54787800 11 0 0 0 0\r
778 seg: 1 6 0 0 0\r
779 vtx: 2 -23926800 21209000 11 0 0 0 0\r
780 \r
781 net: "Xff$XMaster$XXgatetop$NN" 2 1 0 0 0 0 1\r
782 pin: 1 X_IC_2_CD4007.9\r
783 pin: 2 RX$Xff$XMaster$XXgatetop$RN.2\r
784 connect: 1 1 0 1 0\r
785 vtx: 1 -26797000 77647800 11 0 0 0 0\r
786 seg: 1 6 0 0 0\r
787 vtx: 2 -8686800 64389000 11 0 0 0 0\r
788 \r
789 net: "Xff$XMaster$_Q_storage" 3 2 0 0 0 0 1\r
790 pin: 1 X_IC_1_CD4007.6\r
791 pin: 2 RX$Xff$XMaster$XXgatebot$RP.2\r
792 pin: 3 RX$Xff$XMaster$XXgatebot$RN.1\r
793 connect: 1 2 1 1 0\r
794 vtx: 1 -39497000 92887800 11 0 0 0 0\r
795 seg: 1 6 0 0 0\r
796 vtx: 2 -26797000 85267800 11 0 0 0 0\r
797 connect: 2 1 0 1 0\r
798 vtx: 1 -26797000 85267800 11 0 0 0 0\r
799 seg: 1 6 0 0 0\r
800 vtx: 2 -8686800 44069000 11 0 0 0 0\r
801 \r
802 net: "Xff$XMaster$XXlatch$NP" 3 2 0 0 0 0 1\r
803 pin: 1 X_IC_0_CD4007.1\r
804 pin: 2 X_IC_0_CD4007.13\r
805 pin: 3 RX$Xff$XMaster$XXlatch$RP.1\r
806 connect: 1 1 0 1 0\r
807 vtx: 1 -18846800 38989000 11 0 0 0 0\r
808 seg: 1 6 0 0 0\r
809 vtx: 2 -21386800 31369000 11 0 0 0 0\r
810 connect: 2 2 0 1 0\r
811 vtx: 1 -39497000 39547800 11 0 0 0 0\r
812 seg: 1 6 0 0 0\r
813 vtx: 2 -21386800 31369000 11 0 0 0 0\r
814 \r
815 net: "Xff$XSlave$XXstiD$PTI_Out" 2 1 0 0 0 0 1\r
816 pin: 1 X_IC_4_CD4007.1\r
817 pin: 2 RX$Xff$XSlave$XXstiD$XXinv$RP.1\r
818 connect: 1 1 0 1 0\r
819 vtx: 1 -57277000 70027800 11 0 0 0 0\r
820 seg: 1 6 0 0 0\r
821 vtx: 2 -21386800 82169000 11 0 0 0 0\r
822 \r
823 net: "Xff$XSlave$XXgatetop$NN" 2 1 0 0 0 0 1\r
824 pin: 1 X_IC_7_CD4007.9\r
825 pin: 2 RX$Xff$XSlave$XXgatetop$RN.2\r
826 connect: 1 1 0 1 0\r
827 vtx: 1 -44577000 47167800 11 0 0 0 0\r
828 seg: 1 6 0 0 0\r
829 vtx: 2 -13766800 8509000 11 0 0 0 0\r
830 \r
831 net: "$G_Vss" 12 11 0 0 0 0 1\r
832 pin: 1 V$XX1$Vss.2\r
833 pin: 2 X_IC_0_CD4007.7\r
834 pin: 3 X_IC_1_CD4007.7\r
835 pin: 4 X_IC_2_CD4007.7\r
836 pin: 5 X_IC_3_CD4007.7\r
837 pin: 6 X_IC_4_CD4007.4\r
838 pin: 7 X_IC_4_CD4007.7\r
839 pin: 8 X_IC_5_CD4007.7\r
840 pin: 9 X_IC_6_CD4007.7\r
841 pin: 10 X_IC_7_CD4007.7\r
842 pin: 11 X_IC_8_CD4007.7\r
843 pin: 12 X_IC_9_CD4007.7\r
844 connect: 1 1 0 1 0\r
845 vtx: 1 -6146800 31369000 11 0 0 0 0\r
846 seg: 1 6 0 0 0\r
847 vtx: 2 -4241800 26238200 11 0 0 0 0\r
848 connect: 2 6 5 1 0\r
849 vtx: 1 -6146800 82169000 11 0 0 0 0\r
850 seg: 1 6 0 0 0\r
851 vtx: 2 -13766800 82169000 11 0 0 0 0\r
852 connect: 3 2 1 1 0\r
853 vtx: 1 -6146800 44069000 11 0 0 0 0\r
854 seg: 1 6 0 0 0\r
855 vtx: 2 -6146800 31369000 11 0 0 0 0\r
856 connect: 4 10 9 1 0\r
857 vtx: 1 -11226800 13589000 11 0 0 0 0\r
858 seg: 1 6 0 0 0\r
859 vtx: 2 -11226800 889000 11 0 0 0 0\r
860 connect: 5 8 7 1 0\r
861 vtx: 1 -6146800 107569000 11 0 0 0 0\r
862 seg: 1 6 0 0 0\r
863 vtx: 2 -6146800 94869000 11 0 0 0 0\r
864 connect: 6 3 2 1 0\r
865 vtx: 1 -6146800 56769000 11 0 0 0 0\r
866 seg: 1 6 0 0 0\r
867 vtx: 2 -6146800 44069000 11 0 0 0 0\r
868 connect: 7 7 6 1 0\r
869 vtx: 1 -6146800 94869000 11 0 0 0 0\r
870 seg: 1 6 0 0 0\r
871 vtx: 2 -6146800 82169000 11 0 0 0 0\r
872 connect: 8 6 4 1 0\r
873 vtx: 1 -6146800 82169000 11 0 0 0 0\r
874 seg: 1 6 0 0 0\r
875 vtx: 2 -6146800 69469000 11 0 0 0 0\r
876 connect: 9 4 3 1 0\r
877 vtx: 1 -6146800 69469000 11 0 0 0 0\r
878 seg: 1 6 0 0 0\r
879 vtx: 2 -6146800 56769000 11 0 0 0 0\r
880 connect: 10 10 0 1 0\r
881 vtx: 1 -11226800 13589000 11 0 0 0 0\r
882 seg: 1 6 0 0 0\r
883 vtx: 2 -4241800 26238200 11 0 0 0 0\r
884 connect: 11 11 10 1 0\r
885 vtx: 1 -29006800 26289000 11 0 0 0 0\r
886 seg: 1 6 0 0 0\r
887 vtx: 2 -11226800 13589000 11 0 0 0 0\r
888 \r
889 net: "$G_Vdd" 20 19 0 0 0 0 1\r
890 pin: 1 V$XX1$Vdd.1\r
891 pin: 2 X_IC_0_CD4007.2\r
892 pin: 3 X_IC_0_CD4007.14\r
893 pin: 4 X_IC_1_CD4007.2\r
894 pin: 5 X_IC_1_CD4007.14\r
895 pin: 6 X_IC_2_CD4007.2\r
896 pin: 7 X_IC_2_CD4007.14\r
897 pin: 8 X_IC_3_CD4007.2\r
898 pin: 9 X_IC_3_CD4007.14\r
899 pin: 10 X_IC_4_CD4007.2\r
900 pin: 11 X_IC_4_CD4007.14\r
901 pin: 12 X_IC_5_CD4007.2\r
902 pin: 13 X_IC_5_CD4007.14\r
903 pin: 14 X_IC_6_CD4007.2\r
904 pin: 15 X_IC_6_CD4007.14\r
905 pin: 16 X_IC_7_CD4007.2\r
906 pin: 17 X_IC_7_CD4007.14\r
907 pin: 18 X_IC_8_CD4007.2\r
908 pin: 19 X_IC_8_CD4007.14\r
909 pin: 20 X_IC_9_CD4007.14\r
910 connect: 1 9 8 1 0\r
911 vtx: 1 -18846800 82169000 11 0 0 0 0\r
912 seg: 1 6 0 0 0\r
913 vtx: 2 -21386800 77089000 11 0 0 0 0\r
914 connect: 2 11 10 1 0\r
915 vtx: 1 -18846800 94869000 11 0 0 0 0\r
916 seg: 1 6 0 0 0\r
917 vtx: 2 -21386800 89789000 11 0 0 0 0\r
918 connect: 3 17 16 1 0\r
919 vtx: 1 -23926800 13589000 11 0 0 0 0\r
920 seg: 1 6 0 0 0\r
921 vtx: 2 -26466800 8509000 11 0 0 0 0\r
922 connect: 4 13 12 1 0\r
923 vtx: 1 -18846800 107569000 11 0 0 0 0\r
924 seg: 1 6 0 0 0\r
925 vtx: 2 -21386800 102489000 11 0 0 0 0\r
926 connect: 5 7 6 1 0\r
927 vtx: 1 -18846800 69469000 11 0 0 0 0\r
928 seg: 1 6 0 0 0\r
929 vtx: 2 -21386800 64389000 11 0 0 0 0\r
930 connect: 6 3 2 1 0\r
931 vtx: 1 -18846800 44069000 11 0 0 0 0\r
932 seg: 1 6 0 0 0\r
933 vtx: 2 -21386800 38989000 11 0 0 0 0\r
934 connect: 7 5 4 1 0\r
935 vtx: 1 -18846800 56769000 11 0 0 0 0\r
936 seg: 1 6 0 0 0\r
937 vtx: 2 -21386800 51689000 11 0 0 0 0\r
938 connect: 8 2 1 1 0\r
939 vtx: 1 -21386800 38989000 11 0 0 0 0\r
940 seg: 1 6 0 0 0\r
941 vtx: 2 -18846800 31369000 11 0 0 0 0\r
942 connect: 9 18 17 1 0\r
943 vtx: 1 -26466800 21209000 11 0 0 0 0\r
944 seg: 1 6 0 0 0\r
945 vtx: 2 -23926800 13589000 11 0 0 0 0\r
946 connect: 10 4 3 1 0\r
947 vtx: 1 -21386800 51689000 11 0 0 0 0\r
948 seg: 1 6 0 0 0\r
949 vtx: 2 -18846800 44069000 11 0 0 0 0\r
950 connect: 11 10 9 1 0\r
951 vtx: 1 -21386800 89789000 11 0 0 0 0\r
952 seg: 1 6 0 0 0\r
953 vtx: 2 -18846800 82169000 11 0 0 0 0\r
954 connect: 12 6 5 1 0\r
955 vtx: 1 -21386800 64389000 11 0 0 0 0\r
956 seg: 1 6 0 0 0\r
957 vtx: 2 -18846800 56769000 11 0 0 0 0\r
958 connect: 13 8 7 1 0\r
959 vtx: 1 -21386800 77089000 11 0 0 0 0\r
960 seg: 1 6 0 0 0\r
961 vtx: 2 -18846800 69469000 11 0 0 0 0\r
962 connect: 14 16 15 1 0\r
963 vtx: 1 -26466800 8509000 11 0 0 0 0\r
964 seg: 1 6 0 0 0\r
965 vtx: 2 -23926800 889000 11 0 0 0 0\r
966 connect: 15 12 11 1 0\r
967 vtx: 1 -21386800 102489000 11 0 0 0 0\r
968 seg: 1 6 0 0 0\r
969 vtx: 2 -18846800 94869000 11 0 0 0 0\r
970 connect: 16 14 13 1 0\r
971 vtx: 1 -21386800 115189000 11 0 0 0 0\r
972 seg: 1 6 0 0 0\r
973 vtx: 2 -18846800 107569000 11 0 0 0 0\r
974 connect: 17 18 1 1 0\r
975 vtx: 1 -26466800 21209000 11 0 0 0 0\r
976 seg: 1 6 0 0 0\r
977 vtx: 2 -18846800 31369000 11 0 0 0 0\r
978 connect: 18 17 0 1 0\r
979 vtx: 1 -23926800 13589000 11 0 0 0 0\r
980 seg: 1 6 0 0 0\r
981 vtx: 2 -4241800 16078200 11 0 0 0 0\r
982 connect: 19 19 18 1 0\r
983 vtx: 1 -44246800 33909000 11 0 0 0 0\r
984 seg: 1 6 0 0 0\r
985 vtx: 2 -26466800 21209000 11 0 0 0 0\r
986 \r
987 net: "Xff$XMaster$XXgatetop$NP" 3 2 0 0 0 0 1\r
988 pin: 1 X_IC_2_CD4007.1\r
989 pin: 2 X_IC_2_CD4007.13\r
990 pin: 3 RX$Xff$XMaster$XXgatetop$RP.1\r
991 connect: 1 1 0 1 0\r
992 vtx: 1 -18846800 64389000 11 0 0 0 0\r
993 seg: 1 6 0 0 0\r
994 vtx: 2 -21386800 56769000 11 0 0 0 0\r
995 connect: 2 2 1 1 0\r
996 vtx: 1 -39497000 70027800 11 0 0 0 0\r
997 seg: 1 6 0 0 0\r
998 vtx: 2 -18846800 64389000 11 0 0 0 0\r
999 \r
1000 net: "Xff$XMaster$X_Xlatch$NI" 2 1 0 0 0 0 1\r
1001 pin: 1 X_IC_1_CD4007.4\r
1002 pin: 2 X_IC_1_CD4007.8\r
1003 connect: 1 1 0 1 0\r
1004 vtx: 1 -6146800 51689000 11 0 0 0 0\r
1005 seg: 1 6 0 0 0\r
1006 vtx: 2 -13766800 44069000 11 0 0 0 0\r
1007 \r
1008 net: "Xff$XXstiCLK$NTI_Out" 2 1 0 0 0 0 1\r
1009 pin: 1 X_IC_9_CD4007.8\r
1010 pin: 2 RX$Xff$XXstiCLK$XXinv$RN.2\r
1011 connect: 1 1 0 1 0\r
1012 vtx: 1 -44577000 92887800 11 0 0 0 0\r
1013 seg: 1 6 0 0 0\r
1014 vtx: 2 -29006800 33909000 11 0 0 0 0\r
1015 \r
1016 net: "Xff$XSlave$XXgatetop$NP" 3 2 0 0 0 0 1\r
1017 pin: 1 X_IC_7_CD4007.1\r
1018 pin: 2 X_IC_7_CD4007.13\r
1019 pin: 3 RX$Xff$XSlave$XXgatetop$RP.1\r
1020 connect: 1 1 0 1 0\r
1021 vtx: 1 -23926800 8509000 11 0 0 0 0\r
1022 seg: 1 6 0 0 0\r
1023 vtx: 2 -26466800 889000 11 0 0 0 0\r
1024 connect: 2 2 1 1 0\r
1025 vtx: 1 -57277000 39547800 11 0 0 0 0\r
1026 seg: 1 6 0 0 0\r
1027 vtx: 2 -23926800 8509000 11 0 0 0 0\r
1028 \r
1029 net: "Xff$XXstiCLK$PTI_Out" 2 1 0 0 0 0 1\r
1030 pin: 1 X_IC_9_CD4007.13\r
1031 pin: 2 RX$Xff$XXstiCLK$XXinv$RP.1\r
1032 connect: 1 1 0 1 0\r
1033 vtx: 1 -57277000 85267800 11 0 0 0 0\r
1034 seg: 1 6 0 0 0\r
1035 vtx: 2 -41706800 33909000 11 0 0 0 0\r
1036 \r
1037 net: "Xff$XSlave$_D" 3 2 0 0 0 0 1\r
1038 pin: 1 X_IC_8_CD4007.6\r
1039 pin: 2 RX$Xff$XSlave$XXstiD$XXinv$RP.2\r
1040 pin: 3 RX$Xff$XSlave$XXstiD$XXinv$RN.1\r
1041 connect: 1 2 1 1 0\r
1042 vtx: 1 -57277000 77647800 11 0 0 0 0\r
1043 seg: 1 6 0 0 0\r
1044 vtx: 2 -44577000 70027800 11 0 0 0 0\r
1045 connect: 2 1 0 1 0\r
1046 vtx: 1 -44577000 70027800 11 0 0 0 0\r
1047 seg: 1 6 0 0 0\r
1048 vtx: 2 -13766800 13589000 11 0 0 0 0\r
1049 \r
1050 net: "Q" 3 2 0 0 0 0 1\r
1051 pin: 1 X_IC_6_CD4007.3\r
1052 pin: 2 RX$Xff$XSlave$XXlatch$RP.2\r
1053 pin: 3 RX$Xff$XSlave$XXlatch$RN.1\r
1054 connect: 1 1 0 1 0\r
1055 vtx: 1 -26797000 115747800 11 0 0 0 0\r
1056 seg: 1 6 0 0 0\r
1057 vtx: 2 -16306800 107569000 11 0 0 0 0\r
1058 connect: 2 2 0 1 0\r
1059 vtx: 1 -44577000 1447800 11 0 0 0 0\r
1060 seg: 1 6 0 0 0\r
1061 vtx: 2 -16306800 107569000 11 0 0 0 0\r
1062 \r
1063 net: "Xff$XMaster$_D" 3 2 0 0 0 0 1\r
1064 pin: 1 X_IC_3_CD4007.6\r
1065 pin: 2 RX$Xff$XMaster$XXstiD$XXinv$RP.2\r
1066 pin: 3 RX$Xff$XMaster$XXstiD$XXinv$RN.1\r
1067 connect: 1 2 1 1 0\r
1068 vtx: 1 -39497000 108127800 11 0 0 0 0\r
1069 seg: 1 6 0 0 0\r
1070 vtx: 2 -26797000 100507800 11 0 0 0 0\r
1071 connect: 2 1 0 1 0\r
1072 vtx: 1 -26797000 100507800 11 0 0 0 0\r
1073 seg: 1 6 0 0 0\r
1074 vtx: 2 -8686800 69469000 11 0 0 0 0\r
1075 \r
1076 net: "Xff$XSlave$XXlatch$NI" 2 1 0 0 0 0 1\r
1077 pin: 1 X_IC_5_CD4007.4\r
1078 pin: 2 X_IC_5_CD4007.8\r
1079 connect: 1 1 0 1 0\r
1080 vtx: 1 -6146800 102489000 11 0 0 0 0\r
1081 seg: 1 6 0 0 0\r
1082 vtx: 2 -13766800 94869000 11 0 0 0 0\r
1083 \r
1084 net: "Xff$between" 5 4 0 0 0 0 1\r
1085 pin: 1 X_IC_1_CD4007.3\r
1086 pin: 2 X_IC_4_CD4007.3\r
1087 pin: 3 X_IC_7_CD4007.3\r
1088 pin: 4 RX$Xff$XMaster$XXlatch$RP.2\r
1089 pin: 5 RX$Xff$XMaster$XXlatch$RN.1\r
1090 connect: 1 3 0 1 0\r
1091 vtx: 1 -26797000 39547800 11 0 0 0 0\r
1092 seg: 1 6 0 0 0\r
1093 vtx: 2 -16306800 44069000 11 0 0 0 0\r
1094 connect: 2 4 3 1 0\r
1095 vtx: 1 -39497000 47167800 11 0 0 0 0\r
1096 seg: 1 6 0 0 0\r
1097 vtx: 2 -26797000 39547800 11 0 0 0 0\r
1098 connect: 3 1 0 1 0\r
1099 vtx: 1 -16306800 82169000 11 0 0 0 0\r
1100 seg: 1 6 0 0 0\r
1101 vtx: 2 -16306800 44069000 11 0 0 0 0\r
1102 connect: 4 3 2 1 0\r
1103 vtx: 1 -26797000 39547800 11 0 0 0 0\r
1104 seg: 1 6 0 0 0\r
1105 vtx: 2 -21386800 889000 11 0 0 0 0\r
1106 \r
1107 net: "0" 4 3 0 0 0 0 1\r
1108 pin: 1 Vclk.2\r
1109 pin: 2 Vd.2\r
1110 pin: 3 V$XX1$Vdd.2\r
1111 pin: 4 V$XX1$Vss.1\r
1112 connect: 1 3 2 1 0\r
1113 vtx: 1 -4241800 23698200 11 0 0 0 0\r
1114 seg: 1 6 0 0 0\r
1115 vtx: 2 -4241800 18618200 11 0 0 0 0\r
1116 connect: 2 1 0 1 0\r
1117 vtx: 1 -4241800 10998200 11 0 0 0 0\r
1118 seg: 1 6 0 0 0\r
1119 vtx: 2 -4241800 3378200 11 0 0 0 0\r
1120 connect: 3 2 1 1 0\r
1121 vtx: 1 -4241800 18618200 11 0 0 0 0\r
1122 seg: 1 6 0 0 0\r
1123 vtx: 2 -4241800 10998200 11 0 0 0 0\r
1124 \r
1125 net: "Xff$XMaster$Q_storage" 3 2 0 0 0 0 1\r
1126 pin: 1 X_IC_0_CD4007.3\r
1127 pin: 2 RX$Xff$XMaster$XXgatetop$RP.2\r
1128 pin: 3 RX$Xff$XMaster$XXgatetop$RN.1\r
1129 connect: 1 2 1 1 0\r
1130 vtx: 1 -39497000 77647800 11 0 0 0 0\r
1131 seg: 1 6 0 0 0\r
1132 vtx: 2 -26797000 70027800 11 0 0 0 0\r
1133 connect: 2 1 0 1 0\r
1134 vtx: 1 -26797000 70027800 11 0 0 0 0\r
1135 seg: 1 6 0 0 0\r
1136 vtx: 2 -16306800 31369000 11 0 0 0 0\r
1137 \r
1138 net: "Xff$XMaster$X_Xlatch$NN" 2 1 0 0 0 0 1\r
1139 pin: 1 X_IC_1_CD4007.9\r
1140 pin: 2 RX$Xff$XMaster$X_Xlatch$RN.2\r
1141 connect: 1 1 0 1 0\r
1142 vtx: 1 -26797000 62407800 11 0 0 0 0\r
1143 seg: 1 6 0 0 0\r
1144 vtx: 2 -8686800 51689000 11 0 0 0 0\r
1145 \r
1146 net: "CLK" 4 3 0 0 0 0 1\r
1147 pin: 1 Vclk.1\r
1148 pin: 2 X_IC_7_CD4007.6\r
1149 pin: 3 X_IC_8_CD4007.3\r
1150 pin: 4 X_IC_9_CD4007.6\r
1151 connect: 1 1 0 1 0\r
1152 vtx: 1 -13766800 889000 11 0 0 0 0\r
1153 seg: 1 6 0 0 0\r
1154 vtx: 2 -4241800 838200 11 0 0 0 0\r
1155 connect: 2 2 1 1 0\r
1156 vtx: 1 -21386800 13589000 11 0 0 0 0\r
1157 seg: 1 6 0 0 0\r
1158 vtx: 2 -13766800 889000 11 0 0 0 0\r
1159 connect: 3 3 2 1 0\r
1160 vtx: 1 -31546800 26289000 11 0 0 0 0\r
1161 seg: 1 6 0 0 0\r
1162 vtx: 2 -21386800 13589000 11 0 0 0 0\r
1163 \r
1164 net: "Xff$NC_01" 3 2 0 0 0 0 1\r
1165 pin: 1 X_IC_0_CD4007.6\r
1166 pin: 2 RX$Xff$XMaster$X_Xlatch$RP.2\r
1167 pin: 3 RX$Xff$XMaster$X_Xlatch$RN.1\r
1168 connect: 1 2 1 1 0\r
1169 vtx: 1 -39497000 62407800 11 0 0 0 0\r
1170 seg: 1 6 0 0 0\r
1171 vtx: 2 -26797000 54787800 11 0 0 0 0\r
1172 connect: 2 1 0 1 0\r
1173 vtx: 1 -26797000 54787800 11 0 0 0 0\r
1174 seg: 1 6 0 0 0\r
1175 vtx: 2 -8686800 31369000 11 0 0 0 0\r
1176 \r
1177 net: "Xff$XSlave$X_Xlatch$NI" 2 1 0 0 0 0 1\r
1178 pin: 1 X_IC_6_CD4007.4\r
1179 pin: 2 X_IC_6_CD4007.8\r
1180 connect: 1 1 0 1 0\r
1181 vtx: 1 -6146800 115189000 11 0 0 0 0\r
1182 seg: 1 6 0 0 0\r
1183 vtx: 2 -13766800 107569000 11 0 0 0 0\r
1184 \r
1185 [texts]\r
1186 \r
1187 [end]\r