Sign board: rearrange traces to pass design rule check.
[trinary.git] / bb / tnand.py
blob1e9ad769302a2e8fc0e42762ae0424e058e6164a
1 # Ternary NOR, implemented with CD4007
4 nodes = ("A", "B", "TNAND_Out")
6 # Dual MOSFET Complementary Pair + Binary Inverter
7 parts_generated = ["CD4007"]
8 parts_consumed = ["MP1", "MP2", "MN1", "MN2"]
9 parts_kept = ["RP", "RN"]
11 # Based on pinout from http://www.cedmagic.com/tech-info/data/cd4016.pdf
12 pins = [
14 "A": ("CD4007", 3),
15 "B": ("CD4007", 6),
16 "$G_Vdd": [("CD4007", 2), ("CD4007", 14)],
17 "TNOR_Out": "TNOR_Out",
18 "$G_Vss": ("CD4007", 7),
20 # Internal nodes
22 # Connect these two nodes together
23 "NI": [("CD4007", 4), ("CD4007", 8)],
24 # Connects to resistors
25 "NP": [("CD4007", 1), ("CD4007", 13)],
26 "NN": ("CD4007", 5),
30 # Always connected once if use once or more
31 global_pins = {
32 # TODO: always connect binary inverter, since we'll never be using it,
33 # but to prevent MOSFETs from switching on and off, wasting power?
34 # May need a change in this data structure to support multiple connections to $G_Vdd/Vss