Sign board: rearrange traces to pass design rule check.
[trinary.git] / bb / pcb.py
blobc14e666bab2b4efe8fe624322a225743040ddd9f
1 #!env python
2 # Created:20080516
3 # By Jeff Connelly
5 # Run chip mapper/PADS-PCB tool suite
7 import os, sys
9 if len(sys.argv) < 2:
10 print "usage: %s circuit-name" % (sys.argv[0])
11 print
12 print "Where circuit-name is an LTspice circuit name, which reads"
13 print "../circuits/<circuit-name>.net. The extension need not be "
14 print "given. To generate this file in LTspice, SPICE Netlist."
15 print
16 print "Output file is a .pads PADS-PCB netlist, you can import into"
17 print "FreePCB or other PCB layout programs."
18 raise SystemExit
20 name = sys.argv[1]
21 if "." in name:
22 print "You don't need to specify an extension. Try again."
23 raise SystemExit
24 netfile = "../circuits/%s.net" % (name,)
25 if not os.access(netfile, os.R_OK):
26 print "No such file: %s" % (netfile,)
27 if os.access("../circuits/%s.asc" % (name,), os.R_OK):
28 print "But the corresponding .asc file exists."
29 print "To generate .net, in LTspice go to: View -> SPICE Netlist."
30 raise SystemExit
31 if os.access("../circuit/%s.asy" % (name,), os.R_OK):
32 print "Warning! A corresponding symbol exists for this circuit!"
33 print "Are you sure it is the right circuit? Generally, PCBs should be"
34 print "made from *_test.asc files, not the components they test, so that"
35 print "power is supplied."
36 raise SystemExit
38 print "Found netlist: %s" % (netfile,)
40 if "-q" not in sys.argv:
41 # Get parameters on the circuit, to help with unique identifiers,
42 # so multiple circuits can easily be merged.
43 print "\nConfiguration Questions (to skip, pass -q next time)\n"
44 try:
45 os.environ["JC_CHIP_START"] = str(int(raw_input("Start chip numbering at: ")))
46 except ValueError:
47 print "(Using default)"
49 try:
50 os.environ["JC_RESISTOR_SERIAL_START"] = str(int(raw_input("Start resistor numbering at: ")))
51 except ValueError:
52 print "(Using default)"
54 try:
55 os.environ["JC_NETNAME_SUFFIX"] = raw_input("Netname suffix: ")
56 except ValueError:
57 print "(Using default)"
59 try:
60 os.environ["JC_USE_RESISTOR_CHIP"] = str(int(raw_input("Use resistor network or discrete resistors? (1=network, 0=discrete) ")))
61 except ValueError:
62 print "(Using default)"
64 # Copy here so files are saved locally, in 'bb' instead of 'circuits'
65 code = os.system("cp -v %s ." % (netfile,))
66 if code != 0:
67 print "Failed to copy netlist to current directory! Something is wrong."
68 raise SystemExit
69 code = os.system("python bb.py %s.net -p" % (name,))
70 if code != 0:
71 print "Failed!, see errors above. Exit code: %d" % (code,)
72 raise SystemExit
74 if os.access("%s.pads" % (name,), os.R_OK):
75 print "Your PADS-PCB netlist file is now available at %s.pads for importing into FreePCB." % (name,)
76 else:
77 print "Seems there was a problem generating %s.pads." % (name,)