1 * Z:\trinary\code\circuits\tnor_test.asc
\r
2 VA A 0 PWL file=INPUT_A.txt
\r
3 VB B 0 PWL file=INPUT_B.txt
\r
4 XX1 A B TNOR_Out tnor
\r
5 XX2 $G_Vdd $G_Vss tpower
\r
7 * block symbol definitions
\r
8 .subckt tnor A B TNOR_Out
\r
11 MN1 NN A $G_Vss $G_Vss CD4007N
\r
12 MP2 NI A $G_Vdd $G_Vdd CD4007P
\r
13 MN2 NN B $G_Vss $G_Vss CD4007N
\r
14 MP1 NI B NP $G_Vdd CD4007P
\r
17 .subckt tpower Vdd Vss
\r
24 .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
\r