5 WIRE 176 -304 96 -304
\r
6 WIRE 416 -304 336 -304
\r
7 WIRE 176 -256 144 -256
\r
11 WIRE 416 -96 336 -96
\r
12 WIRE 144 -48 144 -256
\r
13 WIRE 176 -48 144 -48
\r
16 WIRE 176 112 112 112
\r
17 WIRE 416 112 336 112
\r
18 WIRE 144 160 144 -48
\r
19 WIRE 144 160 112 160
\r
20 WIRE 176 160 144 160
\r
22 WIRE 112 208 112 160
\r
30 FLAG -320 224 $G_Vdd
\r
31 FLAG -320 288 $G_Vss
\r
36 SYMBOL voltage 112 192 R0
\r
37 WINDOW 123 0 0 Left 0
\r
38 WINDOW 39 0 0 Left 0
\r
39 WINDOW 0 2 14 Left 0
\r
40 SYMATTR InstName Vclk
\r
41 SYMATTR Value PULSE(5 -5 0 1p 1p 10n 20n)
\r
42 SYMBOL voltage 0 192 R0
\r
43 WINDOW 3 -45 164 Left 0
\r
44 WINDOW 123 0 0 Left 0
\r
45 WINDOW 39 0 0 Left 0
\r
46 SYMATTR Value PWL(0 0 7n 0 8n 5 17n 5 18n 0 24n 0 25n -5 34n -5 35n 5)
\r
48 SYMBOL tpower -320 256 R0
\r
50 SYMBOL dtflop-msmo 256 64 R0
\r
51 SYMATTR InstName Xtrit0
\r
52 SYMBOL dtflop-msmo 256 -144 R0
\r
53 SYMATTR InstName Xtrit1
\r
54 SYMBOL dtflop-msmo 256 -352 R0
\r
55 SYMATTR InstName Xtrit2
\r
56 SYMBOL sti 48 -304 R0
\r
57 SYMATTR InstName Xinv
\r
58 TEXT 216 248 Left 0 !.tran 50n
\r
59 TEXT 496 -16 Left 0 ;Compare this with trit_reg3_test, which uses dtflop-ms2.\n \n1) dtflop-msmo starts off at _1, while dtflop-ms2 starts at 0\n2) In some cases, dtflop-msmo may take two clock cycles to\ntransition between 1 and _1, the first cycle latching in 0.\nThis has been observed in lab. For more information, see:\n \nhttp://jeff.tk/wiki/Trinary/Circuits#Rising_Edge-Triggered_Master-Slave_D_Tri-Flop:_Mouftah.27s_version
\r