1 * Z:\trinary\code\circuits\dtflop-ms_test.asc
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2 Vclk CLK 0 PULSE(-5 5 0 1p 1p 10n 20n)
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3 Vd D 0 PWL(0 0 1n 0 5n -5 8n -5 9n 0 10n 0 11n 5 21n 5 22n 0 24n 0 25n -5 34n -5 35n -5 40n -5 41n -5 42n 0 43n 5 44n 5 45n -5 46n 0 47n -5 48n 0)
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4 XX1 $G_Vdd $G_Vss tpower
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5 Xflipflop D CLK Q dtflop-ms
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7 * block symbol definitions
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8 .subckt tpower Vdd Vss
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13 .subckt dtflop-ms D C Q
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14 XX2 tg_master _Q_master sti
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15 XX4 tg_D tg_master sti
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18 XXB _Q_master tg_D C tg
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19 XXC tg_slave tg_master C tg
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21 XXD _Q_slave tg_slave _C tg
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26 Xinv IN NC_01 OUT NC_02 tinv
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29 .subckt tg IN_OUT OUT_IN CONTROL
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30 M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
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31 M2 IN_OUT C OUT_IN $G_Vss CD4007N
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32 M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
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33 M4 _C CONTROL $G_Vss $G_Vss CD4007N
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34 M5 $G_Vdd _C C $G_Vdd CD4007P
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35 M6 C _C $G_Vss $G_Vss CD4007N
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38 .subckt tinv Vin PTI_Out STI_Out NTI_Out
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39 RP PTI_Out STI_Out 12k
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40 RN STI_Out NTI_Out 12k
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41 MN NTI_Out Vin $G_Vss $G_Vss CD4007N
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42 MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
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47 .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
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