1 * Z:\trinary\code\circuits\mux3-1_test.asc
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2 V1 A 0 SINE(0 5 200Meg)
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3 V2 B 0 SINE(0 5 1000Meg)
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4 V3 C 0 PULSE(-5 5 0n 1p 1p 3n 6n)
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5 V4 S 0 PWL(0 -5 14n -5 15n 0 29n 0 30n 5)
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6 XX11 $G_Vdd $G_Vss tpower
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9 * block symbol definitions
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10 .subckt tpower Vdd Vss
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15 .subckt mux3-1 A B C S Q
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19 XX4 S N001 N003 N002 decoder3-1
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22 .subckt tg IN_OUT OUT_IN CONTROL
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23 M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
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24 M2 IN_OUT N003 OUT_IN $G_Vss CD4007N
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25 M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
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26 M4 _C CONTROL $G_Vss $G_Vss CD4007N
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27 M5 $G_Vdd _C N003 $G_Vdd CD4007P
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28 M6 N003 _C $G_Vss $G_Vss CD4007N
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31 .subckt decoder3-1 IN OUT_i OUT_0 OUT_1
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37 XX3 IN N002 N001 max
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41 XX1 IN OUT NC_01 NC_02 tinv
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45 XX1 IN NC_01 NC_02 OUT tinv
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49 XX1 IN NC_01 OUT NC_02 tinv
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52 .subckt max A B MAX_OUT
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54 XX2 P001 MAX_OUT sti
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57 .subckt tinv Vin PTI_Out STI_Out NTI_Out
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58 RP PTI_Out STI_Out 12k
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59 RN STI_Out NTI_Out 12k
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60 MN NTI_Out Vin $G_Vss $G_Vss CD4007N
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61 MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
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64 .subckt tnor A B TNOR_Out
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65 RP N002 TNOR_Out 12k
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66 RN TNOR_Out N003 12k
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67 MN1 N003 A $G_Vss $G_Vss CD4007N
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68 MP2 N001 A $G_Vdd $G_Vdd CD4007P
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69 MN2 N003 B $G_Vss $G_Vss CD4007N
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70 MP1 N001 B N002 $G_Vdd CD4007P
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75 .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
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