1 * Z:\trinary\code\circuits\half_adder_test.asc
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2 XX1 $G_Vdd $G_Vss tpower
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3 VA A 0 PWL file=INPUT_A.txt
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4 VB B 0 PWL file=INPUT_B.txt
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5 XXadder A C S B half_adder
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7 * block symbol definitions
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8 .subckt tpower Vdd Vss
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13 .subckt half_adder A C S B
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14 XXmux_carry1 N001 0 N002 B C mux3-1
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15 XXmux_sum1 N003 A N004 B S mux3-1
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16 XXcd A N003 tcycle_down
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17 XXsu A N004 shift_up
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22 .subckt mux3-1 A B C S Q
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26 XXdecoder S CTRL_A CTRL_B CTRL_C decoder3-1
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29 .subckt tcycle_down IN OUT
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30 XXtnand1 _IN_PTI INI OUT tnand
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31 XXtnand0 _IN_NTI 0 INI tnand
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32 XXnti _IN _IN_NTI nti
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33 XXpti _IN _IN_PTI pti
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37 .subckt shift_up IN OUT
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38 D§Xrd N002 N001 1N4148
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54 .subckt tg IN_OUT OUT_IN CONTROL
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55 M1 OUT_IN _C IN_OUT $G_Vdd CD4007P
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56 M2 IN_OUT C OUT_IN $G_Vss CD4007N
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57 M3 $G_Vdd CONTROL _C $G_Vdd CD4007P
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58 M4 _C CONTROL $G_Vss $G_Vss CD4007N
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59 M5 $G_Vdd _C C $G_Vdd CD4007P
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60 M6 C _C $G_Vss $G_Vss CD4007N
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63 .subckt decoder3-1 IN OUT_i OUT_0 OUT_1
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65 XXPpti2 NP OUT_1 pti
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67 XXZpti NZtnand OUT_0 pti
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69 XXZtnand IN NZsti NZtnand max
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72 .subckt tnand A B TNAND_Out
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75 MP1 NP B $G_Vdd $G_Vdd CD4007P
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76 MP2 NP A $G_Vdd $G_Vdd CD4007P
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77 MN2 NI B $G_Vss $G_Vss CD4007N
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78 MN1 NN A NI $G_Vss CD4007N
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82 Xinv IN NC_01 NC_02 OUT tinv
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86 Xinv IN OUT NC_01 NC_02 tinv
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90 XXinv IN NC_01 OUT NC_02 tinv
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93 .subckt max A B MAX_OUT
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94 XXtnor A B AtnorB tnor
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95 XXsti_tor AtnorB MAX_OUT sti
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98 .subckt tinv Vin PTI_Out STI_Out NTI_Out
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99 RP PTI_Out STI_Out 12k
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100 RN STI_Out NTI_Out 12k
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101 MN NTI_Out Vin $G_Vss $G_Vss CD4007N
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102 MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
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105 .subckt tnor A B TNOR_Out
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108 MN1 NN A $G_Vss $G_Vss CD4007N
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109 MP2 NI A $G_Vdd $G_Vdd CD4007P
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110 MN2 NN B $G_Vss $G_Vss CD4007N
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111 MP1 NI B NP $G_Vdd CD4007P
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115 .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.dio
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118 .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos
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