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Update and clean Tomato RAF files
[tomato.git] / release / src / include / sbconfig.h
bloba6cd07425d9ea55d83d2d619bb0687a0be1e1b8f
1 /*
2 * Broadcom SiliconBackplane hardware register definitions.
3 *
4 * Copyright 2006, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 *
12 * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
13 */
14
15 #ifndef _SBCONFIG_H
16 #define _SBCONFIG_H
17
18 /* cpp contortions to concatenate w/arg prescan */
19 #ifndef PAD
20 #define _PADLINE(line) pad ## line
21 #define _XSTR(line) _PADLINE(line)
22 #define PAD _XSTR(__LINE__)
23 #endif
24
25 /*
26 * SiliconBackplane Address Map.
27 * All regions may not exist on all chips.
28 */
29 #define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
30 #define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
31 #define SB_PCI_MEM_SZ (64 * 1024 * 1024)
32 #define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
33 #define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
34 #define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
35 #define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
36
37 #define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
38 #define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
39 #define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
40 #define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
41 #define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
42 #define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
43 #define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
44 #define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
45 #define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
46 #define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
47
48 #define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
49 #define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
50 #define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
51 * (2 ZettaBytes), low 32 bits
52 */
53 #define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
54 * (2 ZettaBytes), high 32 bits
55 */
56
57 /* enumeration space related defs */
58 #define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
59 #define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
60 #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
61 #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
62
63 /* mips address */
64 #define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
65
66 /*
67 * Sonics Configuration Space Registers.
68 */
69 #define SBIPSFLAG 0x08
70 #define SBTPSFLAG 0x18
71 #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
72 #define SBTMERRLOG 0x50 /* sonics >= 2.3 */
73 #define SBADMATCH3 0x60
74 #define SBADMATCH2 0x68
75 #define SBADMATCH1 0x70
76 #define SBIMSTATE 0x90
77 #define SBINTVEC 0x94
78 #define SBTMSTATELOW 0x98
79 #define SBTMSTATEHIGH 0x9c
80 #define SBBWA0 0xa0
81 #define SBIMCONFIGLOW 0xa8
82 #define SBIMCONFIGHIGH 0xac
83 #define SBADMATCH0 0xb0
84 #define SBTMCONFIGLOW 0xb8
85 #define SBTMCONFIGHIGH 0xbc
86 #define SBBCONFIG 0xc0
87 #define SBBSTATE 0xc8
88 #define SBACTCNFG 0xd8
89 #define SBFLAGST 0xe8
90 #define SBIDLOW 0xf8
91 #define SBIDHIGH 0xfc
92
93 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
94 * a few registers *below* that line. I think it would be very confusing to try
95 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
96 */
97
98 #define SBIMERRLOGA 0xea8
99 #define SBIMERRLOG 0xeb0
100 #define SBTMPORTCONNID0 0xed8
101 #define SBTMPORTLOCK0 0xef8
102
103 #ifndef _LANGUAGE_ASSEMBLY
104
105 typedef volatile struct _sbconfig {
106 uint32 PAD[2];
107 uint32 sbipsflag; /* initiator port ocp slave flag */
108 uint32 PAD[3];
109 uint32 sbtpsflag; /* target port ocp slave flag */
110 uint32 PAD[11];
111 uint32 sbtmerrloga; /* (sonics >= 2.3) */
112 uint32 PAD;
113 uint32 sbtmerrlog; /* (sonics >= 2.3) */
114 uint32 PAD[3];
115 uint32 sbadmatch3; /* address match3 */
116 uint32 PAD;
117 uint32 sbadmatch2; /* address match2 */
118 uint32 PAD;
119 uint32 sbadmatch1; /* address match1 */
120 uint32 PAD[7];
121 uint32 sbimstate; /* initiator agent state */
122 uint32 sbintvec; /* interrupt mask */
123 uint32 sbtmstatelow; /* target state */
124 uint32 sbtmstatehigh; /* target state */
125 uint32 sbbwa0; /* bandwidth allocation table0 */
126 uint32 PAD;
127 uint32 sbimconfiglow; /* initiator configuration */
128 uint32 sbimconfighigh; /* initiator configuration */
129 uint32 sbadmatch0; /* address match0 */
130 uint32 PAD;
131 uint32 sbtmconfiglow; /* target configuration */
132 uint32 sbtmconfighigh; /* target configuration */
133 uint32 sbbconfig; /* broadcast configuration */
134 uint32 PAD;
135 uint32 sbbstate; /* broadcast state */
136 uint32 PAD[3];
137 uint32 sbactcnfg; /* activate configuration */
138 uint32 PAD[3];
139 uint32 sbflagst; /* current sbflags */
140 uint32 PAD[3];
141 uint32 sbidlow; /* identification */
142 uint32 sbidhigh; /* identification */
143 } sbconfig_t;
144
145 #endif /* _LANGUAGE_ASSEMBLY */
146
147 /* sbipsflag */
148 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
149 #define SBIPS_INT1_SHIFT 0
150 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
151 #define SBIPS_INT2_SHIFT 8
152 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
153 #define SBIPS_INT3_SHIFT 16
154 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
155 #define SBIPS_INT4_SHIFT 24
156
157 /* sbtpsflag */
158 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
159 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
160
161 /* sbtmerrlog */
162 #define SBTMEL_CM 0x00000007 /* command */
163 #define SBTMEL_CI 0x0000ff00 /* connection id */
164 #define SBTMEL_EC 0x0f000000 /* error code */
165 #define SBTMEL_ME 0x80000000 /* multiple error */
166
167 /* sbimstate */
168 #define SBIM_PC 0xf /* pipecount */
169 #define SBIM_AP_MASK 0x30 /* arbitration policy */
170 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
171 #define SBIM_AP_TS 0x10 /* use timesliaces only */
172 #define SBIM_AP_TK 0x20 /* use token only */
173 #define SBIM_AP_RSV 0x30 /* reserved */
174 #define SBIM_IBE 0x20000 /* inbanderror */
175 #define SBIM_TO 0x40000 /* timeout */
176 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
177 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
178
179 /* sbtmstatelow */
180 #define SBTML_RESET 0x1 /* reset */
181 #define SBTML_REJ_MASK 0x6 /* reject */
182 #define SBTML_REJ_SHIFT 1
183 #define SBTML_CLK 0x10000 /* clock enable */
184 #define SBTML_FGC 0x20000 /* force gated clocks on */
185 #define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
186 #define SBTML_PE 0x40000000 /* pme enable */
187 #define SBTML_BE 0x80000000 /* bist enable */
188
189 /* sbtmstatehigh */
190 #define SBTMH_SERR 0x1 /* serror */
191 #define SBTMH_INT 0x2 /* interrupt */
192 #define SBTMH_BUSY 0x4 /* busy */
193 #define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
194 #define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */
195 #define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
196 #define SBTMH_GCR 0x20000000 /* gated clock request */
197 #define SBTMH_BISTF 0x40000000 /* bist failed */
198 #define SBTMH_BISTD 0x80000000 /* bist done */
199
200 /* sbbwa0 */
201 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
202 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
203 #define SBBWA_TAB1_SHIFT 16
204
205 /* sbimconfiglow */
206 #define SBIMCL_STO_MASK 0x7 /* service timeout */
207 #define SBIMCL_RTO_MASK 0x70 /* request timeout */
208 #define SBIMCL_RTO_SHIFT 4
209 #define SBIMCL_CID_MASK 0xff0000 /* connection id */
210 #define SBIMCL_CID_SHIFT 16
211
212 /* sbimconfighigh */
213 #define SBIMCH_IEM_MASK 0xc /* inband error mode */
214 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
215 #define SBIMCH_TEM_SHIFT 4
216 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
217 #define SBIMCH_BEM_SHIFT 6
218
219 /* sbadmatch0 */
220 #define SBAM_TYPE_MASK 0x3 /* address type */
221 #define SBAM_AD64 0x4 /* reserved */
222 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */
223 #define SBAM_ADINT0_SHIFT 3
224 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
225 #define SBAM_ADINT1_SHIFT 3
226 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
227 #define SBAM_ADINT2_SHIFT 3
228 #define SBAM_ADEN 0x400 /* enable */
229 #define SBAM_ADNEG 0x800 /* negative decode */
230 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
231 #define SBAM_BASE0_SHIFT 8
232 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
233 #define SBAM_BASE1_SHIFT 12
234 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
235 #define SBAM_BASE2_SHIFT 16
236
237 /* sbtmconfiglow */
238 #define SBTMCL_CD_MASK 0xff /* clock divide */
239 #define SBTMCL_CO_MASK 0xf800 /* clock offset */
240 #define SBTMCL_CO_SHIFT 11
241 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
242 #define SBTMCL_IF_SHIFT 18
243 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
244 #define SBTMCL_IM_SHIFT 24
245
246 /* sbtmconfighigh */
247 #define SBTMCH_BM_MASK 0x3 /* busy mode */
248 #define SBTMCH_RM_MASK 0x3 /* retry mode */
249 #define SBTMCH_RM_SHIFT 2
250 #define SBTMCH_SM_MASK 0x30 /* stop mode */
251 #define SBTMCH_SM_SHIFT 4
252 #define SBTMCH_EM_MASK 0x300 /* sb error mode */
253 #define SBTMCH_EM_SHIFT 8
254 #define SBTMCH_IM_MASK 0xc00 /* int mode */
255 #define SBTMCH_IM_SHIFT 10
256
257 /* sbbconfig */
258 #define SBBC_LAT_MASK 0x3 /* sb latency */
259 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
260 #define SBBC_MAX0_SHIFT 16
261 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
262 #define SBBC_MAX1_SHIFT 20
263
264 /* sbbstate */
265 #define SBBS_SRD 0x1 /* st reg disable */
266 #define SBBS_HRD 0x2 /* hold reg disable */
267
268 /* sbidlow */
269 #define SBIDL_CS_MASK 0x3 /* config space */
270 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */
271 #define SBIDL_AR_SHIFT 3
272 #define SBIDL_SYNCH 0x40 /* sync */
273 #define SBIDL_INIT 0x80 /* initiator */
274 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
275 #define SBIDL_MINLAT_SHIFT 8
276 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
277 #define SBIDL_MAXLAT_SHIFT 12
278 #define SBIDL_FIRST 0x10000 /* this initiator is first */
279 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
280 #define SBIDL_CW_SHIFT 18
281 #define SBIDL_TP_MASK 0xf00000 /* target ports */
282 #define SBIDL_TP_SHIFT 20
283 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */
284 #define SBIDL_IP_SHIFT 24
285 #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
286 #define SBIDL_RV_SHIFT 28
287 #define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
288 #define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
289
290 /* sbidhigh */
291 #define SBIDH_RC_MASK 0x000f /* revision code */
292 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
293 #define SBIDH_RCE_SHIFT 8
294 #define SBCOREREV(sbidh) \
295 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
296 #define SBIDH_CC_MASK 0x8ff0 /* core code */
297 #define SBIDH_CC_SHIFT 4
298 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
299 #define SBIDH_VC_SHIFT 16
300
301 #define SB_COMMIT 0xfd8 /* update buffered registers value */
302
303 /* vendor codes */
304 #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
305
306 /* core codes */
307 #define SB_NODEV 0x700 /* Invalid coreid */
308 #define SB_CC 0x800 /* chipcommon core */
309 #define SB_ILINE20 0x801 /* iline20 core */
310 #define SB_SDRAM 0x803 /* sdram core */
311 #define SB_PCI 0x804 /* pci core */
312 #define SB_MIPS 0x805 /* mips core */
313 #define SB_ENET 0x806 /* enet mac core */
314 #define SB_CODEC 0x807 /* v90 codec core */
315 #define SB_USB 0x808 /* usb 1.1 host/device core */
316 #define SB_ADSL 0x809 /* ADSL core */
317 #define SB_ILINE100 0x80a /* iline100 core */
318 #define SB_IPSEC 0x80b /* ipsec core */
319 #define SB_PCMCIA 0x80d /* pcmcia core */
320 #define SB_SOCRAM 0x80e /* internal memory core */
321 #define SB_MEMC 0x80f /* memc sdram core */
322 #define SB_EXTIF 0x811 /* external interface core */
323 #define SB_D11 0x812 /* 802.11 MAC core */
324 #define SB_MIPS33 0x816 /* mips3302 core */
325 #define SB_USB11H 0x817 /* usb 1.1 host core */
326 #define SB_USB11D 0x818 /* usb 1.1 device core */
327 #define SB_USB20H 0x819 /* usb 2.0 host core */
328 #define SB_USB20D 0x81a /* usb 2.0 device core */
329 #define SB_SDIOH 0x81b /* sdio host core */
330 #define SB_ROBO 0x81c /* roboswitch core */
331 #define SB_ATA100 0x81d /* parallel ATA core */
332 #define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
333 #define SB_GIGETH 0x81f /* gigabit ethernet core */
334 #define SB_PCIE 0x820 /* pci express core */
335 #define SB_MIMO 0x821 /* MIMO phy core */
336 #define SB_SRAMC 0x822 /* SRAM controller core */
337 #define SB_MINIMAC 0x823 /* MINI MAC/phy core */
338 #define SB_ARM11 0x824 /* ARM 1176 core */
339 #define SB_ARM7S 0x825 /* ARM7tdmi-s core */
340 #define SB_SDIOD 0x829 /* SDIO device core */
341 #define SB_ARMCM3 0x82a /* ARM Cortex M3 core */
342 #define SB_OCP 0x830 /* OCP2OCP bridge core */
343 #define SB_SC 0x831 /* shared common core */
344 #define SB_AHB 0x832 /* OCP2AHB bridge core */
345
346 #define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
347
348 /* Not an enumeration space register, but common to all cores to
349 * communicate w/PMU regarding Silicon Backplane clocking.
350 */
351 #define SB_CLK_CTL_ST 0x1e0 /* clock control and status */
352
353 /* clk_ctl_st register */
354 #define CCS_FORCEALP 0x00000001 /* force ALP request */
355 #define CCS_FORCEHT 0x00000002 /* force HT request */
356 #define CCS_FORCEILP 0x00000004 /* force ILP request */
357 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
358 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
359 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
360 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
361 #define CCS_HTAVAIL 0x00020000 /* HT is available */
362 #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
363 #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
364
365 /* Not really related to Silicon Backplane, but a couple of software
366 * conventions for the use the flash space:
367 */
368
369 /* Minumum amount of flash we support */
370 #define FLASH_MIN 0x00020000 /* Minimum flash size */
371
372 /* A boot/binary may have an embedded block that describes its size */
373 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
374 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
375 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */
376 #define BISZ_TXTST_IDX 1 /* 1: text start */
377 #define BISZ_TXTEND_IDX 2 /* 2: text end */
378 #define BISZ_DATAST_IDX 3 /* 3: data start */
379 #define BISZ_DATAEND_IDX 4 /* 4: data end */
380 #define BISZ_BSSST_IDX 5 /* 5: bss start */
381 #define BISZ_BSSEND_IDX 6 /* 6: bss end */
382 #define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
383
384 #endif /* _SBCONFIG_H */
Tomato firmware and modifications.