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Tomato 1.28
[tomato.git] / release / src / include / sbconfig.h
blobe9334c04ccc1de48560bdc587aab5d153b8a8075
1 /*
2 * Broadcom SiliconBackplane hardware register definitions.
3 *
4 * Copyright 2005, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 * $Id: sbconfig.h,v 1.1.1.9 2005/03/07 07:31:12 kanki Exp $
12 */
13
14 #ifndef _SBCONFIG_H
15 #define _SBCONFIG_H
16
17 /* cpp contortions to concatenate w/arg prescan */
18 #ifndef PAD
19 #define _PADLINE(line) pad ## line
20 #define _XSTR(line) _PADLINE(line)
21 #define PAD _XSTR(__LINE__)
22 #endif
23
24 /*
25 * SiliconBackplane Address Map.
26 * All regions may not exist on all chips.
27 */
28 #define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
29 #define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
30 #define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
31 #define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
32 #define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
33 #define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
34
35 #define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
36 #define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
37
38 #define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
39 #define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
40 #define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
41
42 #define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
43 #define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
44 #define SB_EUART (SB_EXTIF_BASE + 0x00800000)
45 #define SB_LED (SB_EXTIF_BASE + 0x00900000)
46
47 /* enumeration space related defs */
48 #define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
49 #define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
50 #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
51 #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
52
53 /* mips address */
54 #define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
55
56 /*
57 * Sonics Configuration Space Registers.
58 */
59 #define SBIPSFLAG 0x08
60 #define SBTPSFLAG 0x18
61 #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
62 #define SBTMERRLOG 0x50 /* sonics >= 2.3 */
63 #define SBADMATCH3 0x60
64 #define SBADMATCH2 0x68
65 #define SBADMATCH1 0x70
66 #define SBIMSTATE 0x90
67 #define SBINTVEC 0x94
68 #define SBTMSTATELOW 0x98
69 #define SBTMSTATEHIGH 0x9c
70 #define SBBWA0 0xa0
71 #define SBIMCONFIGLOW 0xa8
72 #define SBIMCONFIGHIGH 0xac
73 #define SBADMATCH0 0xb0
74 #define SBTMCONFIGLOW 0xb8
75 #define SBTMCONFIGHIGH 0xbc
76 #define SBBCONFIG 0xc0
77 #define SBBSTATE 0xc8
78 #define SBACTCNFG 0xd8
79 #define SBFLAGST 0xe8
80 #define SBIDLOW 0xf8
81 #define SBIDHIGH 0xfc
82
83 #ifndef _LANGUAGE_ASSEMBLY
84
85 typedef volatile struct _sbconfig {
86 uint32 PAD[2];
87 uint32 sbipsflag; /* initiator port ocp slave flag */
88 uint32 PAD[3];
89 uint32 sbtpsflag; /* target port ocp slave flag */
90 uint32 PAD[11];
91 uint32 sbtmerrloga; /* (sonics >= 2.3) */
92 uint32 PAD;
93 uint32 sbtmerrlog; /* (sonics >= 2.3) */
94 uint32 PAD[3];
95 uint32 sbadmatch3; /* address match3 */
96 uint32 PAD;
97 uint32 sbadmatch2; /* address match2 */
98 uint32 PAD;
99 uint32 sbadmatch1; /* address match1 */
100 uint32 PAD[7];
101 uint32 sbimstate; /* initiator agent state */
102 uint32 sbintvec; /* interrupt mask */
103 uint32 sbtmstatelow; /* target state */
104 uint32 sbtmstatehigh; /* target state */
105 uint32 sbbwa0; /* bandwidth allocation table0 */
106 uint32 PAD;
107 uint32 sbimconfiglow; /* initiator configuration */
108 uint32 sbimconfighigh; /* initiator configuration */
109 uint32 sbadmatch0; /* address match0 */
110 uint32 PAD;
111 uint32 sbtmconfiglow; /* target configuration */
112 uint32 sbtmconfighigh; /* target configuration */
113 uint32 sbbconfig; /* broadcast configuration */
114 uint32 PAD;
115 uint32 sbbstate; /* broadcast state */
116 uint32 PAD[3];
117 uint32 sbactcnfg; /* activate configuration */
118 uint32 PAD[3];
119 uint32 sbflagst; /* current sbflags */
120 uint32 PAD[3];
121 uint32 sbidlow; /* identification */
122 uint32 sbidhigh; /* identification */
123 } sbconfig_t;
124
125 #endif /* _LANGUAGE_ASSEMBLY */
126
127 /* sbipsflag */
128 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
129 #define SBIPS_INT1_SHIFT 0
130 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
131 #define SBIPS_INT2_SHIFT 8
132 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
133 #define SBIPS_INT3_SHIFT 16
134 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
135 #define SBIPS_INT4_SHIFT 24
136
137 /* sbtpsflag */
138 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
139 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
140
141 /* sbtmerrlog */
142 #define SBTMEL_CM 0x00000007 /* command */
143 #define SBTMEL_CI 0x0000ff00 /* connection id */
144 #define SBTMEL_EC 0x0f000000 /* error code */
145 #define SBTMEL_ME 0x80000000 /* multiple error */
146
147 /* sbimstate */
148 #define SBIM_PC 0xf /* pipecount */
149 #define SBIM_AP_MASK 0x30 /* arbitration policy */
150 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
151 #define SBIM_AP_TS 0x10 /* use timesliaces only */
152 #define SBIM_AP_TK 0x20 /* use token only */
153 #define SBIM_AP_RSV 0x30 /* reserved */
154 #define SBIM_IBE 0x20000 /* inbanderror */
155 #define SBIM_TO 0x40000 /* timeout */
156 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
157 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
158
159 /* sbtmstatelow */
160 #define SBTML_RESET 0x1 /* reset */
161 #define SBTML_REJ 0x2 /* reject */
162 #define SBTML_CLK 0x10000 /* clock enable */
163 #define SBTML_FGC 0x20000 /* force gated clocks on */
164 #define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
165 #define SBTML_PE 0x40000000 /* pme enable */
166 #define SBTML_BE 0x80000000 /* bist enable */
167
168 /* sbtmstatehigh */
169 #define SBTMH_SERR 0x1 /* serror */
170 #define SBTMH_INT 0x2 /* interrupt */
171 #define SBTMH_BUSY 0x4 /* busy */
172 #define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
173 #define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
174 #define SBTMH_GCR 0x20000000 /* gated clock request */
175 #define SBTMH_BISTF 0x40000000 /* bist failed */
176 #define SBTMH_BISTD 0x80000000 /* bist done */
177
178 /* sbbwa0 */
179 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
180 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
181 #define SBBWA_TAB1_SHIFT 16
182
183 /* sbimconfiglow */
184 #define SBIMCL_STO_MASK 0x7 /* service timeout */
185 #define SBIMCL_RTO_MASK 0x70 /* request timeout */
186 #define SBIMCL_RTO_SHIFT 4
187 #define SBIMCL_CID_MASK 0xff0000 /* connection id */
188 #define SBIMCL_CID_SHIFT 16
189
190 /* sbimconfighigh */
191 #define SBIMCH_IEM_MASK 0xc /* inband error mode */
192 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
193 #define SBIMCH_TEM_SHIFT 4
194 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
195 #define SBIMCH_BEM_SHIFT 6
196
197 /* sbadmatch0 */
198 #define SBAM_TYPE_MASK 0x3 /* address type */
199 #define SBAM_AD64 0x4 /* reserved */
200 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */
201 #define SBAM_ADINT0_SHIFT 3
202 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
203 #define SBAM_ADINT1_SHIFT 3
204 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
205 #define SBAM_ADINT2_SHIFT 3
206 #define SBAM_ADEN 0x400 /* enable */
207 #define SBAM_ADNEG 0x800 /* negative decode */
208 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
209 #define SBAM_BASE0_SHIFT 8
210 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
211 #define SBAM_BASE1_SHIFT 12
212 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
213 #define SBAM_BASE2_SHIFT 16
214
215 /* sbtmconfiglow */
216 #define SBTMCL_CD_MASK 0xff /* clock divide */
217 #define SBTMCL_CO_MASK 0xf800 /* clock offset */
218 #define SBTMCL_CO_SHIFT 11
219 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
220 #define SBTMCL_IF_SHIFT 18
221 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
222 #define SBTMCL_IM_SHIFT 24
223
224 /* sbtmconfighigh */
225 #define SBTMCH_BM_MASK 0x3 /* busy mode */
226 #define SBTMCH_RM_MASK 0x3 /* retry mode */
227 #define SBTMCH_RM_SHIFT 2
228 #define SBTMCH_SM_MASK 0x30 /* stop mode */
229 #define SBTMCH_SM_SHIFT 4
230 #define SBTMCH_EM_MASK 0x300 /* sb error mode */
231 #define SBTMCH_EM_SHIFT 8
232 #define SBTMCH_IM_MASK 0xc00 /* int mode */
233 #define SBTMCH_IM_SHIFT 10
234
235 /* sbbconfig */
236 #define SBBC_LAT_MASK 0x3 /* sb latency */
237 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
238 #define SBBC_MAX0_SHIFT 16
239 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
240 #define SBBC_MAX1_SHIFT 20
241
242 /* sbbstate */
243 #define SBBS_SRD 0x1 /* st reg disable */
244 #define SBBS_HRD 0x2 /* hold reg disable */
245
246 /* sbidlow */
247 #define SBIDL_CS_MASK 0x3 /* config space */
248 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */
249 #define SBIDL_AR_SHIFT 3
250 #define SBIDL_SYNCH 0x40 /* sync */
251 #define SBIDL_INIT 0x80 /* initiator */
252 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
253 #define SBIDL_MINLAT_SHIFT 8
254 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
255 #define SBIDL_MAXLAT_SHIFT 12
256 #define SBIDL_FIRST 0x10000 /* this initiator is first */
257 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
258 #define SBIDL_CW_SHIFT 18
259 #define SBIDL_TP_MASK 0xf00000 /* target ports */
260 #define SBIDL_TP_SHIFT 20
261 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */
262 #define SBIDL_IP_SHIFT 24
263 #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
264 #define SBIDL_RV_SHIFT 28
265
266 /* sbidhigh */
267 #define SBIDH_RC_MASK 0xf /* revision code*/
268 #define SBIDH_CC_MASK 0xfff0 /* core code */
269 #define SBIDH_CC_SHIFT 4
270 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
271 #define SBIDH_VC_SHIFT 16
272
273 #define SB_COMMIT 0xfd8 /* update buffered registers value */
274
275 /* vendor codes */
276 #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
277
278 /* core codes */
279 #define SB_CC 0x800 /* chipcommon core */
280 #define SB_ILINE20 0x801 /* iline20 core */
281 #define SB_SDRAM 0x803 /* sdram core */
282 #define SB_PCI 0x804 /* pci core */
283 #define SB_MIPS 0x805 /* mips core */
284 #define SB_ENET 0x806 /* enet mac core */
285 #define SB_CODEC 0x807 /* v90 codec core */
286 #define SB_USB 0x808 /* usb 1.1 host/device core */
287 #define SB_ADSL 0x809 /* ADSL core */
288 #define SB_ILINE100 0x80a /* iline100 core */
289 #define SB_IPSEC 0x80b /* ipsec core */
290 #define SB_PCMCIA 0x80d /* pcmcia core */
291 #define SB_SOCRAM 0x80e /* internal memory core */
292 #define SB_MEMC 0x80f /* memc sdram core */
293 #define SB_EXTIF 0x811 /* external interface core */
294 #define SB_D11 0x812 /* 802.11 MAC core */
295 #define SB_MIPS33 0x816 /* mips3302 core */
296 #define SB_USB11H 0x817 /* usb 1.1 host core */
297 #define SB_USB11D 0x818 /* usb 1.1 device core */
298 #define SB_USB20H 0x819 /* usb 2.0 host core */
299 #define SB_USB20D 0x81a /* usb 2.0 device core */
300 #define SB_SDIOH 0x81b /* sdio host core */
301 #define SB_ROBO 0x81c /* roboswitch core */
302 #define SB_ATA100 0x81d /* parallel ATA core */
303 #define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
304 #define SB_GIGETH 0x81f /* gigabit ethernet core */
305
306 /* Not really related to Silicon Backplane, but a couple of software
307 * conventions for the use the flash space:
308 */
309
310 /* Minumum amount of flash we support */
311 #define FLASH_MIN 0x00020000 /* Minimum flash size */
312
313 /* A boot/binary may have an embedded block that describes its size */
314 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
315 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
316 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */
317 #define BISZ_TXTST_IDX 1 /* 1: text start */
318 #define BISZ_TXTEND_IDX 2 /* 2: text start */
319 #define BISZ_DATAST_IDX 3 /* 3: text start */
320 #define BISZ_DATAEND_IDX 4 /* 4: text start */
321 #define BISZ_BSSST_IDX 5 /* 5: text start */
322 #define BISZ_BSSEND_IDX 6 /* 6: text start */
323 #define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
324
325 #endif /* _SBCONFIG_H */
Tomato firmware and modifications.