2 * x86-64 code generator for TCC
4 * Copyright (c) 2008 Shinichiro Hamaji
6 * Based on i386-gen.c by Fabrice Bellard
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifdef TARGET_DEFS_ONLY
25 /* number of available registers */
27 #define NB_ASM_REGS 16
28 #define CONFIG_TCC_ASM
30 /* a register can belong to several classes. The classes must be
31 sorted from more general to more precise (see gv2() code which does
32 assumptions on it). */
33 #define RC_INT 0x0001 /* generic integer register */
34 #define RC_FLOAT 0x0002 /* generic float register */
40 #define RC_ST0 0x0080 /* only for long double */
45 #define RC_XMM0 0x1000
46 #define RC_XMM1 0x2000
47 #define RC_XMM2 0x4000
48 #define RC_XMM3 0x8000
49 #define RC_XMM4 0x10000
50 #define RC_XMM5 0x20000
51 #define RC_XMM6 0x40000
52 #define RC_XMM7 0x80000
53 #define RC_IRET RC_RAX /* function return: integer register */
54 #define RC_IRE2 RC_RDX /* function return: second integer register */
55 #define RC_FRET RC_XMM0 /* function return: float register */
56 #define RC_FRE2 RC_XMM1 /* function return: second float register */
58 /* pretty names for the registers */
86 #define REX_BASE(reg) (((reg) >> 3) & 1)
87 #define REG_VALUE(reg) ((reg) & 7)
89 /* return registers for function */
90 #define REG_IRET TREG_RAX /* single word int return register */
91 #define REG_IRE2 TREG_RDX /* second word return register (for long long) */
92 #define REG_FRET TREG_XMM0 /* float return register */
93 #define REG_FRE2 TREG_XMM1 /* second float return register */
95 /* defined if function parameters must be evaluated in reverse order */
96 #define INVERT_FUNC_PARAMS
98 /* pointer size, in bytes */
101 /* long double size and alignment, in bytes */
102 #define LDOUBLE_SIZE 16
103 #define LDOUBLE_ALIGN 16
104 /* maximum alignment (for aligned attribute support) */
107 /* define if return values need to be extended explicitely
108 at caller side (for interfacing with non-TCC compilers) */
111 #define TCC_TARGET_NATIVE_STRUCT_COPY
112 ST_FUNC
void gen_struct_copy(int size
);
114 /******************************************************/
115 #else /* ! TARGET_DEFS_ONLY */
116 /******************************************************/
117 #define USING_GLOBALS
121 ST_DATA
const char * const target_machine_defs
=
126 ST_DATA
const int reg_classes
[NB_REGS
] = {
127 /* eax */ RC_INT
| RC_RAX
,
128 /* ecx */ RC_INT
| RC_RCX
,
129 /* edx */ RC_INT
| RC_RDX
,
143 /* xmm0 */ RC_FLOAT
| RC_XMM0
,
144 /* xmm1 */ RC_FLOAT
| RC_XMM1
,
145 /* xmm2 */ RC_FLOAT
| RC_XMM2
,
146 /* xmm3 */ RC_FLOAT
| RC_XMM3
,
147 /* xmm4 */ RC_FLOAT
| RC_XMM4
,
148 /* xmm5 */ RC_FLOAT
| RC_XMM5
,
149 /* xmm6 an xmm7 are included so gv() can be used on them,
150 but they are not tagged with RC_FLOAT because they are
151 callee saved on Windows */
157 static unsigned long func_sub_sp_offset
;
158 static int func_ret_sub
;
160 #if defined(CONFIG_TCC_BCHECK)
161 static addr_t func_bound_offset
;
162 static unsigned long func_bound_ind
;
163 ST_DATA
int func_bound_add_epilog
;
167 static int func_scratch
, func_alloca
;
170 /* XXX: make it faster ? */
171 ST_FUNC
void g(int c
)
177 if (ind1
> cur_text_section
->data_allocated
)
178 section_realloc(cur_text_section
, ind1
);
179 cur_text_section
->data
[ind
] = c
;
183 ST_FUNC
void o(unsigned int c
)
191 ST_FUNC
void gen_le16(int v
)
197 ST_FUNC
void gen_le32(int c
)
205 ST_FUNC
void gen_le64(int64_t c
)
217 static void orex(int ll
, int r
, int r2
, int b
)
219 if ((r
& VT_VALMASK
) >= VT_CONST
)
221 if ((r2
& VT_VALMASK
) >= VT_CONST
)
223 if (ll
|| REX_BASE(r
) || REX_BASE(r2
))
224 o(0x40 | REX_BASE(r
) | (REX_BASE(r2
) << 2) | (ll
<< 3));
228 /* output a symbol and patch all calls to it */
229 ST_FUNC
void gsym_addr(int t
, int a
)
232 unsigned char *ptr
= cur_text_section
->data
+ t
;
233 uint32_t n
= read32le(ptr
); /* next value */
234 write32le(ptr
, a
< 0 ? -a
: a
- t
- 4);
239 static int is64_type(int t
)
241 return ((t
& VT_BTYPE
) == VT_PTR
||
242 (t
& VT_BTYPE
) == VT_FUNC
||
243 (t
& VT_BTYPE
) == VT_LLONG
);
246 /* instruction + 4 bytes data. Return the address of the data */
247 static int oad(int c
, int s
)
258 /* generate jmp to a label */
259 #define gjmp2(instr,lbl) oad(instr,lbl)
261 ST_FUNC
void gen_addr32(int r
, Sym
*sym
, int c
)
264 greloca(cur_text_section
, sym
, ind
, R_X86_64_32S
, c
), c
=0;
268 /* output constant with relocation if 'r & VT_SYM' is true */
269 ST_FUNC
void gen_addr64(int r
, Sym
*sym
, int64_t c
)
272 greloca(cur_text_section
, sym
, ind
, R_X86_64_64
, c
), c
=0;
276 /* output constant with relocation if 'r & VT_SYM' is true */
277 ST_FUNC
void gen_addrpc32(int r
, Sym
*sym
, int c
)
280 greloca(cur_text_section
, sym
, ind
, R_X86_64_PC32
, c
-4), c
=4;
284 /* output got address with relocation */
285 static void gen_gotpcrel(int r
, Sym
*sym
, int c
)
288 tcc_error("internal error: no GOT on PE: %s %x %x | %02x %02x %02x\n",
289 get_tok_str(sym
->v
, NULL
), c
, r
,
290 cur_text_section
->data
[ind
-3],
291 cur_text_section
->data
[ind
-2],
292 cur_text_section
->data
[ind
-1]
295 greloca(cur_text_section
, sym
, ind
, R_X86_64_GOTPCREL
, -4);
298 /* we use add c, %xxx for displacement */
300 o(0xc0 + REG_VALUE(r
));
305 static void gen_modrm_impl(int op_reg
, int r
, Sym
*sym
, int c
, int is_got
)
307 op_reg
= REG_VALUE(op_reg
) << 3;
308 if ((r
& VT_VALMASK
) == VT_CONST
) {
309 /* constant memory reference */
311 /* Absolute memory reference */
312 o(0x04 | op_reg
); /* [sib] | destreg */
313 oad(0x25, c
); /* disp32 */
315 o(0x05 | op_reg
); /* (%rip)+disp32 | destreg */
317 gen_gotpcrel(r
, sym
, c
);
319 gen_addrpc32(r
, sym
, c
);
322 } else if ((r
& VT_VALMASK
) == VT_LOCAL
) {
323 /* currently, we use only ebp as base */
325 /* short reference */
329 oad(0x85 | op_reg
, c
);
331 } else if ((r
& VT_VALMASK
) >= TREG_MEM
) {
333 g(0x80 | op_reg
| REG_VALUE(r
));
336 g(0x00 | op_reg
| REG_VALUE(r
));
339 g(0x00 | op_reg
| REG_VALUE(r
));
343 /* generate a modrm reference. 'op_reg' contains the additional 3
345 static void gen_modrm(int op_reg
, int r
, Sym
*sym
, int c
)
347 gen_modrm_impl(op_reg
, r
, sym
, c
, 0);
350 /* generate a modrm reference. 'op_reg' contains the additional 3
352 static void gen_modrm64(int opcode
, int op_reg
, int r
, Sym
*sym
, int c
)
355 is_got
= (op_reg
& TREG_MEM
) && !(sym
->type
.t
& VT_STATIC
);
356 orex(1, r
, op_reg
, opcode
);
357 gen_modrm_impl(op_reg
, r
, sym
, c
, is_got
);
361 /* load 'r' from value 'sv' */
362 void load(int r
, SValue
*sv
)
364 int v
, t
, ft
, fc
, fr
;
369 sv
= pe_getimport(sv
, &v2
);
373 ft
= sv
->type
.t
& ~VT_DEFSIGN
;
375 if (fc
!= sv
->c
.i
&& (fr
& VT_SYM
))
376 tcc_error("64 bit addend in load");
378 ft
&= ~(VT_VOLATILE
| VT_CONSTANT
);
380 #ifndef TCC_TARGET_PE
381 /* we use indirect access via got */
382 if ((fr
& VT_VALMASK
) == VT_CONST
&& (fr
& VT_SYM
) &&
383 (fr
& VT_LVAL
) && !(sv
->sym
->type
.t
& VT_STATIC
)) {
384 /* use the result register as a temporal register */
385 int tr
= r
| TREG_MEM
;
387 /* we cannot use float registers as a temporal register */
388 tr
= get_reg(RC_INT
) | TREG_MEM
;
390 gen_modrm64(0x8b, tr
, fr
, sv
->sym
, 0);
392 /* load from the temporal register */
400 if (v
== VT_LLOCAL
) {
402 v1
.r
= VT_LOCAL
| VT_LVAL
;
405 if (!(reg_classes
[fr
] & (RC_INT
|RC_R11
)))
406 fr
= get_reg(RC_INT
);
410 /* If the addends doesn't fit into a 32bit signed
411 we must use a 64bit move. We've checked above
412 that this doesn't have a sym associated. */
413 v1
.type
.t
= VT_LLONG
;
417 if (!(reg_classes
[fr
] & (RC_INT
|RC_R11
)))
418 fr
= get_reg(RC_INT
);
423 /* Like GCC we can load from small enough properly sized
424 structs and unions as well.
425 XXX maybe move to generic operand handling, but should
426 occur only with asm, so tccasm.c might also be a better place */
427 if ((ft
& VT_BTYPE
) == VT_STRUCT
) {
429 switch (type_size(&sv
->type
, &align
)) {
430 case 1: ft
= VT_BYTE
; break;
431 case 2: ft
= VT_SHORT
; break;
432 case 4: ft
= VT_INT
; break;
433 case 8: ft
= VT_LLONG
; break;
435 tcc_error("invalid aggregate type for register load");
439 if ((ft
& VT_BTYPE
) == VT_FLOAT
) {
441 r
= REG_VALUE(r
); /* movd */
442 } else if ((ft
& VT_BTYPE
) == VT_DOUBLE
) {
443 b
= 0x7e0ff3; /* movq */
445 } else if ((ft
& VT_BTYPE
) == VT_LDOUBLE
) {
446 b
= 0xdb, r
= 5; /* fldt */
447 } else if ((ft
& VT_TYPE
) == VT_BYTE
|| (ft
& VT_TYPE
) == VT_BOOL
) {
448 b
= 0xbe0f; /* movsbl */
449 } else if ((ft
& VT_TYPE
) == (VT_BYTE
| VT_UNSIGNED
)) {
450 b
= 0xb60f; /* movzbl */
451 } else if ((ft
& VT_TYPE
) == VT_SHORT
) {
452 b
= 0xbf0f; /* movswl */
453 } else if ((ft
& VT_TYPE
) == (VT_SHORT
| VT_UNSIGNED
)) {
454 b
= 0xb70f; /* movzwl */
455 } else if ((ft
& VT_TYPE
) == (VT_VOID
)) {
456 /* Can happen with zero size structs */
459 assert(((ft
& VT_BTYPE
) == VT_INT
)
460 || ((ft
& VT_BTYPE
) == VT_LLONG
)
461 || ((ft
& VT_BTYPE
) == VT_PTR
)
462 || ((ft
& VT_BTYPE
) == VT_FUNC
)
468 gen_modrm64(b
, r
, fr
, sv
->sym
, fc
);
471 gen_modrm(r
, fr
, sv
->sym
, fc
);
478 o(0x05 + REG_VALUE(r
) * 8); /* lea xx(%rip), r */
479 gen_addrpc32(fr
, sv
->sym
, fc
);
481 if (sv
->sym
->type
.t
& VT_STATIC
) {
483 o(0x05 + REG_VALUE(r
) * 8); /* lea xx(%rip), r */
484 gen_addrpc32(fr
, sv
->sym
, fc
);
487 o(0x05 + REG_VALUE(r
) * 8); /* mov xx(%rip), r */
488 gen_gotpcrel(r
, sv
->sym
, fc
);
491 } else if (is64_type(ft
)) {
492 orex(1,r
,0, 0xb8 + REG_VALUE(r
)); /* mov $xx, r */
495 orex(0,r
,0, 0xb8 + REG_VALUE(r
)); /* mov $xx, r */
498 } else if (v
== VT_LOCAL
) {
499 orex(1,0,r
,0x8d); /* lea xxx(%ebp), r */
500 gen_modrm(r
, VT_LOCAL
, sv
->sym
, fc
);
501 } else if (v
== VT_CMP
) {
506 /* This was a float compare. If the parity bit is
507 set the result was unordered, meaning false for everything
508 except TOK_NE, and true for TOK_NE. */
509 orex(0, r
, 0, 0xb0 + REG_VALUE(r
)); /* mov $0/1,%al */
510 g(v
^ fc
^ (v
== TOK_NE
));
511 o(0x037a + (REX_BASE(r
) << 8));
513 orex(0,r
,0, 0x0f); /* setxx %br */
515 o(0xc0 + REG_VALUE(r
));
517 o(0xc0b6 + REG_VALUE(r
) * 0x900); /* movzbl %al, %eax */
518 } else if (v
== VT_JMP
|| v
== VT_JMPI
) {
521 oad(0xb8 + REG_VALUE(r
), t
); /* mov $1, r */
522 o(0x05eb + (REX_BASE(r
) << 8)); /* jmp after */
525 oad(0xb8 + REG_VALUE(r
), t
^ 1); /* mov $0, r */
527 if ((r
>= TREG_XMM0
) && (r
<= TREG_XMM7
)) {
529 /* gen_cvt_ftof(VT_DOUBLE); */
530 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
531 /* movsd -0x10(%rsp),%xmmN */
533 o(0x44 + REG_VALUE(r
)*8); /* %xmmN */
536 assert((v
>= TREG_XMM0
) && (v
<= TREG_XMM7
));
537 if ((ft
& VT_BTYPE
) == VT_FLOAT
) {
540 assert((ft
& VT_BTYPE
) == VT_DOUBLE
);
543 o(0xc0 + REG_VALUE(v
) + REG_VALUE(r
)*8);
545 } else if (r
== TREG_ST0
) {
546 assert((v
>= TREG_XMM0
) && (v
<= TREG_XMM7
));
547 /* gen_cvt_ftof(VT_LDOUBLE); */
548 /* movsd %xmmN,-0x10(%rsp) */
550 o(0x44 + REG_VALUE(r
)*8); /* %xmmN */
552 o(0xf02444dd); /* fldl -0x10(%rsp) */
554 orex(is64_type(ft
), r
, v
, 0x89);
555 o(0xc0 + REG_VALUE(r
) + REG_VALUE(v
) * 8); /* mov v, r */
561 /* store register 'r' in lvalue 'v' */
562 void store(int r
, SValue
*v
)
566 /* store the REX prefix in this variable when PIC is enabled */
571 v
= pe_getimport(v
, &v2
);
574 fr
= v
->r
& VT_VALMASK
;
577 if (fc
!= v
->c
.i
&& (fr
& VT_SYM
))
578 tcc_error("64 bit addend in store");
579 ft
&= ~(VT_VOLATILE
| VT_CONSTANT
);
582 #ifndef TCC_TARGET_PE
583 /* we need to access the variable via got */
586 && !(v
->sym
->type
.t
& VT_STATIC
)) {
587 /* mov xx(%rip), %r11 */
589 gen_gotpcrel(TREG_R11
, v
->sym
, v
->c
.i
);
590 pic
= is64_type(bt
) ? 0x49 : 0x41;
594 /* XXX: incorrect if float reg to reg */
595 if (bt
== VT_FLOAT
) {
598 o(0x7e0f); /* movd */
600 } else if (bt
== VT_DOUBLE
) {
603 o(0xd60f); /* movq */
605 } else if (bt
== VT_LDOUBLE
) {
606 o(0xc0d9); /* fld %st(0) */
614 if (bt
== VT_BYTE
|| bt
== VT_BOOL
)
616 else if (is64_type(bt
))
622 /* xxx r, (%r11) where xxx is mov, movq, fld, or etc */
627 if (fr
== VT_CONST
|| fr
== VT_LOCAL
|| (v
->r
& VT_LVAL
)) {
628 gen_modrm64(op64
, r
, v
->r
, v
->sym
, fc
);
629 } else if (fr
!= r
) {
630 orex(1, fr
, r
, op64
);
631 o(0xc0 + fr
+ r
* 8); /* mov r, fr */
634 if (fr
== VT_CONST
|| fr
== VT_LOCAL
|| (v
->r
& VT_LVAL
)) {
635 gen_modrm(r
, v
->r
, v
->sym
, fc
);
636 } else if (fr
!= r
) {
637 o(0xc0 + fr
+ r
* 8); /* mov r, fr */
642 /* 'is_jmp' is '1' if it is a jump */
643 static void gcall_or_jmp(int is_jmp
)
646 if ((vtop
->r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
&&
647 ((vtop
->r
& VT_SYM
) && (vtop
->c
.i
-4) == (int)(vtop
->c
.i
-4))) {
648 /* constant symbolic case -> simple relocation */
650 greloca(cur_text_section
, vtop
->sym
, ind
+ 1, R_X86_64_PC32
, (int)(vtop
->c
.i
-4));
652 greloca(cur_text_section
, vtop
->sym
, ind
+ 1, R_X86_64_PLT32
, (int)(vtop
->c
.i
-4));
654 oad(0xe8 + is_jmp
, 0); /* call/jmp im */
656 /* otherwise, indirect call */
660 o(0xff); /* call/jmp *r */
661 o(0xd0 + REG_VALUE(r
) + (is_jmp
<< 4));
665 #if defined(CONFIG_TCC_BCHECK)
667 static void gen_bounds_call(int v
)
669 Sym
*sym
= external_helper_sym(v
);
672 greloca(cur_text_section
, sym
, ind
-4, R_X86_64_PC32
, -4);
674 greloca(cur_text_section
, sym
, ind
-4, R_X86_64_PLT32
, -4);
679 # define TREG_FASTCALL_1 TREG_RCX
681 # define TREG_FASTCALL_1 TREG_RDI
684 static void gen_bounds_prolog(void)
686 /* leave some room for bound checking code */
687 func_bound_offset
= lbounds_section
->data_offset
;
688 func_bound_ind
= ind
;
689 func_bound_add_epilog
= 0;
690 o(0x0d8d48 + ((TREG_FASTCALL_1
== TREG_RDI
) * 0x300000)); /*lbound section pointer */
692 oad(0xb8, 0); /* call to function */
695 static void gen_bounds_epilog(void)
700 int offset_modified
= func_bound_offset
!= lbounds_section
->data_offset
;
702 if (!offset_modified
&& !func_bound_add_epilog
)
705 /* add end of table info */
706 bounds_ptr
= section_ptr_add(lbounds_section
, sizeof(addr_t
));
709 sym_data
= get_sym_ref(&char_pointer_type
, lbounds_section
,
710 func_bound_offset
, PTR_SIZE
);
712 /* generate bound local allocation */
713 if (offset_modified
) {
715 ind
= func_bound_ind
;
716 greloca(cur_text_section
, sym_data
, ind
+ 3, R_X86_64_PC32
, -4);
718 gen_bounds_call(TOK___bound_local_new
);
722 /* generate bound check local freeing */
723 o(0x5250); /* save returned value, if any */
724 o(0x20ec8348); /* sub $32,%rsp */
725 o(0x290f); /* movaps %xmm0,0x10(%rsp) */
727 o(0x240c290f); /* movaps %xmm1,(%rsp) */
728 greloca(cur_text_section
, sym_data
, ind
+ 3, R_X86_64_PC32
, -4);
729 o(0x0d8d48 + ((TREG_FASTCALL_1
== TREG_RDI
) * 0x300000)); /* lea xxx(%rip), %rcx/rdi */
731 gen_bounds_call(TOK___bound_local_delete
);
732 o(0x280f); /* movaps 0x10(%rsp),%xmm0 */
734 o(0x240c280f); /* movaps (%rsp),%xmm1 */
735 o(0x20c48348); /* add $32,%rsp */
736 o(0x585a); /* restore returned value, if any */
743 static const uint8_t arg_regs
[REGN
] = {
744 TREG_RCX
, TREG_RDX
, TREG_R8
, TREG_R9
747 /* Prepare arguments in R10 and R11 rather than RCX and RDX
748 because gv() will not ever use these */
749 static int arg_prepare_reg(int idx
) {
750 if (idx
== 0 || idx
== 1)
751 /* idx=0: r10, idx=1: r11 */
754 return idx
>= 0 && idx
< REGN
? arg_regs
[idx
] : 0;
757 /* Generate function call. The function address is pushed first, then
758 all the parameters in call order. This functions pops all the
759 parameters and the function address. */
761 static void gen_offs_sp(int b
, int r
, int d
)
763 orex(1,0,r
& 0x100 ? 0 : r
, b
);
765 o(0x2444 | (REG_VALUE(r
) << 3));
768 o(0x2484 | (REG_VALUE(r
) << 3));
773 static int using_regs(int size
)
775 return !(size
> 8 || (size
& (size
- 1)));
778 /* Return the number of registers needed to return the struct, or 0 if
779 returning via struct pointer. */
780 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
, int *ret_align
, int *regsize
)
783 *ret_align
= 1; // Never have to re-align return values for x86-64
785 size
= type_size(vt
, &align
);
786 if (!using_regs(size
))
800 static int is_sse_float(int t
) {
803 return bt
== VT_DOUBLE
|| bt
== VT_FLOAT
;
806 static int gfunc_arg_size(CType
*type
) {
808 if (type
->t
& (VT_ARRAY
|VT_BITFIELD
))
810 return type_size(type
, &align
);
813 void gfunc_call(int nb_args
)
815 int size
, r
, args_size
, i
, d
, bt
, struct_size
;
818 #ifdef CONFIG_TCC_BCHECK
819 if (tcc_state
->do_bounds_check
)
820 gbound_args(nb_args
);
823 args_size
= (nb_args
< REGN
? REGN
: nb_args
) * PTR_SIZE
;
826 /* for struct arguments, we need to call memcpy and the function
827 call breaks register passing arguments we are preparing.
828 So, we process arguments which will be passed by stack first. */
829 struct_size
= args_size
;
830 for(i
= 0; i
< nb_args
; i
++) {
835 bt
= (sv
->type
.t
& VT_BTYPE
);
836 size
= gfunc_arg_size(&sv
->type
);
838 if (using_regs(size
))
839 continue; /* arguments smaller than 8 bytes passed in registers or on stack */
841 if (bt
== VT_STRUCT
) {
842 /* align to stack align size */
843 size
= (size
+ 15) & ~15;
844 /* generate structure store */
846 gen_offs_sp(0x8d, r
, struct_size
);
849 /* generate memcpy call */
850 vset(&sv
->type
, r
| VT_LVAL
, 0);
854 } else if (bt
== VT_LDOUBLE
) {
856 gen_offs_sp(0xdb, 0x107, struct_size
);
861 if (func_scratch
< struct_size
)
862 func_scratch
= struct_size
;
865 struct_size
= args_size
;
867 for(i
= 0; i
< nb_args
; i
++) {
869 bt
= (vtop
->type
.t
& VT_BTYPE
);
871 size
= gfunc_arg_size(&vtop
->type
);
872 if (!using_regs(size
)) {
873 /* align to stack align size */
874 size
= (size
+ 15) & ~15;
877 gen_offs_sp(0x8d, d
, struct_size
);
878 gen_offs_sp(0x89, d
, arg
*8);
880 d
= arg_prepare_reg(arg
);
881 gen_offs_sp(0x8d, d
, struct_size
);
885 if (is_sse_float(vtop
->type
.t
)) {
886 if (tcc_state
->nosse
)
887 tcc_error("SSE disabled");
890 /* movq %xmm0, j*8(%rsp) */
891 gen_offs_sp(0xd60f66, 0x100, arg
*8);
893 /* Load directly to xmmN register */
895 d
= arg_prepare_reg(arg
);
896 /* mov %xmmN, %rxx */
899 o(0xc0 + arg
*8 + REG_VALUE(d
));
902 if (bt
== VT_STRUCT
) {
903 vtop
->type
.ref
= NULL
;
904 vtop
->type
.t
= size
> 4 ? VT_LLONG
: size
> 2 ? VT_INT
905 : size
> 1 ? VT_SHORT
: VT_BYTE
;
910 gen_offs_sp(0x89, r
, arg
*8);
912 d
= arg_prepare_reg(arg
);
913 orex(1,d
,r
,0x89); /* mov */
914 o(0xc0 + REG_VALUE(r
) * 8 + REG_VALUE(d
));
921 /* Copy R10 and R11 into RCX and RDX, respectively */
923 o(0xd1894c); /* mov %r10, %rcx */
925 o(0xda894c); /* mov %r11, %rdx */
931 if ((vtop
->r
& VT_SYM
) && vtop
->sym
->v
== TOK_alloca
) {
932 /* need to add the "func_scratch" area after alloca */
933 o(0x48); func_alloca
= oad(0x05, func_alloca
); /* add $NN, %rax */
934 #ifdef CONFIG_TCC_BCHECK
935 if (tcc_state
->do_bounds_check
)
936 gen_bounds_call(TOK___bound_alloca_nr
); /* new region */
943 #define FUNC_PROLOG_SIZE 11
945 /* generate function prolog of type 't' */
946 void gfunc_prolog(Sym
*func_sym
)
948 CType
*func_type
= &func_sym
->type
;
949 int addr
, reg_param_index
, bt
, size
;
959 ind
+= FUNC_PROLOG_SIZE
;
960 func_sub_sp_offset
= ind
;
963 sym
= func_type
->ref
;
965 /* if the function returns a structure, then add an
966 implicit pointer parameter */
967 size
= gfunc_arg_size(&func_vt
);
968 if (!using_regs(size
)) {
969 gen_modrm64(0x89, arg_regs
[reg_param_index
], VT_LOCAL
, NULL
, addr
);
975 /* define parameters */
976 while ((sym
= sym
->next
) != NULL
) {
978 bt
= type
->t
& VT_BTYPE
;
979 size
= gfunc_arg_size(type
);
980 if (!using_regs(size
)) {
981 if (reg_param_index
< REGN
) {
982 gen_modrm64(0x89, arg_regs
[reg_param_index
], VT_LOCAL
, NULL
, addr
);
984 sym_push(sym
->v
& ~SYM_FIELD
, type
,
985 VT_LLOCAL
| VT_LVAL
, addr
);
987 if (reg_param_index
< REGN
) {
988 /* save arguments passed by register */
989 if ((bt
== VT_FLOAT
) || (bt
== VT_DOUBLE
)) {
990 if (tcc_state
->nosse
)
991 tcc_error("SSE disabled");
992 o(0xd60f66); /* movq */
993 gen_modrm(reg_param_index
, VT_LOCAL
, NULL
, addr
);
995 gen_modrm64(0x89, arg_regs
[reg_param_index
], VT_LOCAL
, NULL
, addr
);
998 sym_push(sym
->v
& ~SYM_FIELD
, type
,
999 VT_LOCAL
| VT_LVAL
, addr
);
1005 while (reg_param_index
< REGN
) {
1007 gen_modrm64(0x89, arg_regs
[reg_param_index
], VT_LOCAL
, NULL
, addr
);
1012 #ifdef CONFIG_TCC_BCHECK
1013 if (tcc_state
->do_bounds_check
)
1014 gen_bounds_prolog();
1018 /* generate function epilog */
1019 void gfunc_epilog(void)
1023 /* align local size to word & save local variables */
1024 func_scratch
= (func_scratch
+ 15) & -16;
1025 loc
= (loc
& -16) - func_scratch
;
1027 #ifdef CONFIG_TCC_BCHECK
1028 if (tcc_state
->do_bounds_check
)
1029 gen_bounds_epilog();
1032 o(0xc9); /* leave */
1033 if (func_ret_sub
== 0) {
1036 o(0xc2); /* ret n */
1038 g(func_ret_sub
>> 8);
1042 ind
= func_sub_sp_offset
- FUNC_PROLOG_SIZE
;
1046 Sym
*sym
= external_helper_sym(TOK___chkstk
);
1047 oad(0xb8, v
); /* mov stacksize, %eax */
1048 oad(0xe8, 0); /* call __chkstk, (does the stackframe too) */
1049 greloca(cur_text_section
, sym
, ind
-4, R_X86_64_PC32
, -4);
1050 o(0x90); /* fill for FUNC_PROLOG_SIZE = 11 bytes */
1052 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1053 o(0xec8148); /* sub rsp, stacksize */
1057 /* add the "func_scratch" area after each alloca seen */
1058 gsym_addr(func_alloca
, -func_scratch
);
1060 cur_text_section
->data_offset
= saved_ind
;
1061 pe_add_unwind_data(ind
, saved_ind
, v
);
1062 ind
= cur_text_section
->data_offset
;
1067 static void gadd_sp(int val
)
1069 if (val
== (char)val
) {
1073 oad(0xc48148, val
); /* add $xxx, %rsp */
1077 typedef enum X86_64_Mode
{
1080 x86_64_mode_integer
,
1085 static X86_64_Mode
classify_x86_64_merge(X86_64_Mode a
, X86_64_Mode b
)
1089 else if (a
== x86_64_mode_none
)
1091 else if (b
== x86_64_mode_none
)
1093 else if ((a
== x86_64_mode_memory
) || (b
== x86_64_mode_memory
))
1094 return x86_64_mode_memory
;
1095 else if ((a
== x86_64_mode_integer
) || (b
== x86_64_mode_integer
))
1096 return x86_64_mode_integer
;
1097 else if ((a
== x86_64_mode_x87
) || (b
== x86_64_mode_x87
))
1098 return x86_64_mode_memory
;
1100 return x86_64_mode_sse
;
1103 static X86_64_Mode
classify_x86_64_inner(CType
*ty
)
1108 switch (ty
->t
& VT_BTYPE
) {
1109 case VT_VOID
: return x86_64_mode_none
;
1118 return x86_64_mode_integer
;
1121 case VT_DOUBLE
: return x86_64_mode_sse
;
1123 case VT_LDOUBLE
: return x86_64_mode_x87
;
1128 mode
= x86_64_mode_none
;
1129 for (f
= f
->next
; f
; f
= f
->next
)
1130 mode
= classify_x86_64_merge(mode
, classify_x86_64_inner(&f
->type
));
1138 static X86_64_Mode
classify_x86_64_arg(CType
*ty
, CType
*ret
, int *psize
, int *palign
, int *reg_count
)
1141 int size
, align
, ret_t
= 0;
1143 if (ty
->t
& (VT_BITFIELD
|VT_ARRAY
)) {
1148 mode
= x86_64_mode_integer
;
1150 size
= type_size(ty
, &align
);
1151 *psize
= (size
+ 7) & ~7;
1152 *palign
= (align
+ 7) & ~7;
1153 *reg_count
= 0; /* avoid compiler warning */
1156 mode
= x86_64_mode_memory
;
1158 mode
= classify_x86_64_inner(ty
);
1160 case x86_64_mode_integer
:
1174 if ((ty
->t
& VT_BTYPE
) == VT_STRUCT
|| (ty
->t
& VT_UNSIGNED
))
1175 ret_t
|= VT_UNSIGNED
;
1179 case x86_64_mode_x87
:
1184 case x86_64_mode_sse
:
1190 ret_t
= (size
> 4) ? VT_DOUBLE
: VT_FLOAT
;
1193 default: break; /* nothing to be done for x86_64_mode_memory and x86_64_mode_none*/
1206 ST_FUNC
int classify_x86_64_va_arg(CType
*ty
)
1208 /* This definition must be synced with stdarg.h */
1209 enum __va_arg_type
{
1210 __va_gen_reg
, __va_float_reg
, __va_stack
1212 int size
, align
, reg_count
;
1213 X86_64_Mode mode
= classify_x86_64_arg(ty
, NULL
, &size
, &align
, ®_count
);
1215 default: return __va_stack
;
1216 case x86_64_mode_integer
: return __va_gen_reg
;
1217 case x86_64_mode_sse
: return __va_float_reg
;
1221 /* Return the number of registers needed to return the struct, or 0 if
1222 returning via struct pointer. */
1223 ST_FUNC
int gfunc_sret(CType
*vt
, int variadic
, CType
*ret
, int *ret_align
, int *regsize
)
1225 int size
, align
, reg_count
;
1226 if (classify_x86_64_arg(vt
, ret
, &size
, &align
, ®_count
) == x86_64_mode_memory
)
1228 *ret_align
= 1; // Never have to re-align return values for x86-64
1229 *regsize
= 8 * reg_count
; /* the (virtual) regsize is 16 for VT_QLONG/QFLOAT */
1234 static const uint8_t arg_regs
[REGN
] = {
1235 TREG_RDI
, TREG_RSI
, TREG_RDX
, TREG_RCX
, TREG_R8
, TREG_R9
1238 static int arg_prepare_reg(int idx
) {
1239 if (idx
== 2 || idx
== 3)
1240 /* idx=2: r10, idx=3: r11 */
1243 return idx
>= 0 && idx
< REGN
? arg_regs
[idx
] : 0;
1246 /* Generate function call. The function address is pushed first, then
1247 all the parameters in call order. This functions pops all the
1248 parameters and the function address. */
1249 void gfunc_call(int nb_args
)
1253 int size
, align
, r
, args_size
, stack_adjust
, i
, reg_count
, k
;
1254 int nb_reg_args
= 0;
1255 int nb_sse_args
= 0;
1256 int sse_reg
, gen_reg
;
1257 char *onstack
= tcc_malloc((nb_args
+ 1) * sizeof (char));
1259 #ifdef CONFIG_TCC_BCHECK
1260 if (tcc_state
->do_bounds_check
)
1261 gbound_args(nb_args
);
1264 /* calculate the number of integer/float register arguments, remember
1265 arguments to be passed via stack (in onstack[]), and also remember
1266 if we have to align the stack pointer to 16 (onstack[i] == 2). Needs
1267 to be done in a left-to-right pass over arguments. */
1269 for(i
= nb_args
- 1; i
>= 0; i
--) {
1270 mode
= classify_x86_64_arg(&vtop
[-i
].type
, NULL
, &size
, &align
, ®_count
);
1271 if (size
== 0) continue;
1272 if (mode
== x86_64_mode_sse
&& nb_sse_args
+ reg_count
<= 8) {
1273 nb_sse_args
+= reg_count
;
1275 } else if (mode
== x86_64_mode_integer
&& nb_reg_args
+ reg_count
<= REGN
) {
1276 nb_reg_args
+= reg_count
;
1278 } else if (mode
== x86_64_mode_none
) {
1281 if (align
== 16 && (stack_adjust
&= 15)) {
1286 stack_adjust
+= size
;
1290 if (nb_sse_args
&& tcc_state
->nosse
)
1291 tcc_error("SSE disabled but floating point arguments passed");
1293 /* fetch cpu flag before generating any code */
1294 if ((vtop
->r
& VT_VALMASK
) == VT_CMP
)
1297 /* for struct arguments, we need to call memcpy and the function
1298 call breaks register passing arguments we are preparing.
1299 So, we process arguments which will be passed by stack first. */
1300 gen_reg
= nb_reg_args
;
1301 sse_reg
= nb_sse_args
;
1304 for (i
= k
= 0; i
< nb_args
;) {
1305 mode
= classify_x86_64_arg(&vtop
[-i
].type
, NULL
, &size
, &align
, ®_count
);
1307 if (!onstack
[i
+ k
]) {
1311 /* Possibly adjust stack to align SSE boundary. We're processing
1312 args from right to left while allocating happens left to right
1313 (stack grows down), so the adjustment needs to happen _after_
1314 an argument that requires it. */
1316 o(0x50); /* push %rax; aka sub $8,%rsp */
1320 if (onstack
[i
+ k
] == 2)
1326 switch (vtop
->type
.t
& VT_BTYPE
) {
1328 /* allocate the necessary size on stack */
1330 oad(0xec81, size
); /* sub $xxx, %rsp */
1331 /* generate structure store */
1332 r
= get_reg(RC_INT
);
1333 orex(1, r
, 0, 0x89); /* mov %rsp, r */
1334 o(0xe0 + REG_VALUE(r
));
1335 vset(&vtop
->type
, r
| VT_LVAL
, 0);
1337 /* keep stack aligned for (__bound_)memmove call */
1338 o(0x10ec8348); /* sub $16,%rsp */
1339 o(0xf0e48348); /* and $-16,%rsp */
1340 orex(0,r
,0,0x50 + REG_VALUE(r
)); /* push r (last %rsp) */
1341 o(0x08ec8348); /* sub $8,%rsp */
1343 o(0x08c48348); /* add $8,%rsp */
1344 o(0x5c); /* pop %rsp */
1349 oad(0xec8148, size
); /* sub $xxx, %rsp */
1350 o(0x7cdb); /* fstpt 0(%rsp) */
1357 assert(mode
== x86_64_mode_sse
);
1359 o(0x50); /* push $rax */
1360 /* movq %xmmN, (%rsp) */
1362 o(0x04 + REG_VALUE(r
)*8);
1367 assert(mode
== x86_64_mode_integer
);
1369 /* XXX: implicit cast ? */
1371 orex(0,r
,0,0x50 + REG_VALUE(r
)); /* push r */
1383 /* XXX This should be superfluous. */
1384 save_regs(0); /* save used temporary registers */
1386 /* then, we prepare register passing arguments.
1387 Note that we cannot set RDX and RCX in this loop because gv()
1388 may break these temporary registers. Let's use R10 and R11
1390 assert(gen_reg
<= REGN
);
1391 assert(sse_reg
<= 8);
1392 for(i
= 0; i
< nb_args
; i
++) {
1393 mode
= classify_x86_64_arg(&vtop
->type
, &type
, &size
, &align
, ®_count
);
1394 if (size
== 0) continue;
1395 /* Alter stack entry type so that gv() knows how to treat it */
1397 if (mode
== x86_64_mode_sse
) {
1398 if (reg_count
== 2) {
1400 gv(RC_FRET
); /* Use pair load into xmm0 & xmm1 */
1401 if (sse_reg
) { /* avoid redundant movaps %xmm0, %xmm0 */
1402 /* movaps %xmm1, %xmmN */
1404 o(0xc1 + ((sse_reg
+1) << 3));
1405 /* movaps %xmm0, %xmmN */
1407 o(0xc0 + (sse_reg
<< 3));
1410 assert(reg_count
== 1);
1412 /* Load directly to register */
1413 gv(RC_XMM0
<< sse_reg
);
1415 } else if (mode
== x86_64_mode_integer
) {
1417 /* XXX: implicit cast ? */
1419 gen_reg
-= reg_count
;
1421 d
= arg_prepare_reg(gen_reg
);
1422 orex(1,d
,r
,0x89); /* mov */
1423 o(0xc0 + REG_VALUE(r
) * 8 + REG_VALUE(d
));
1424 if (reg_count
== 2) {
1425 d
= arg_prepare_reg(gen_reg
+1);
1426 orex(1,d
,vtop
->r2
,0x89); /* mov */
1427 o(0xc0 + REG_VALUE(vtop
->r2
) * 8 + REG_VALUE(d
));
1432 assert(gen_reg
== 0);
1433 assert(sse_reg
== 0);
1435 /* We shouldn't have many operands on the stack anymore, but the
1436 call address itself is still there, and it might be in %eax
1437 (or edx/ecx) currently, which the below writes would clobber.
1438 So evict all remaining operands here. */
1441 /* Copy R10 and R11 into RDX and RCX, respectively */
1442 if (nb_reg_args
> 2) {
1443 o(0xd2894c); /* mov %r10, %rdx */
1444 if (nb_reg_args
> 3) {
1445 o(0xd9894c); /* mov %r11, %rcx */
1449 if (vtop
->type
.ref
->f
.func_type
!= FUNC_NEW
) /* implies FUNC_OLD or FUNC_ELLIPSIS */
1450 oad(0xb8, nb_sse_args
< 8 ? nb_sse_args
: 8); /* mov nb_sse_args, %eax */
1457 #define FUNC_PROLOG_SIZE 11
1459 static void push_arg_reg(int i
) {
1461 gen_modrm64(0x89, arg_regs
[i
], VT_LOCAL
, NULL
, loc
);
1464 /* generate function prolog of type 't' */
1465 void gfunc_prolog(Sym
*func_sym
)
1467 CType
*func_type
= &func_sym
->type
;
1468 X86_64_Mode mode
, ret_mode
;
1469 int i
, addr
, align
, size
, reg_count
;
1470 int param_addr
= 0, reg_param_index
, sse_param_index
;
1474 sym
= func_type
->ref
;
1475 addr
= PTR_SIZE
* 2;
1477 ind
+= FUNC_PROLOG_SIZE
;
1478 func_sub_sp_offset
= ind
;
1480 ret_mode
= classify_x86_64_arg(&func_vt
, NULL
, &size
, &align
, ®_count
);
1483 int seen_reg_num
, seen_sse_num
, seen_stack_size
;
1484 seen_reg_num
= ret_mode
== x86_64_mode_memory
;
1486 /* frame pointer and return address */
1487 seen_stack_size
= PTR_SIZE
* 2;
1488 /* count the number of seen parameters */
1489 sym
= func_type
->ref
;
1490 while ((sym
= sym
->next
) != NULL
) {
1492 mode
= classify_x86_64_arg(type
, NULL
, &size
, &align
, ®_count
);
1496 seen_stack_size
= ((seen_stack_size
+ align
- 1) & -align
) + size
;
1499 case x86_64_mode_integer
:
1500 if (seen_reg_num
+ reg_count
> REGN
)
1502 seen_reg_num
+= reg_count
;
1505 case x86_64_mode_sse
:
1506 if (seen_sse_num
+ reg_count
> 8)
1508 seen_sse_num
+= reg_count
;
1514 /* movl $0x????????, -0x18(%rbp) */
1516 gen_le32(seen_reg_num
* 8);
1517 /* movl $0x????????, -0x14(%rbp) */
1519 gen_le32(seen_sse_num
* 16 + 48);
1520 /* leaq $0x????????, %r11 */
1522 gen_le32(seen_stack_size
);
1523 /* movq %r11, -0x10(%rbp) */
1525 /* leaq $-192(%rbp), %r11 */
1527 gen_le32(-176 - 24);
1528 /* movq %r11, -0x8(%rbp) */
1531 /* save all register passing arguments */
1532 for (i
= 0; i
< 8; i
++) {
1534 if (!tcc_state
->nosse
) {
1535 o(0xd60f66); /* movq */
1536 gen_modrm(7 - i
, VT_LOCAL
, NULL
, loc
);
1538 /* movq $0, loc+8(%rbp) */
1543 for (i
= 0; i
< REGN
; i
++) {
1544 push_arg_reg(REGN
-1-i
);
1548 sym
= func_type
->ref
;
1549 reg_param_index
= 0;
1550 sse_param_index
= 0;
1552 /* if the function returns a structure, then add an
1553 implicit pointer parameter */
1554 if (ret_mode
== x86_64_mode_memory
) {
1555 push_arg_reg(reg_param_index
);
1559 /* define parameters */
1560 while ((sym
= sym
->next
) != NULL
) {
1562 mode
= classify_x86_64_arg(type
, NULL
, &size
, &align
, ®_count
);
1564 case x86_64_mode_sse
:
1565 if (tcc_state
->nosse
)
1566 tcc_error("SSE disabled but floating point arguments used");
1567 if (sse_param_index
+ reg_count
<= 8) {
1568 /* save arguments passed by register */
1569 loc
-= reg_count
* 8;
1571 for (i
= 0; i
< reg_count
; ++i
) {
1572 o(0xd60f66); /* movq */
1573 gen_modrm(sse_param_index
, VT_LOCAL
, NULL
, param_addr
+ i
*8);
1577 addr
= (addr
+ align
- 1) & -align
;
1583 case x86_64_mode_memory
:
1584 case x86_64_mode_x87
:
1585 addr
= (addr
+ align
- 1) & -align
;
1590 case x86_64_mode_integer
: {
1591 if (reg_param_index
+ reg_count
<= REGN
) {
1592 /* save arguments passed by register */
1593 loc
-= reg_count
* 8;
1595 for (i
= 0; i
< reg_count
; ++i
) {
1596 gen_modrm64(0x89, arg_regs
[reg_param_index
], VT_LOCAL
, NULL
, param_addr
+ i
*8);
1600 addr
= (addr
+ align
- 1) & -align
;
1606 default: break; /* nothing to be done for x86_64_mode_none */
1608 sym_push(sym
->v
& ~SYM_FIELD
, type
,
1609 VT_LOCAL
| VT_LVAL
, param_addr
);
1612 #ifdef CONFIG_TCC_BCHECK
1613 if (tcc_state
->do_bounds_check
)
1614 gen_bounds_prolog();
1618 /* generate function epilog */
1619 void gfunc_epilog(void)
1623 #ifdef CONFIG_TCC_BCHECK
1624 if (tcc_state
->do_bounds_check
)
1625 gen_bounds_epilog();
1627 o(0xc9); /* leave */
1628 if (func_ret_sub
== 0) {
1631 o(0xc2); /* ret n */
1633 g(func_ret_sub
>> 8);
1635 /* align local size to word & save local variables */
1636 v
= (-loc
+ 15) & -16;
1638 ind
= func_sub_sp_offset
- FUNC_PROLOG_SIZE
;
1639 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1640 o(0xec8148); /* sub rsp, stacksize */
1647 ST_FUNC
void gen_fill_nops(int bytes
)
1653 /* generate a jump to a label */
1656 return gjmp2(0xe9, t
);
1659 /* generate a jump to a fixed address */
1660 void gjmp_addr(int a
)
1668 oad(0xe9, a
- ind
- 5);
1672 ST_FUNC
int gjmp_append(int n
, int t
)
1675 /* insert vtop->c jump list in t */
1677 uint32_t n1
= n
, n2
;
1678 while ((n2
= read32le(p
= cur_text_section
->data
+ n1
)))
1686 ST_FUNC
int gjmp_cond(int op
, int t
)
1690 /* This was a float compare. If the parity flag is set
1691 the result was unordered. For anything except != this
1692 means false and we don't jump (anding both conditions).
1693 For != this means true (oring both).
1694 Take care about inverting the test. We need to jump
1695 to our target if the result was unordered and test wasn't NE,
1696 otherwise if unordered we don't want to jump. */
1697 int v
= vtop
->cmp_r
;
1699 if (op
^ v
^ (v
!= TOK_NE
))
1700 o(0x067a); /* jp +6 */
1704 t
= gjmp2(0x8a, t
); /* jp t */
1708 t
= gjmp2(op
- 16, t
);
1712 /* generate an integer binary operation */
1713 void gen_opi(int op
)
1718 ll
= is64_type(vtop
[-1].type
.t
);
1719 uu
= (vtop
[-1].type
.t
& VT_UNSIGNED
) != 0;
1720 cc
= (vtop
->r
& (VT_VALMASK
| VT_LVAL
| VT_SYM
)) == VT_CONST
;
1724 case TOK_ADDC1
: /* add with carry generation */
1727 if (cc
&& (!ll
|| (int)vtop
->c
.i
== vtop
->c
.i
)) {
1734 /* XXX: generate inc and dec for smaller code ? */
1735 orex(ll
, r
, 0, 0x83);
1736 o(0xc0 | (opc
<< 3) | REG_VALUE(r
));
1739 orex(ll
, r
, 0, 0x81);
1740 oad(0xc0 | (opc
<< 3) | REG_VALUE(r
), c
);
1743 gv2(RC_INT
, RC_INT
);
1746 orex(ll
, r
, fr
, (opc
<< 3) | 0x01);
1747 o(0xc0 + REG_VALUE(r
) + REG_VALUE(fr
) * 8);
1750 if (op
>= TOK_ULT
&& op
<= TOK_GT
)
1754 case TOK_SUBC1
: /* sub with carry generation */
1757 case TOK_ADDC2
: /* add with carry use */
1760 case TOK_SUBC2
: /* sub with carry use */
1773 gv2(RC_INT
, RC_INT
);
1776 orex(ll
, fr
, r
, 0xaf0f); /* imul fr, r */
1777 o(0xc0 + REG_VALUE(fr
) + REG_VALUE(r
) * 8);
1789 opc
= 0xc0 | (opc
<< 3);
1795 orex(ll
, r
, 0, 0xc1); /* shl/shr/sar $xxx, r */
1796 o(opc
| REG_VALUE(r
));
1797 g(vtop
->c
.i
& (ll
? 63 : 31));
1799 /* we generate the shift in ecx */
1800 gv2(RC_INT
, RC_RCX
);
1802 orex(ll
, r
, 0, 0xd3); /* shl/shr/sar %cl, r */
1803 o(opc
| REG_VALUE(r
));
1816 /* first operand must be in eax */
1817 /* XXX: need better constraint for second operand */
1818 gv2(RC_RAX
, RC_RCX
);
1823 orex(ll
, 0, 0, uu
? 0xd231 : 0x99); /* xor %edx,%edx : cqto */
1824 orex(ll
, fr
, 0, 0xf7); /* div fr, %eax */
1825 o((uu
? 0xf0 : 0xf8) + REG_VALUE(fr
));
1826 if (op
== '%' || op
== TOK_UMOD
)
1838 void gen_opl(int op
)
1843 void vpush_const(int t
, int v
)
1845 CType ctype
= { t
| VT_CONSTANT
, 0 };
1846 vpushsym(&ctype
, external_global_sym(v
, &ctype
));
1850 /* generate a floating point operation 'v = t1 op t2' instruction. The
1851 two operands are guaranteed to have the same floating point type */
1852 /* XXX: need to use ST1 too */
1853 void gen_opf(int op
)
1855 int a
, ft
, fc
, swapped
, r
;
1856 int bt
= vtop
->type
.t
& VT_BTYPE
;
1857 int float_type
= bt
== VT_LDOUBLE
? RC_ST0
: RC_FLOAT
;
1859 if (op
== TOK_NEG
) { /* unary minus */
1861 if (float_type
== RC_ST0
) {
1862 o(0xe0d9); /* fchs */
1864 /* -0.0, in libtcc1.c */
1865 vpush_const(bt
, bt
== VT_FLOAT
? TOK___mzerosf
: TOK___mzerodf
);
1867 if (bt
== VT_DOUBLE
)
1869 /* xorp[sd] %xmm1, %xmm0 */
1870 o(0xc0570f | (REG_VALUE(vtop
[0].r
) + REG_VALUE(vtop
[-1].r
)*8) << 16);
1876 /* convert constants to memory references */
1877 if ((vtop
[-1].r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
) {
1882 if ((vtop
[0].r
& (VT_VALMASK
| VT_LVAL
)) == VT_CONST
)
1885 /* must put at least one value in the floating point register */
1886 if ((vtop
[-1].r
& VT_LVAL
) &&
1887 (vtop
[0].r
& VT_LVAL
)) {
1893 /* swap the stack if needed so that t1 is the register and t2 is
1894 the memory reference */
1895 if (vtop
[-1].r
& VT_LVAL
) {
1899 if ((vtop
->type
.t
& VT_BTYPE
) == VT_LDOUBLE
) {
1900 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
1901 /* load on stack second operand */
1902 load(TREG_ST0
, vtop
);
1903 save_reg(TREG_RAX
); /* eax is used by FP comparison code */
1904 if (op
== TOK_GE
|| op
== TOK_GT
)
1906 else if (op
== TOK_EQ
|| op
== TOK_NE
)
1909 o(0xc9d9); /* fxch %st(1) */
1910 if (op
== TOK_EQ
|| op
== TOK_NE
)
1911 o(0xe9da); /* fucompp */
1913 o(0xd9de); /* fcompp */
1914 o(0xe0df); /* fnstsw %ax */
1916 o(0x45e480); /* and $0x45, %ah */
1917 o(0x40fC80); /* cmp $0x40, %ah */
1918 } else if (op
== TOK_NE
) {
1919 o(0x45e480); /* and $0x45, %ah */
1920 o(0x40f480); /* xor $0x40, %ah */
1922 } else if (op
== TOK_GE
|| op
== TOK_LE
) {
1923 o(0x05c4f6); /* test $0x05, %ah */
1926 o(0x45c4f6); /* test $0x45, %ah */
1932 /* no memory reference possible for long double operations */
1933 load(TREG_ST0
, vtop
);
1957 o(0xde); /* fxxxp %st, %st(1) */
1962 if (op
>= TOK_ULT
&& op
<= TOK_GT
) {
1963 /* if saved lvalue, then we must reload it */
1966 if ((r
& VT_VALMASK
) == VT_LLOCAL
) {
1968 r
= get_reg(RC_INT
);
1970 v1
.r
= VT_LOCAL
| VT_LVAL
;
1974 vtop
->r
= r
= r
| VT_LVAL
;
1977 if (op
== TOK_EQ
|| op
== TOK_NE
) {
1980 if (op
== TOK_LE
|| op
== TOK_LT
)
1982 if (op
== TOK_LE
|| op
== TOK_GE
) {
1983 op
= 0x93; /* setae */
1985 op
= 0x97; /* seta */
1993 assert(!(vtop
[-1].r
& VT_LVAL
));
1995 if ((vtop
->type
.t
& VT_BTYPE
) == VT_DOUBLE
)
1997 if (op
== TOK_EQ
|| op
== TOK_NE
)
1998 o(0x2e0f); /* ucomisd */
2000 o(0x2f0f); /* comisd */
2002 if (vtop
->r
& VT_LVAL
) {
2003 gen_modrm(vtop
[-1].r
, r
, vtop
->sym
, fc
);
2005 o(0xc0 + REG_VALUE(vtop
[0].r
) + REG_VALUE(vtop
[-1].r
)*8);
2009 vset_VT_CMP(op
| 0x100);
2012 assert((vtop
->type
.t
& VT_BTYPE
) != VT_LDOUBLE
);
2030 assert((ft
& VT_BTYPE
) != VT_LDOUBLE
);
2033 /* if saved lvalue, then we must reload it */
2034 if ((vtop
->r
& VT_VALMASK
) == VT_LLOCAL
) {
2036 r
= get_reg(RC_INT
);
2038 v1
.r
= VT_LOCAL
| VT_LVAL
;
2042 vtop
->r
= r
= r
| VT_LVAL
;
2045 assert(!(vtop
[-1].r
& VT_LVAL
));
2047 assert(vtop
->r
& VT_LVAL
);
2052 if ((ft
& VT_BTYPE
) == VT_DOUBLE
) {
2060 if (vtop
->r
& VT_LVAL
) {
2061 gen_modrm(vtop
[-1].r
, r
, vtop
->sym
, fc
);
2063 o(0xc0 + REG_VALUE(vtop
[0].r
) + REG_VALUE(vtop
[-1].r
)*8);
2071 /* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
2072 and 'long long' cases. */
2073 void gen_cvt_itof(int t
)
2075 if ((t
& VT_BTYPE
) == VT_LDOUBLE
) {
2078 if ((vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
) {
2079 /* signed long long to float/double/long double (unsigned case
2080 is handled generically) */
2081 o(0x50 + (vtop
->r
& VT_VALMASK
)); /* push r */
2082 o(0x242cdf); /* fildll (%rsp) */
2083 o(0x08c48348); /* add $8, %rsp */
2084 } else if ((vtop
->type
.t
& (VT_BTYPE
| VT_UNSIGNED
)) ==
2085 (VT_INT
| VT_UNSIGNED
)) {
2086 /* unsigned int to float/double/long double */
2087 o(0x6a); /* push $0 */
2089 o(0x50 + (vtop
->r
& VT_VALMASK
)); /* push r */
2090 o(0x242cdf); /* fildll (%rsp) */
2091 o(0x10c48348); /* add $16, %rsp */
2093 /* int to float/double/long double */
2094 o(0x50 + (vtop
->r
& VT_VALMASK
)); /* push r */
2095 o(0x2404db); /* fildl (%rsp) */
2096 o(0x08c48348); /* add $8, %rsp */
2100 int r
= get_reg(RC_FLOAT
);
2102 o(0xf2 + ((t
& VT_BTYPE
) == VT_FLOAT
?1:0));
2103 if ((vtop
->type
.t
& (VT_BTYPE
| VT_UNSIGNED
)) ==
2104 (VT_INT
| VT_UNSIGNED
) ||
2105 (vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
) {
2109 o(0xc0 + (vtop
->r
& VT_VALMASK
) + REG_VALUE(r
)*8); /* cvtsi2sd */
2114 /* convert from one floating point type to another */
2115 void gen_cvt_ftof(int t
)
2123 if (bt
== VT_FLOAT
) {
2125 if (tbt
== VT_DOUBLE
) {
2126 o(0x140f); /* unpcklps */
2127 o(0xc0 + REG_VALUE(vtop
->r
)*9);
2128 o(0x5a0f); /* cvtps2pd */
2129 o(0xc0 + REG_VALUE(vtop
->r
)*9);
2130 } else if (tbt
== VT_LDOUBLE
) {
2132 /* movss %xmm0,-0x10(%rsp) */
2134 o(0x44 + REG_VALUE(vtop
->r
)*8);
2136 o(0xf02444d9); /* flds -0x10(%rsp) */
2139 } else if (bt
== VT_DOUBLE
) {
2141 if (tbt
== VT_FLOAT
) {
2142 o(0x140f66); /* unpcklpd */
2143 o(0xc0 + REG_VALUE(vtop
->r
)*9);
2144 o(0x5a0f66); /* cvtpd2ps */
2145 o(0xc0 + REG_VALUE(vtop
->r
)*9);
2146 } else if (tbt
== VT_LDOUBLE
) {
2148 /* movsd %xmm0,-0x10(%rsp) */
2150 o(0x44 + REG_VALUE(vtop
->r
)*8);
2152 o(0xf02444dd); /* fldl -0x10(%rsp) */
2158 r
= get_reg(RC_FLOAT
);
2159 if (tbt
== VT_DOUBLE
) {
2160 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
2161 /* movsd -0x10(%rsp),%xmm0 */
2163 o(0x44 + REG_VALUE(r
)*8);
2166 } else if (tbt
== VT_FLOAT
) {
2167 o(0xf0245cd9); /* fstps -0x10(%rsp) */
2168 /* movss -0x10(%rsp),%xmm0 */
2170 o(0x44 + REG_VALUE(r
)*8);
2177 /* convert fp to int 't' type */
2178 void gen_cvt_ftoi(int t
)
2180 int ft
, bt
, size
, r
;
2183 if (bt
== VT_LDOUBLE
) {
2184 gen_cvt_ftof(VT_DOUBLE
);
2194 r
= get_reg(RC_INT
);
2195 if (bt
== VT_FLOAT
) {
2197 } else if (bt
== VT_DOUBLE
) {
2202 orex(size
== 8, r
, 0, 0x2c0f); /* cvttss2si or cvttsd2si */
2203 o(0xc0 + REG_VALUE(vtop
->r
) + REG_VALUE(r
)*8);
2207 // Generate sign extension from 32 to 64 bits:
2208 ST_FUNC
void gen_cvt_sxtw(void)
2211 /* x86_64 specific: movslq */
2213 o(0xc0 + (REG_VALUE(r
) << 3) + REG_VALUE(r
));
2216 /* char/short to int conversion */
2217 ST_FUNC
void gen_cvt_csti(int t
)
2221 sz
= !(t
& VT_UNSIGNED
);
2222 xl
= (t
& VT_BTYPE
) == VT_SHORT
;
2223 ll
= (vtop
->type
.t
& VT_BTYPE
) == VT_LLONG
;
2224 orex(ll
, r
, 0, 0xc0b60f /* mov[sz] %a[xl], %eax */
2225 | (sz
<< 3 | xl
) << 8
2226 | (REG_VALUE(r
) << 3 | REG_VALUE(r
)) << 16
2230 /* increment tcov counter */
2231 ST_FUNC
void gen_increment_tcov (SValue
*sv
)
2233 o(0x058348); /* addq $1, xxx(%rip) */
2234 greloca(cur_text_section
, sv
->sym
, ind
, R_X86_64_PC32
, -5);
2239 /* computed goto support */
2240 ST_FUNC
void ggoto(void)
2246 /* Save the stack pointer onto the stack and return the location of its address */
2247 ST_FUNC
void gen_vla_sp_save(int addr
) {
2248 /* mov %rsp,addr(%rbp)*/
2249 gen_modrm64(0x89, TREG_RSP
, VT_LOCAL
, NULL
, addr
);
2252 /* Restore the SP from a location on the stack */
2253 ST_FUNC
void gen_vla_sp_restore(int addr
) {
2254 gen_modrm64(0x8b, TREG_RSP
, VT_LOCAL
, NULL
, addr
);
2257 #ifdef TCC_TARGET_PE
2258 /* Save result of gen_vla_alloc onto the stack */
2259 ST_FUNC
void gen_vla_result(int addr
) {
2260 /* mov %rax,addr(%rbp)*/
2261 gen_modrm64(0x89, TREG_RAX
, VT_LOCAL
, NULL
, addr
);
2265 /* Subtract from the stack pointer, and push the resulting value onto the stack */
2266 ST_FUNC
void gen_vla_alloc(CType
*type
, int align
) {
2269 #if defined(CONFIG_TCC_BCHECK)
2270 use_call
= tcc_state
->do_bounds_check
;
2272 #ifdef TCC_TARGET_PE /* alloca does more than just adjust %rsp on Windows */
2277 vpush_helper_func(TOK_alloca
);
2278 vswap(); /* Move alloca ref past allocation size */
2283 r
= gv(RC_INT
); /* allocation size */
2286 o(0xe0 | REG_VALUE(r
));
2287 /* We align to 16 bytes rather than align */
2295 * Assmuing the top part of the stack looks like below,
2298 ST_FUNC
void gen_struct_copy(int size
)
2300 int n
= size
/ PTR_SIZE
;
2301 #ifdef TCC_TARGET_PE
2302 o(0x5756); /* push rsi, rdi */
2304 gv2(RC_RDI
, RC_RSI
);
2320 #ifdef TCC_TARGET_PE
2321 o(0x5e5f); /* pop rdi, rsi */
2327 /* end of x86-64 code generator */
2328 /*************************************************************/
2329 #endif /* ! TARGET_DEFS_ONLY */
2330 /******************************************************/