riscv64-tok.h: update with more instructions from the spec
commite70fec871b9eae3295620d8e32ac6d4d93f1a954
authornoneofyourbusiness <noneofyourbusiness@danwin1210.de>
Thu, 10 Aug 2023 11:27:11 +0000 (10 13:27 +0200)
committernoneofyourbusiness <noneofyourbusiness@danwin1210.de>
Thu, 10 Aug 2023 12:25:03 +0000 (10 14:25 +0200)
tree84edc284c56b61c43ad77656f0dcdf0c6404ce9e
parentc29420ab0de92cefc95388e23506cf8dd8c5348d
riscv64-tok.h: update with more instructions from the spec

defined tokens for C, M, Ziscr extensions.

separate the base RV32 instructions from the RV64, for potential future
re-use in a RV32-only assembler, from which the RV64-tok can #include

scall, sbreak have been renamed (page 7 of spec),
necessitating some renaming in riscv64-asm.c

riscv-spec-20191213.pdf was used,
in which the "V" extension is not yet ratified.
available under https://riscv.org/technical/specifications/

Tables 16.5–16.7 do not list any "scall"
neither does the privileged spec

3 additional tokens not present in the tables were removed

note that this riscv64-asm.c still contains defects, which will
be addressed in another commit
riscv64-asm.c
riscv64-tok.h