com32/gpllib/cpuid.c

   1 /*
   2  * Portions of this file taken from the Linux kernel,
   3  * Copyright 1991-2009 Linus Torvalds and contributors
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
  17 */
  18
  19 #include <stdio.h>
  20 #include <string.h>
  21 #include "cpuid.h"
  22
  23 const char *cpu_flags_names[] = {
  24     CPU_FLAGS(STRUCT_MEMBER_NAMES)
  25 };
  26
  27 size_t cpu_flags_offset[] = {
  28     CPU_FLAGS(STRUCTURE_MEMBER_OFFSETS)
  29 };
  30
  31 size_t cpu_flags_count = sizeof cpu_flags_names / sizeof *cpu_flags_names;
  32
  33 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = { };
  34
  35 bool get_cpu_flag_value_from_name(s_cpu *cpu, const char * flag_name) {
  36     size_t i;
  37     bool cpu_flag_present=false, *flag_value = &cpu_flag_present;
  38
  39     for (i = 0; i < cpu_flags_count; i++) {
  40         if (strcmp(cpu_flags_names[i],flag_name) == 0) {
  41                 flag_value = (bool *)((char *)&cpu->flags + cpu_flags_offset[i]);
  42         }
  43     }
  44     return *flag_value;
  45 }
  46
  47
  48 /*
  49 * CPUID functions returning a single datum
  50 */
  51
  52 /* Probe for the CPUID instruction */
  53 static int have_cpuid_p(void)
  54 {
  55     return cpu_has_eflag(X86_EFLAGS_ID);
  56 }
  57
  58 static struct cpu_dev amd_cpu_dev = {
  59     .c_vendor = "AMD",
  60     .c_ident = {"AuthenticAMD"}
  61 };
  62
  63 static struct cpu_dev intel_cpu_dev = {
  64     .c_vendor = "Intel",
  65     .c_ident = {"GenuineIntel"}
  66 };
  67
  68 static struct cpu_dev cyrix_cpu_dev = {
  69     .c_vendor = "Cyrix",
  70     .c_ident = {"CyrixInstead"}
  71 };
  72
  73 static struct cpu_dev umc_cpu_dev = {
  74     .c_vendor = "UMC",
  75     .c_ident = {"UMC UMC UMC"}
  76
  77 };
  78
  79 static struct cpu_dev nexgen_cpu_dev = {
  80     .c_vendor = "Nexgen",
  81     .c_ident = {"NexGenDriven"}
  82 };
  83
  84 static struct cpu_dev centaur_cpu_dev = {
  85     .c_vendor = "Centaur",
  86     .c_ident = {"CentaurHauls"}
  87 };
  88
  89 static struct cpu_dev rise_cpu_dev = {
  90     .c_vendor = "Rise",
  91     .c_ident = {"RiseRiseRise"}
  92 };
  93
  94 static struct cpu_dev transmeta_cpu_dev = {
  95     .c_vendor = "Transmeta",
  96     .c_ident = {"GenuineTMx86", "TransmetaCPU"}
  97 };
  98
  99 static struct cpu_dev nsc_cpu_dev = {
 100     .c_vendor = "National Semiconductor",
 101     .c_ident = {"Geode by NSC"}
 102 };
 103
 104 static struct cpu_dev unknown_cpu_dev = {
 105     .c_vendor = "Unknown Vendor",
 106     .c_ident = {"Unknown CPU"}
 107 };
 108
 109 void init_cpu_devs(void)
 110 {
 111     cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
 112     cpu_devs[X86_VENDOR_CYRIX] = &cyrix_cpu_dev;
 113     cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
 114     cpu_devs[X86_VENDOR_UMC] = &umc_cpu_dev;
 115     cpu_devs[X86_VENDOR_NEXGEN] = &nexgen_cpu_dev;
 116     cpu_devs[X86_VENDOR_CENTAUR] = &centaur_cpu_dev;
 117     cpu_devs[X86_VENDOR_RISE] = &rise_cpu_dev;
 118     cpu_devs[X86_VENDOR_TRANSMETA] = &transmeta_cpu_dev;
 119     cpu_devs[X86_VENDOR_NSC] = &nsc_cpu_dev;
 120     cpu_devs[X86_VENDOR_UNKNOWN] = &unknown_cpu_dev;
 121 }
 122
 123 void get_cpu_vendor(struct cpuinfo_x86 *c)
 124 {
 125     char *v = c->x86_vendor_id;
 126     int i;
 127     init_cpu_devs();
 128     for (i = 0; i < X86_VENDOR_NUM-1; i++) {
 129         if (cpu_devs[i]) {
 130             if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 131                 (cpu_devs[i]->c_ident[1] &&
 132                  !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 133                 c->x86_vendor = i;
 134                 return;
 135             }
 136         }
 137     }
 138
 139     c->x86_vendor = X86_VENDOR_UNKNOWN;
 140 }
 141
 142 int get_model_name(struct cpuinfo_x86 *c)
 143 {
 144     unsigned int *v;
 145     char *p, *q;
 146
 147     if (cpuid_eax(0x80000000) < 0x80000004)
 148         return 0;
 149
 150     v = (unsigned int *)c->x86_model_id;
 151     cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 152     cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 153     cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 154     c->x86_model_id[48] = 0;
 155
 156     /* Intel chips right-justify this string for some dumb reason;
 157        undo that brain damage */
 158     p = q = &c->x86_model_id[0];
 159     while (*p == ' ')
 160         p++;
 161     if (p != q) {
 162         while (*p)
 163             *q++ = *p++;
 164         while (q <= &c->x86_model_id[48])
 165             *q++ = '\0';        /* Zero-pad the rest */
 166     }
 167
 168     return 1;
 169 }
 170
 171 void detect_cache(uint32_t xlvl, struct cpuinfo_x86 *c)
 172 {
 173     uint32_t eax, ebx, ecx, edx, l2size;
 174     /* Detecting L1 cache */
 175     if (xlvl >= 0x80000005) {
 176         cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
 177         c->x86_l1_data_cache_size = ecx >> 24;
 178         c->x86_l1_instruction_cache_size = edx >> 24;
 179     }
 180
 181     /* Detecting L2 cache */
 182     c->x86_l2_cache_size = 0;
 183
 184     if (xlvl < 0x80000006)      /* Some chips just has a large L1. */
 185         return;
 186
 187     cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
 188     l2size = ecx >> 16;
 189
 190     /* Vendor based fixes */
 191     switch (c->x86_vendor) {
 192     case X86_VENDOR_INTEL:
 193         /*
 194          * Intel PIII Tualatin. This comes in two flavours.
 195          * One has 256kb of cache, the other 512. We have no way
 196          * to determine which, so we use a boottime override
 197          * for the 512kb model, and assume 256 otherwise.
 198          */
 199         if ((c->x86 == 6) && (c->x86_model == 11) && (l2size == 0))
 200             l2size = 256;
 201         break;
 202     case X86_VENDOR_AMD:
 203         /* AMD errata T13 (order #21922) */
 204         if ((c->x86 == 6)) {
 205             if (c->x86_model == 3 && c->x86_mask == 0)  /* Duron Rev A0 */
 206                 l2size = 64;
 207             if (c->x86_model == 4 && (c->x86_mask == 0 || c->x86_mask == 1))    /* Tbird rev A1/A2 */
 208                 l2size = 256;
 209         }
 210         break;
 211     }
 212     c->x86_l2_cache_size = l2size;
 213 }
 214
 215 void generic_identify(struct cpuinfo_x86 *c)
 216 {
 217     uint32_t tfms, xlvl;
 218     uint32_t eax, ebx, ecx, edx;
 219
 220     /* Get vendor name */
 221     cpuid(0x00000000,
 222           (uint32_t *) & c->cpuid_level,
 223           (uint32_t *) & c->x86_vendor_id[0],
 224           (uint32_t *) & c->x86_vendor_id[8],
 225           (uint32_t *) & c->x86_vendor_id[4]);
 226
 227     get_cpu_vendor(c);
 228
 229     /* Intel-defined flags: level 0x00000001 */
 230     if (c->cpuid_level >= 0x00000001) {
 231         uint32_t capability, excap;
 232         cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
 233         c->x86_capability[0] = capability;
 234         c->x86_capability[4] = excap;
 235         c->x86 = (tfms >> 8) & 15;
 236         c->x86_model = (tfms >> 4) & 15;
 237         if (c->x86 == 0xf)
 238             c->x86 += (tfms >> 20) & 0xff;
 239         if (c->x86 >= 0x6)
 240             c->x86_model += ((tfms >> 16) & 0xF) << 4;
 241         c->x86_mask = tfms & 15;
 242         if (cpu_has(c, X86_FEATURE_CLFLSH))
 243             c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
 244     } else {
 245         /* Have CPUID level 0 only - unheard of */
 246         c->x86 = 4;
 247     }
 248
 249     /* AMD-defined flags: level 0x80000001 */
 250     xlvl = cpuid_eax(0x80000000);
 251     if ((xlvl & 0xffff0000) == 0x80000000) {
 252         if (xlvl >= 0x80000001) {
 253             c->x86_capability[1] = cpuid_edx(0x80000001);
 254             c->x86_capability[6] = cpuid_ecx(0x80000001);
 255         }
 256         if (xlvl >= 0x80000004)
 257             get_model_name(c);  /* Default name */
 258     }
 259
 260     /* Detecting the number of cores */
 261     switch (c->x86_vendor) {
 262     case X86_VENDOR_AMD:
 263         if (xlvl >= 0x80000008) {
 264             c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 265             if (c->x86_num_cores & (c->x86_num_cores - 1))
 266                 c->x86_num_cores = 1;
 267         }
 268         break;
 269     case X86_VENDOR_INTEL:
 270         if (c->cpuid_level >= 0x00000004) {
 271             cpuid(0x4, &eax, &ebx, &ecx, &edx);
 272             c->x86_num_cores = ((eax & 0xfc000000) >> 26) + 1;
 273         }
 274         break;
 275     default:
 276         c->x86_num_cores = 1;
 277         break;
 278     }
 279
 280     detect_cache(xlvl, c);
 281 }
 282
 283 /*
 284  * Checksum an MP configuration block.
 285  */
 286
 287 static int mpf_checksum(unsigned char *mp, int len)
 288 {
 289     int sum = 0;
 290
 291     while (len--)
 292         sum += *mp++;
 293
 294     return sum & 0xFF;
 295 }
 296
 297 static int smp_scan_config(unsigned long base, unsigned long length)
 298 {
 299     unsigned long *bp = (unsigned long *)base;
 300     struct intel_mp_floating *mpf;
 301
 302 //        printf("Scan SMP from %p for %ld bytes.\n", bp,length);
 303     if (sizeof(*mpf) != 16) {
 304         printf("Error: MPF size\n");
 305         return 0;
 306     }
 307
 308     while (length > 0) {
 309         mpf = (struct intel_mp_floating *)bp;
 310         if ((*bp == SMP_MAGIC_IDENT) &&
 311             (mpf->mpf_length == 1) &&
 312             !mpf_checksum((unsigned char *)bp, 16) &&
 313             ((mpf->mpf_specification == 1)
 314              || (mpf->mpf_specification == 4))) {
 315             return 1;
 316         }
 317         bp += 4;
 318         length -= 16;
 319     }
 320     return 0;
 321 }
 322
 323 int find_smp_config(void)
 324 {
 325 //        unsigned int address;
 326
 327     /*
 328      * FIXME: Linux assumes you have 640K of base ram..
 329      * this continues the error...
 330      *
 331      * 1) Scan the bottom 1K for a signature
 332      * 2) Scan the top 1K of base RAM
 333      * 3) Scan the 64K of bios
 334      */
 335     if (smp_scan_config(0x0, 0x400) ||
 336         smp_scan_config(639 * 0x400, 0x400) ||
 337         smp_scan_config(0xF0000, 0x10000))
 338         return 1;
 339     /*
 340      * If it is an SMP machine we should know now, unless the
 341      * configuration is in an EISA/MCA bus machine with an
 342      * extended bios data area.
 343      *
 344      * there is a real-mode segmented pointer pointing to the
 345      * 4K EBDA area at 0x40E, calculate and scan it here.
 346      *
 347      * NOTE! There are Linux loaders that will corrupt the EBDA
 348      * area, and as such this kind of SMP config may be less
 349      * trustworthy, simply because the SMP table may have been
 350      * stomped on during early boot. These loaders are buggy and
 351      * should be fixed.
 352      *
 353      * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
 354      */
 355
 356 //        address = get_bios_ebda();
 357 //        if (address)
 358 //                smp_scan_config(address, 0x400);
 359     return 0;
 360 }
 361
 362 void set_cpu_flags(struct cpuinfo_x86 *c, s_cpu * cpu)
 363 {
 364     cpu->flags.fpu = cpu_has(c, X86_FEATURE_FPU);
 365     cpu->flags.vme = cpu_has(c, X86_FEATURE_VME);
 366     cpu->flags.de = cpu_has(c, X86_FEATURE_DE);
 367     cpu->flags.pse = cpu_has(c, X86_FEATURE_PSE);
 368     cpu->flags.tsc = cpu_has(c, X86_FEATURE_TSC);
 369     cpu->flags.msr = cpu_has(c, X86_FEATURE_MSR);
 370     cpu->flags.pae = cpu_has(c, X86_FEATURE_PAE);
 371     cpu->flags.mce = cpu_has(c, X86_FEATURE_MCE);
 372     cpu->flags.cx8 = cpu_has(c, X86_FEATURE_CX8);
 373     cpu->flags.apic = cpu_has(c, X86_FEATURE_APIC);
 374     cpu->flags.sep = cpu_has(c, X86_FEATURE_SEP);
 375     cpu->flags.mtrr = cpu_has(c, X86_FEATURE_MTRR);
 376     cpu->flags.pge = cpu_has(c, X86_FEATURE_PGE);
 377     cpu->flags.mca = cpu_has(c, X86_FEATURE_MCA);
 378     cpu->flags.cmov = cpu_has(c, X86_FEATURE_CMOV);
 379     cpu->flags.pat = cpu_has(c, X86_FEATURE_PAT);
 380     cpu->flags.pse_36 = cpu_has(c, X86_FEATURE_PSE36);
 381     cpu->flags.psn = cpu_has(c, X86_FEATURE_PN);
 382     cpu->flags.clflsh = cpu_has(c, X86_FEATURE_CLFLSH);
 383     cpu->flags.dts = cpu_has(c, X86_FEATURE_DTES);
 384     cpu->flags.acpi = cpu_has(c, X86_FEATURE_ACPI);
 385     cpu->flags.pbe = cpu_has(c, X86_FEATURE_PBE);
 386     cpu->flags.mmx = cpu_has(c, X86_FEATURE_MMX);
 387     cpu->flags.fxsr = cpu_has(c, X86_FEATURE_FXSR);
 388     cpu->flags.sse = cpu_has(c, X86_FEATURE_XMM);
 389     cpu->flags.sse2 = cpu_has(c, X86_FEATURE_XMM2);
 390     cpu->flags.ss = cpu_has(c, X86_FEATURE_SELFSNOOP);
 391     cpu->flags.htt = cpu_has(c, X86_FEATURE_HT);
 392     cpu->flags.acc = cpu_has(c, X86_FEATURE_ACC);
 393     cpu->flags.syscall = cpu_has(c, X86_FEATURE_SYSCALL);
 394     cpu->flags.mp = cpu_has(c, X86_FEATURE_MP);
 395     cpu->flags.nx = cpu_has(c, X86_FEATURE_NX);
 396     cpu->flags.mmxext = cpu_has(c, X86_FEATURE_MMXEXT);
 397     cpu->flags.fxsr_opt = cpu_has(c, X86_FEATURE_FXSR_OPT);
 398     cpu->flags.gbpages = cpu_has(c, X86_FEATURE_GBPAGES);
 399     cpu->flags.rdtscp = cpu_has(c, X86_FEATURE_RDTSCP);
 400     cpu->flags.lm = cpu_has(c, X86_FEATURE_LM);
 401     cpu->flags.nowext = cpu_has(c, X86_FEATURE_3DNOWEXT);
 402     cpu->flags.now = cpu_has(c, X86_FEATURE_3DNOW);
 403     cpu->flags.smp = find_smp_config();
 404     cpu->flags.pni = cpu_has(c, X86_FEATURE_XMM3);
 405     cpu->flags.pclmulqd = cpu_has(c, X86_FEATURE_PCLMULQDQ);
 406     cpu->flags.dtes64 = cpu_has(c, X86_FEATURE_DTES64);
 407     cpu->flags.vmx = cpu_has(c, X86_FEATURE_VMX);
 408     cpu->flags.smx = cpu_has(c, X86_FEATURE_SMX);
 409     cpu->flags.est = cpu_has(c, X86_FEATURE_EST);
 410     cpu->flags.tm2 = cpu_has(c, X86_FEATURE_TM2);
 411     cpu->flags.sse3 = cpu_has(c, X86_FEATURE_SSE3);
 412     cpu->flags.cid = cpu_has(c, X86_FEATURE_CID);
 413     cpu->flags.fma = cpu_has(c, X86_FEATURE_FMA);
 414     cpu->flags.cx16 = cpu_has(c, X86_FEATURE_CX16);
 415     cpu->flags.xtpr = cpu_has(c, X86_FEATURE_XTPR);
 416     cpu->flags.pdcm = cpu_has(c, X86_FEATURE_PDCM);
 417     cpu->flags.dca = cpu_has(c, X86_FEATURE_DCA);
 418     cpu->flags.xmm4_1 = cpu_has(c, X86_FEATURE_XMM4_1);
 419     cpu->flags.xmm4_2 = cpu_has(c, X86_FEATURE_XMM4_2);
 420     cpu->flags.x2apic = cpu_has(c, X86_FEATURE_X2APIC);
 421     cpu->flags.movbe = cpu_has(c, X86_FEATURE_MOVBE);
 422     cpu->flags.popcnt = cpu_has(c, X86_FEATURE_POPCNT);
 423     cpu->flags.aes = cpu_has(c, X86_FEATURE_AES);
 424     cpu->flags.xsave = cpu_has(c, X86_FEATURE_XSAVE);
 425     cpu->flags.osxsave = cpu_has(c, X86_FEATURE_OSXSAVE);
 426     cpu->flags.avx = cpu_has(c, X86_FEATURE_AVX);
 427     cpu->flags.hypervisor = cpu_has(c, X86_FEATURE_HYPERVISOR);
 428     cpu->flags.ace2 = cpu_has(c, X86_FEATURE_ACE2);
 429     cpu->flags.ace2_en = cpu_has(c, X86_FEATURE_ACE2_EN);
 430     cpu->flags.phe = cpu_has(c, X86_FEATURE_PHE);
 431     cpu->flags.phe_en = cpu_has(c, X86_FEATURE_PHE_EN);
 432     cpu->flags.pmm = cpu_has(c, X86_FEATURE_PMM);
 433     cpu->flags.pmm_en = cpu_has(c, X86_FEATURE_PMM_EN);
 434     cpu->flags.extapic = cpu_has(c, X86_FEATURE_EXTAPIC);
 435     cpu->flags.cr8_legacy = cpu_has(c, X86_FEATURE_CR8_LEGACY);
 436     cpu->flags.abm = cpu_has(c, X86_FEATURE_ABM);
 437     cpu->flags.sse4a = cpu_has(c, X86_FEATURE_SSE4A);
 438     cpu->flags.misalignsse = cpu_has(c, X86_FEATURE_MISALIGNSSE);
 439     cpu->flags.nowprefetch = cpu_has(c, X86_FEATURE_3DNOWPREFETCH);
 440     cpu->flags.osvw = cpu_has(c, X86_FEATURE_OSVW);
 441     cpu->flags.ibs = cpu_has(c, X86_FEATURE_IBS);
 442     cpu->flags.sse5 = cpu_has(c, X86_FEATURE_SSE5);
 443     cpu->flags.skinit = cpu_has(c, X86_FEATURE_SKINIT);
 444     cpu->flags.wdt = cpu_has(c, X86_FEATURE_WDT);
 445     cpu->flags.ida = cpu_has(c, X86_FEATURE_IDA);
 446     cpu->flags.arat = cpu_has(c, X86_FEATURE_ARAT);
 447     cpu->flags.tpr_shadow = cpu_has(c, X86_FEATURE_TPR_SHADOW);
 448     cpu->flags.vnmi = cpu_has(c, X86_FEATURE_VNMI);
 449     cpu->flags.flexpriority = cpu_has(c, X86_FEATURE_FLEXPRIORITY);
 450     cpu->flags.ept = cpu_has(c, X86_FEATURE_EPT);
 451     cpu->flags.vpid = cpu_has(c, X86_FEATURE_VPID);
 452     cpu->flags.svm = cpu_has(c, X86_FEATURE_SVM);
 453 }
 454
 455 void set_generic_info(struct cpuinfo_x86 *c, s_cpu * cpu)
 456 {
 457     cpu->family = c->x86;
 458     cpu->vendor_id = c->x86_vendor;
 459     cpu->model_id = c->x86_model;
 460     cpu->stepping = c->x86_mask;
 461     strlcpy(cpu->vendor, cpu_devs[c->x86_vendor]->c_vendor,
 462             sizeof(cpu->vendor));
 463     strlcpy(cpu->model, c->x86_model_id, sizeof(cpu->model));
 464     cpu->num_cores = c->x86_num_cores;
 465     cpu->l1_data_cache_size = c->x86_l1_data_cache_size;
 466     cpu->l1_instruction_cache_size = c->x86_l1_instruction_cache_size;
 467     cpu->l2_cache_size = c->x86_l2_cache_size;
 468 }
 469
 470 void detect_cpu(s_cpu * cpu)
 471 {
 472     struct cpuinfo_x86 c;
 473     memset(&c,0,sizeof(c));
 474     c.x86_clflush_size = 32;
 475     c.x86_vendor = X86_VENDOR_UNKNOWN;
 476     c.cpuid_level = -1;         /* CPUID not detected */
 477     c.x86_num_cores = 1;
 478     memset(&cpu->flags, 0, sizeof(s_cpu_flags));
 479
 480     if (!have_cpuid_p())
 481         return;
 482
 483     generic_identify(&c);
 484     set_generic_info(&c, cpu);
 485     set_cpu_flags(&c, cpu);
 486 }