Merge branch 'xtensa'
[smatch.git] / target-riscv.c
blob3bba7c15ff1f68bfb3f756a3a51665e1b3fb5c0b
1 #include "lib.h"
2 #include "symbol.h"
3 #include "target.h"
4 #include "machine.h"
5 #include <string.h>
7 #define RISCV_32BIT (1 << 0)
8 #define RISCV_64BIT (1 << 1)
9 #define RISCV_MUL (1 << 2)
10 #define RISCV_DIV (1 << 3)
11 #define RISCV_ATOMIC (1 << 4)
12 #define RISCV_FLOAT (1 << 5)
13 #define RISCV_DOUBLE (1 << 6)
14 #define RISCV_FDIV (1 << 7)
15 #define RISCV_COMP (1 << 8)
16 #define RISCV_EMBD (1 << 9)
17 #define RISCV_FPU (RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
18 #define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
19 #define RISCV_ZICSR (1 << 10)
20 #define RISCV_ZIFENCEI (1 << 11)
22 static unsigned int riscv_flags;
24 static void parse_march_riscv(const char *arg)
26 static struct {
27 const char *pattern;
28 unsigned int flags;
29 } basic_sets[] = {
30 { "rv32i", RISCV_32BIT },
31 { "rv32e", RISCV_32BIT|RISCV_EMBD },
32 { "rv32g", RISCV_32BIT|RISCV_GENERIC },
33 { "rv64i", RISCV_64BIT },
34 { "rv64g", RISCV_64BIT|RISCV_GENERIC },
35 }, extensions[] = {
36 { "m", RISCV_MUL|RISCV_DIV },
37 { "a", RISCV_ATOMIC },
38 { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
39 { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
40 { "g", RISCV_GENERIC },
41 { "q", 0 },
42 { "l", 0 },
43 { "c", RISCV_COMP },
44 { "b", 0 },
45 { "j", 0 },
46 { "t", 0 },
47 { "p", 0 },
48 { "v", 0 },
49 { "n", 0 },
50 { "h", 0 },
51 { "s", 0 },
52 { "_zicsr", RISCV_ZICSR },
53 { "_zifencei", RISCV_ZIFENCEI },
55 int i;
57 for (i = 0; i < ARRAY_SIZE(basic_sets); i++) {
58 const char *pat = basic_sets[i].pattern;
59 size_t len = strlen(pat);
61 if (!strncmp(arg, pat, len)) {
62 riscv_flags |= basic_sets[i].flags;
63 arg += len;
64 goto ext;
67 die("invalid argument to '-march': '%s'\n", arg);
69 ext:
70 for (i = 0; i < ARRAY_SIZE(extensions); i++) {
71 const char *pat = extensions[i].pattern;
72 size_t len = strlen(pat);
74 if (!strncmp(arg, pat, len)) {
75 riscv_flags |= extensions[i].flags;
76 arg += len;
79 if (arg[0])
80 die("invalid argument to '-march': '%s'\n", arg);
83 static void init_riscv(const struct target *self)
85 if (arch_cmodel == CMODEL_UNKNOWN)
86 arch_cmodel = CMODEL_MEDLOW;
87 if (fpic)
88 arch_cmodel = CMODEL_PIC;
90 if (riscv_flags == 0)
91 riscv_flags = self->flags;
94 static void init_riscv32(const struct target *self)
96 fast16_ctype = &int_ctype;
97 ufast16_ctype = &uint_ctype;
98 fast32_ctype = &int_ctype;
99 ufast32_ctype = &uint_ctype;
101 init_riscv(self);
104 static void predefine_riscv(const struct target *self)
106 static const char *cmodels[CMODEL_LAST] = {
107 [CMODEL_MEDANY] = "medany",
108 [CMODEL_MEDLOW] = "medlow",
109 [CMODEL_PIC] = "pic",
111 const char *cmodel = cmodels[arch_cmodel];
113 predefine("__riscv", 1, "1");
114 predefine("__riscv_xlen", 1, "%d", ptr_ctype.bit_size);
116 if (riscv_flags & RISCV_ATOMIC)
117 predefine("__riscv_atomic", 1, "1");
118 if (riscv_flags & RISCV_COMP)
119 predefine("__riscv_compressed", 1, "1");
120 if (riscv_flags & RISCV_DIV)
121 predefine("__riscv_div", 1, "1");
122 if (riscv_flags & RISCV_EMBD)
123 predefine("__riscv_32e", 1, "1");
124 if (riscv_flags & RISCV_FPU)
125 predefine("__riscv_flen", 1, "%d", (riscv_flags & RISCV_DOUBLE) ? 64 : 32);
126 if (riscv_flags & RISCV_FDIV)
127 predefine("__riscv_fdiv", 1, "1");
128 if (riscv_flags & RISCV_FDIV)
129 predefine("__riscv_fsqrt", 1, "1");
130 if (riscv_flags & RISCV_MUL)
131 predefine("__riscv_mul", 1, "1");
132 if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV))
133 predefine("__riscv_muldiv", 1, "1");
134 if (riscv_flags & RISCV_ZICSR)
135 predefine("__riscv_zicsr", 1, "1");
136 if (riscv_flags & RISCV_ZIFENCEI)
137 predefine("__riscv_zifencei", 1, "1");
139 if (cmodel)
140 predefine_strong("__riscv_cmodel_%s", cmodel);
143 const struct target target_riscv32 = {
144 .mach = MACH_RISCV32,
145 .bitness = ARCH_LP32,
146 .big_endian = 0,
147 .unsigned_char = 1,
148 .flags = RISCV_32BIT|RISCV_GENERIC|RISCV_COMP,
150 .target_64bit = &target_riscv64,
152 .init = init_riscv32,
153 .predefine = predefine_riscv,
154 .parse_march = parse_march_riscv,
157 const struct target target_riscv64 = {
158 .mach = MACH_RISCV64,
159 .bitness = ARCH_LP64,
160 .big_endian = 0,
161 .unsigned_char = 1,
162 .has_int128 = 1,
163 .flags = RISCV_64BIT|RISCV_GENERIC|RISCV_COMP,
165 .target_32bit = &target_riscv32,
167 .init = init_riscv,
168 .predefine = predefine_riscv,
169 .parse_march = parse_march_riscv,