2 * QEMU PC System Emulator
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
45 #include <linux/if_tun.h>
53 #define DEFAULT_NETWORK_SCRIPT "/etc/qemu-ifup"
54 #define BIOS_FILENAME "bios.bin"
55 #define VGABIOS_FILENAME "vgabios.bin"
57 //#define DEBUG_UNUSED_IOPORT
59 //#define DEBUG_IRQ_LATENCY
61 /* output Bochs bios info messages */
64 /* debug IDE devices */
70 /* debug NE2000 card */
71 //#define DEBUG_NE2000
73 /* debug PC keyboard */
76 /* debug PC keyboard : only mouse */
79 #define PHYS_RAM_BASE 0xac000000
80 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
82 #define KERNEL_LOAD_ADDR 0x00100000
83 #define INITRD_LOAD_ADDR 0x00400000
84 #define KERNEL_PARAMS_ADDR 0x00090000
86 #define GUI_REFRESH_INTERVAL 30
90 /* from plex86 (BSD license) */
91 struct __attribute__ ((packed
)) linux_params
{
92 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
93 // I just padded out the VESA parts, rather than define them.
95 /* 0x000 */ uint8_t orig_x
;
96 /* 0x001 */ uint8_t orig_y
;
97 /* 0x002 */ uint16_t ext_mem_k
;
98 /* 0x004 */ uint16_t orig_video_page
;
99 /* 0x006 */ uint8_t orig_video_mode
;
100 /* 0x007 */ uint8_t orig_video_cols
;
101 /* 0x008 */ uint16_t unused1
;
102 /* 0x00a */ uint16_t orig_video_ega_bx
;
103 /* 0x00c */ uint16_t unused2
;
104 /* 0x00e */ uint8_t orig_video_lines
;
105 /* 0x00f */ uint8_t orig_video_isVGA
;
106 /* 0x010 */ uint16_t orig_video_points
;
107 /* 0x012 */ uint8_t pad0
[0x20 - 0x12]; // VESA info.
108 /* 0x020 */ uint16_t cl_magic
; // Commandline magic number (0xA33F)
109 /* 0x022 */ uint16_t cl_offset
; // Commandline offset. Address of commandline
110 // is calculated as 0x90000 + cl_offset, bu
111 // only if cl_magic == 0xA33F.
112 /* 0x024 */ uint8_t pad1
[0x40 - 0x24]; // VESA info.
114 /* 0x040 */ uint8_t apm_bios_info
[20]; // struct apm_bios_info
115 /* 0x054 */ uint8_t pad2
[0x80 - 0x54];
117 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
118 // Might be truncated?
119 /* 0x080 */ uint8_t hd0_info
[16]; // hd0-disk-parameter from intvector 0x41
120 /* 0x090 */ uint8_t hd1_info
[16]; // hd1-disk-parameter from intvector 0x46
122 // System description table truncated to 16 bytes
123 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
124 /* 0x0a0 */ uint16_t sys_description_len
;
125 /* 0x0a2 */ uint8_t sys_description_table
[14];
127 // [1] machine submodel id
131 /* 0x0b0 */ uint8_t pad3
[0x1e0 - 0xb0];
132 /* 0x1e0 */ uint32_t alt_mem_k
;
133 /* 0x1e4 */ uint8_t pad4
[4];
134 /* 0x1e8 */ uint8_t e820map_entries
;
135 /* 0x1e9 */ uint8_t eddbuf_entries
; // EDD_NR
136 /* 0x1ea */ uint8_t pad5
[0x1f1 - 0x1ea];
137 /* 0x1f1 */ uint8_t setup_sects
; // size of setup.S, number of sectors
138 /* 0x1f2 */ uint16_t mount_root_rdonly
; // MOUNT_ROOT_RDONLY (if !=0)
139 /* 0x1f4 */ uint16_t sys_size
; // size of compressed kernel-part in the
140 // (b)zImage-file (in 16 byte units, rounded up)
141 /* 0x1f6 */ uint16_t swap_dev
; // (unused AFAIK)
142 /* 0x1f8 */ uint16_t ramdisk_flags
;
143 /* 0x1fa */ uint16_t vga_mode
; // (old one)
144 /* 0x1fc */ uint16_t orig_root_dev
; // (high=Major, low=minor)
145 /* 0x1fe */ uint8_t pad6
[1];
146 /* 0x1ff */ uint8_t aux_device_info
;
147 /* 0x200 */ uint16_t jump_setup
; // Jump to start of setup code,
148 // aka "reserved" field.
149 /* 0x202 */ uint8_t setup_signature
[4]; // Signature for SETUP-header, ="HdrS"
150 /* 0x206 */ uint16_t header_format_version
; // Version number of header format;
151 /* 0x208 */ uint8_t setup_S_temp0
[8]; // Used by setup.S for communication with
152 // boot loaders, look there.
153 /* 0x210 */ uint8_t loader_type
;
158 // T=2: bootsect-loader
162 /* 0x211 */ uint8_t loadflags
;
163 // bit0 = 1: kernel is loaded high (bzImage)
164 // bit7 = 1: Heap and pointer (see below) set by boot
166 /* 0x212 */ uint16_t setup_S_temp1
;
167 /* 0x214 */ uint32_t kernel_start
;
168 /* 0x218 */ uint32_t initrd_start
;
169 /* 0x21c */ uint32_t initrd_size
;
170 /* 0x220 */ uint8_t setup_S_temp2
[4];
171 /* 0x224 */ uint16_t setup_S_heap_end_pointer
;
172 /* 0x226 */ uint8_t pad7
[0x2d0 - 0x226];
174 /* 0x2d0 : Int 15, ax=e820 memory map. */
175 // (linux/include/asm-i386/e820.h, 'struct e820entry')
178 #define E820_RESERVED 2
179 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
187 /* 0x550 */ uint8_t pad8
[0x600 - 0x550];
189 // BIOS Enhanced Disk Drive Services.
190 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
191 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
192 /* 0x600 */ uint8_t eddbuf
[0x7d4 - 0x600];
194 /* 0x7d4 */ uint8_t pad9
[0x800 - 0x7d4];
195 /* 0x800 */ uint8_t commandline
[0x800];
198 uint64_t gdt_table
[256];
199 uint64_t idt_table
[48];
202 #define KERNEL_CS 0x10
203 #define KERNEL_DS 0x18
205 #define MAX_IOPORTS 4096
207 static const char *bios_dir
= CONFIG_QEMU_SHAREDIR
;
208 char phys_ram_file
[1024];
209 CPUX86State
*global_env
;
210 CPUX86State
*cpu_single_env
;
211 IOPortReadFunc
*ioport_read_table
[3][MAX_IOPORTS
];
212 IOPortWriteFunc
*ioport_write_table
[3][MAX_IOPORTS
];
213 BlockDriverState
*bs_table
[MAX_DISKS
];
215 static DisplayState display_state
;
218 int64_t ticks_per_sec
;
220 /***********************************************************/
223 uint32_t default_ioport_readb(CPUX86State
*env
, uint32_t address
)
225 #ifdef DEBUG_UNUSED_IOPORT
226 fprintf(stderr
, "inb: port=0x%04x\n", address
);
231 void default_ioport_writeb(CPUX86State
*env
, uint32_t address
, uint32_t data
)
233 #ifdef DEBUG_UNUSED_IOPORT
234 fprintf(stderr
, "outb: port=0x%04x data=0x%02x\n", address
, data
);
238 /* default is to make two byte accesses */
239 uint32_t default_ioport_readw(CPUX86State
*env
, uint32_t address
)
242 data
= ioport_read_table
[0][address
& (MAX_IOPORTS
- 1)](env
, address
);
243 data
|= ioport_read_table
[0][(address
+ 1) & (MAX_IOPORTS
- 1)](env
, address
+ 1) << 8;
247 void default_ioport_writew(CPUX86State
*env
, uint32_t address
, uint32_t data
)
249 ioport_write_table
[0][address
& (MAX_IOPORTS
- 1)](env
, address
, data
& 0xff);
250 ioport_write_table
[0][(address
+ 1) & (MAX_IOPORTS
- 1)](env
, address
+ 1, (data
>> 8) & 0xff);
253 uint32_t default_ioport_readl(CPUX86State
*env
, uint32_t address
)
255 #ifdef DEBUG_UNUSED_IOPORT
256 fprintf(stderr
, "inl: port=0x%04x\n", address
);
261 void default_ioport_writel(CPUX86State
*env
, uint32_t address
, uint32_t data
)
263 #ifdef DEBUG_UNUSED_IOPORT
264 fprintf(stderr
, "outl: port=0x%04x data=0x%02x\n", address
, data
);
268 void init_ioports(void)
272 for(i
= 0; i
< MAX_IOPORTS
; i
++) {
273 ioport_read_table
[0][i
] = default_ioport_readb
;
274 ioport_write_table
[0][i
] = default_ioport_writeb
;
275 ioport_read_table
[1][i
] = default_ioport_readw
;
276 ioport_write_table
[1][i
] = default_ioport_writew
;
277 ioport_read_table
[2][i
] = default_ioport_readl
;
278 ioport_write_table
[2][i
] = default_ioport_writel
;
282 /* size is the word size in byte */
283 int register_ioport_read(int start
, int length
, IOPortReadFunc
*func
, int size
)
295 for(i
= start
; i
< start
+ length
; i
+= size
)
296 ioport_read_table
[bsize
][i
] = func
;
300 /* size is the word size in byte */
301 int register_ioport_write(int start
, int length
, IOPortWriteFunc
*func
, int size
)
313 for(i
= start
; i
< start
+ length
; i
+= size
)
314 ioport_write_table
[bsize
][i
] = func
;
318 void pstrcpy(char *buf
, int buf_size
, const char *str
)
328 if (c
== 0 || q
>= buf
+ buf_size
- 1)
335 /* strcat and truncate. */
336 char *pstrcat(char *buf
, int buf_size
, const char *s
)
341 pstrcpy(buf
+ len
, buf_size
- len
, s
);
345 int load_kernel(const char *filename
, uint8_t *addr
)
347 int fd
, size
, setup_sects
;
348 uint8_t bootsect
[512];
350 fd
= open(filename
, O_RDONLY
);
353 if (read(fd
, bootsect
, 512) != 512)
355 setup_sects
= bootsect
[0x1F1];
358 /* skip 16 bit setup code */
359 lseek(fd
, (setup_sects
+ 1) * 512, SEEK_SET
);
360 size
= read(fd
, addr
, 16 * 1024 * 1024);
370 /* return the size or -1 if error */
371 int load_image(const char *filename
, uint8_t *addr
)
374 fd
= open(filename
, O_RDONLY
);
377 size
= lseek(fd
, 0, SEEK_END
);
378 lseek(fd
, 0, SEEK_SET
);
379 if (read(fd
, addr
, size
) != size
) {
387 void cpu_x86_outb(CPUX86State
*env
, int addr
, int val
)
389 ioport_write_table
[0][addr
& (MAX_IOPORTS
- 1)](env
, addr
, val
);
392 void cpu_x86_outw(CPUX86State
*env
, int addr
, int val
)
394 ioport_write_table
[1][addr
& (MAX_IOPORTS
- 1)](env
, addr
, val
);
397 void cpu_x86_outl(CPUX86State
*env
, int addr
, int val
)
399 ioport_write_table
[2][addr
& (MAX_IOPORTS
- 1)](env
, addr
, val
);
402 int cpu_x86_inb(CPUX86State
*env
, int addr
)
404 return ioport_read_table
[0][addr
& (MAX_IOPORTS
- 1)](env
, addr
);
407 int cpu_x86_inw(CPUX86State
*env
, int addr
)
409 return ioport_read_table
[1][addr
& (MAX_IOPORTS
- 1)](env
, addr
);
412 int cpu_x86_inl(CPUX86State
*env
, int addr
)
414 return ioport_read_table
[2][addr
& (MAX_IOPORTS
- 1)](env
, addr
);
417 /***********************************************************/
418 void ioport80_write(CPUX86State
*env
, uint32_t addr
, uint32_t data
)
422 void hw_error(const char *fmt
, ...)
427 fprintf(stderr
, "qemu: hardware error: ");
428 vfprintf(stderr
, fmt
, ap
);
429 fprintf(stderr
, "\n");
431 cpu_x86_dump_state(global_env
, stderr
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
437 /***********************************************************/
440 #define RTC_SECONDS 0
441 #define RTC_SECONDS_ALARM 1
442 #define RTC_MINUTES 2
443 #define RTC_MINUTES_ALARM 3
445 #define RTC_HOURS_ALARM 5
446 #define RTC_ALARM_DONT_CARE 0xC0
448 #define RTC_DAY_OF_WEEK 6
449 #define RTC_DAY_OF_MONTH 7
458 /* PC cmos mappings */
459 #define REG_EQUIPMENT_BYTE 0x14
461 uint8_t cmos_data
[128];
464 void cmos_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t data
)
467 cmos_index
= data
& 0x7f;
471 uint32_t cmos_ioport_read(CPUX86State
*env
, uint32_t addr
)
478 /* toggle update-in-progress bit for Linux (same hack as
480 ret
= cmos_data
[cmos_index
];
481 if (cmos_index
== RTC_REG_A
)
482 cmos_data
[RTC_REG_A
] ^= 0x80;
483 else if (cmos_index
== RTC_REG_C
)
484 cmos_data
[RTC_REG_C
] = 0x00;
490 static inline int to_bcd(int a
)
492 return ((a
/ 10) << 4) | (a
% 10);
503 cmos_data
[RTC_SECONDS
] = to_bcd(tm
->tm_sec
);
504 cmos_data
[RTC_MINUTES
] = to_bcd(tm
->tm_min
);
505 cmos_data
[RTC_HOURS
] = to_bcd(tm
->tm_hour
);
506 cmos_data
[RTC_DAY_OF_WEEK
] = to_bcd(tm
->tm_wday
);
507 cmos_data
[RTC_DAY_OF_MONTH
] = to_bcd(tm
->tm_mday
);
508 cmos_data
[RTC_MONTH
] = to_bcd(tm
->tm_mon
+ 1);
509 cmos_data
[RTC_YEAR
] = to_bcd(tm
->tm_year
% 100);
511 cmos_data
[RTC_REG_A
] = 0x26;
512 cmos_data
[RTC_REG_B
] = 0x02;
513 cmos_data
[RTC_REG_C
] = 0x00;
514 cmos_data
[RTC_REG_D
] = 0x80;
516 /* various important CMOS locations needed by PC/Bochs bios */
518 cmos_data
[REG_EQUIPMENT_BYTE
] = 0x02; /* FPU is there */
519 cmos_data
[REG_EQUIPMENT_BYTE
] |= 0x04; /* PS/2 mouse installed */
522 val
= (phys_ram_size
/ 1024) - 1024;
525 cmos_data
[0x17] = val
;
526 cmos_data
[0x18] = val
>> 8;
527 cmos_data
[0x30] = val
;
528 cmos_data
[0x31] = val
>> 8;
530 val
= (phys_ram_size
/ 65536) - ((16 * 1024 * 1024) / 65536);
533 cmos_data
[0x34] = val
;
534 cmos_data
[0x35] = val
>> 8;
536 cmos_data
[0x3d] = 0x02; /* hard drive boot */
538 register_ioport_write(0x70, 2, cmos_ioport_write
, 1);
539 register_ioport_read(0x70, 2, cmos_ioport_read
, 1);
542 /***********************************************************/
543 /* 8259 pic emulation */
545 typedef struct PicState
{
546 uint8_t last_irr
; /* edge detection */
547 uint8_t irr
; /* interrupt request register */
548 uint8_t imr
; /* interrupt mask register */
549 uint8_t isr
; /* interrupt service register */
550 uint8_t priority_add
; /* used to compute irq priority */
552 uint8_t read_reg_select
;
553 uint8_t special_mask
;
556 uint8_t rotate_on_autoeoi
;
557 uint8_t init4
; /* true if 4 byte init */
560 /* 0 is master pic, 1 is slave pic */
562 int pic_irq_requested
;
564 /* set irq level. If an edge is detected, then the IRR is set to 1 */
565 static inline void pic_set_irq1(PicState
*s
, int irq
, int level
)
570 if ((s
->last_irr
& mask
) == 0)
574 s
->last_irr
&= ~mask
;
578 static inline int get_priority(PicState
*s
, int mask
)
584 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
589 /* return the pic wanted interrupt. return -1 if none */
590 static int pic_get_irq(PicState
*s
)
592 int mask
, cur_priority
, priority
;
594 mask
= s
->irr
& ~s
->imr
;
595 priority
= get_priority(s
, mask
);
598 /* compute current priority */
599 cur_priority
= get_priority(s
, s
->isr
);
600 if (priority
> cur_priority
) {
601 /* higher priority found: an irq should be generated */
608 /* raise irq to CPU if necessary. must be called every time the active
610 static void pic_update_irq(void)
614 /* first look at slave pic */
615 irq2
= pic_get_irq(&pics
[1]);
617 /* if irq request by slave pic, signal master PIC */
618 pic_set_irq1(&pics
[0], 2, 1);
619 pic_set_irq1(&pics
[0], 2, 0);
621 /* look at requested irq */
622 irq
= pic_get_irq(&pics
[0]);
626 pic_irq_requested
= 8 + irq2
;
628 /* from master pic */
629 pic_irq_requested
= irq
;
631 cpu_x86_interrupt(global_env
, CPU_INTERRUPT_HARD
);
635 #ifdef DEBUG_IRQ_LATENCY
636 int64_t irq_time
[16];
637 int64_t cpu_get_ticks(void);
639 #if defined(DEBUG_PIC)
643 void pic_set_irq(int irq
, int level
)
645 #if defined(DEBUG_PIC)
646 if (level
!= irq_level
[irq
]) {
647 printf("pic_set_irq: irq=%d level=%d\n", irq
, level
);
648 irq_level
[irq
] = level
;
651 #ifdef DEBUG_IRQ_LATENCY
653 irq_time
[irq
] = cpu_get_ticks();
656 pic_set_irq1(&pics
[irq
>> 3], irq
& 7, level
);
660 int cpu_x86_get_pic_interrupt(CPUX86State
*env
)
662 int irq
, irq2
, intno
;
664 /* signal the pic that the irq was acked by the CPU */
665 irq
= pic_irq_requested
;
666 #ifdef DEBUG_IRQ_LATENCY
667 printf("IRQ%d latency=%0.3fus\n",
669 (double)(cpu_get_ticks() - irq_time
[irq
]) * 1000000.0 / ticks_per_sec
);
672 printf("pic_interrupt: irq=%d\n", irq
);
677 pics
[1].isr
|= (1 << irq2
);
678 pics
[1].irr
&= ~(1 << irq2
);
680 intno
= pics
[1].irq_base
+ irq2
;
682 intno
= pics
[0].irq_base
+ irq
;
684 pics
[0].isr
|= (1 << irq
);
685 pics
[0].irr
&= ~(1 << irq
);
689 void pic_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
695 printf("pic_write: addr=0x%02x val=0x%02x\n", addr
, val
);
697 s
= &pics
[addr
>> 7];
702 memset(s
, 0, sizeof(PicState
));
706 hw_error("single mode not supported");
708 hw_error("level sensitive irq not supported");
709 } else if (val
& 0x08) {
711 s
->read_reg_select
= val
& 1;
713 s
->special_mask
= (val
>> 5) & 1;
718 s
->rotate_on_autoeoi
= val
>> 7;
720 case 0x20: /* end of interrupt */
722 priority
= get_priority(s
, s
->isr
);
724 s
->isr
&= ~(1 << ((priority
+ s
->priority_add
) & 7));
727 s
->priority_add
= (s
->priority_add
+ 1) & 7;
732 s
->isr
&= ~(1 << priority
);
736 s
->priority_add
= (val
+ 1) & 7;
741 s
->isr
&= ~(1 << priority
);
742 s
->priority_add
= (priority
+ 1) & 7;
748 switch(s
->init_state
) {
755 s
->irq_base
= val
& 0xf8;
766 s
->auto_eoi
= (val
>> 1) & 1;
773 uint32_t pic_ioport_read(CPUX86State
*env
, uint32_t addr1
)
780 s
= &pics
[addr
>> 7];
783 if (s
->read_reg_select
)
791 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1
, ret
);
798 register_ioport_write(0x20, 2, pic_ioport_write
, 1);
799 register_ioport_read(0x20, 2, pic_ioport_read
, 1);
800 register_ioport_write(0xa0, 2, pic_ioport_write
, 1);
801 register_ioport_read(0xa0, 2, pic_ioport_read
, 1);
804 /***********************************************************/
805 /* 8253 PIT emulation */
807 #define PIT_FREQ 1193182
809 #define RW_STATE_LSB 0
810 #define RW_STATE_MSB 1
811 #define RW_STATE_WORD0 2
812 #define RW_STATE_WORD1 3
813 #define RW_STATE_LATCHED_WORD0 4
814 #define RW_STATE_LATCHED_WORD1 5
816 typedef struct PITChannelState
{
817 int count
; /* can be 65536 */
818 uint16_t latched_count
;
821 uint8_t bcd
; /* not supported */
822 uint8_t gate
; /* timer start */
823 int64_t count_load_time
;
824 int64_t count_last_edge_check_time
;
827 PITChannelState pit_channels
[3];
829 int dummy_refresh_clock
;
830 int pit_min_timer_count
= 0;
833 #if defined(__powerpc__)
835 static inline uint32_t get_tbl(void)
838 asm volatile("mftb %0" : "=r" (tbl
));
842 static inline uint32_t get_tbu(void)
845 asm volatile("mftbu %0" : "=r" (tbl
));
849 int64_t cpu_get_real_ticks(void)
852 /* NOTE: we test if wrapping has occurred */
858 return ((int64_t)h
<< 32) | l
;
861 #elif defined(__i386__)
863 int64_t cpu_get_real_ticks(void)
866 asm("rdtsc" : "=A" (val
));
871 #error unsupported CPU
874 static int64_t cpu_ticks_offset
;
875 static int64_t cpu_ticks_last
;
877 int64_t cpu_get_ticks(void)
879 return cpu_get_real_ticks() + cpu_ticks_offset
;
882 /* enable cpu_get_ticks() */
883 void cpu_enable_ticks(void)
885 cpu_ticks_offset
= cpu_ticks_last
- cpu_get_real_ticks();
888 /* disable cpu_get_ticks() : the clock is stopped. You must not call
889 cpu_get_ticks() after that. */
890 void cpu_disable_ticks(void)
892 cpu_ticks_last
= cpu_get_ticks();
895 int64_t get_clock(void)
898 gettimeofday(&tv
, NULL
);
899 return tv
.tv_sec
* 1000000LL + tv
.tv_usec
;
902 void cpu_calibrate_ticks(void)
907 ticks
= cpu_get_ticks();
909 usec
= get_clock() - usec
;
910 ticks
= cpu_get_ticks() - ticks
;
911 ticks_per_sec
= (ticks
* 1000000LL + (usec
>> 1)) / usec
;
914 /* compute with 96 bit intermediate result: (a*b)/c */
915 static uint64_t muldiv64(uint64_t a
, uint32_t b
, uint32_t c
)
920 #ifdef WORDS_BIGENDIAN
930 rl
= (uint64_t)u
.l
.low
* (uint64_t)b
;
931 rh
= (uint64_t)u
.l
.high
* (uint64_t)b
;
934 res
.l
.low
= (((rh
% c
) << 32) + (rl
& 0xffffffff)) / c
;
938 static int pit_get_count(PITChannelState
*s
)
943 d
= muldiv64(cpu_get_ticks() - s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
949 counter
= (s
->count
- d
) & 0xffff;
952 counter
= s
->count
- (d
% s
->count
);
958 /* get pit output bit */
959 static int pit_get_out(PITChannelState
*s
)
964 d
= muldiv64(cpu_get_ticks() - s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
968 out
= (d
>= s
->count
);
971 out
= (d
< s
->count
);
974 if ((d
% s
->count
) == 0 && d
!= 0)
980 out
= (d
% s
->count
) < (s
->count
>> 1);
984 out
= (d
== s
->count
);
990 /* get the number of 0 to 1 transitions we had since we call this
992 /* XXX: maybe better to use ticks precision to avoid getting edges
993 twice if checks are done at very small intervals */
994 static int pit_get_out_edges(PITChannelState
*s
)
1000 ticks
= cpu_get_ticks();
1001 d1
= muldiv64(s
->count_last_edge_check_time
- s
->count_load_time
,
1002 PIT_FREQ
, ticks_per_sec
);
1003 d2
= muldiv64(ticks
- s
->count_load_time
,
1004 PIT_FREQ
, ticks_per_sec
);
1005 s
->count_last_edge_check_time
= ticks
;
1009 if (d1
< s
->count
&& d2
>= s
->count
)
1023 v
= s
->count
- (s
->count
>> 1);
1024 d1
= (d1
+ v
) / s
->count
;
1025 d2
= (d2
+ v
) / s
->count
;
1030 if (d1
< s
->count
&& d2
>= s
->count
)
1039 static inline void pit_load_count(PITChannelState
*s
, int val
)
1043 s
->count_load_time
= cpu_get_ticks();
1044 s
->count_last_edge_check_time
= s
->count_load_time
;
1046 if (s
== &pit_channels
[0] && val
<= pit_min_timer_count
) {
1048 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
1049 PIT_FREQ
/ pit_min_timer_count
);
1053 void pit_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1055 int channel
, access
;
1063 s
= &pit_channels
[channel
];
1064 access
= (val
>> 4) & 3;
1067 s
->latched_count
= pit_get_count(s
);
1068 s
->rw_state
= RW_STATE_LATCHED_WORD0
;
1071 s
->mode
= (val
>> 1) & 7;
1073 s
->rw_state
= access
- 1 + RW_STATE_LSB
;
1077 s
= &pit_channels
[addr
];
1078 switch(s
->rw_state
) {
1080 pit_load_count(s
, val
);
1083 pit_load_count(s
, val
<< 8);
1085 case RW_STATE_WORD0
:
1086 case RW_STATE_WORD1
:
1087 if (s
->rw_state
& 1) {
1088 pit_load_count(s
, (s
->latched_count
& 0xff) | (val
<< 8));
1090 s
->latched_count
= val
;
1098 uint32_t pit_ioport_read(CPUX86State
*env
, uint32_t addr
)
1104 s
= &pit_channels
[addr
];
1105 switch(s
->rw_state
) {
1108 case RW_STATE_WORD0
:
1109 case RW_STATE_WORD1
:
1110 count
= pit_get_count(s
);
1111 if (s
->rw_state
& 1)
1112 ret
= (count
>> 8) & 0xff;
1115 if (s
->rw_state
& 2)
1119 case RW_STATE_LATCHED_WORD0
:
1120 case RW_STATE_LATCHED_WORD1
:
1121 if (s
->rw_state
& 1)
1122 ret
= s
->latched_count
>> 8;
1124 ret
= s
->latched_count
& 0xff;
1131 void speaker_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1133 speaker_data_on
= (val
>> 1) & 1;
1134 pit_channels
[2].gate
= val
& 1;
1137 uint32_t speaker_ioport_read(CPUX86State
*env
, uint32_t addr
)
1140 out
= pit_get_out(&pit_channels
[2]);
1141 dummy_refresh_clock
^= 1;
1142 return (speaker_data_on
<< 1) | pit_channels
[2].gate
| (out
<< 5) |
1143 (dummy_refresh_clock
<< 4);
1151 cpu_calibrate_ticks();
1153 for(i
= 0;i
< 3; i
++) {
1154 s
= &pit_channels
[i
];
1157 pit_load_count(s
, 0);
1160 register_ioport_write(0x40, 4, pit_ioport_write
, 1);
1161 register_ioport_read(0x40, 3, pit_ioport_read
, 1);
1163 register_ioport_read(0x61, 1, speaker_ioport_read
, 1);
1164 register_ioport_write(0x61, 1, speaker_ioport_write
, 1);
1167 /***********************************************************/
1168 /* serial port emulation */
1172 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1174 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1175 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1176 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1177 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1179 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1180 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1182 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1183 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1184 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1185 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1187 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1188 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1189 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1190 #define UART_LSR_FE 0x08 /* Frame error indicator */
1191 #define UART_LSR_PE 0x04 /* Parity error indicator */
1192 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1193 #define UART_LSR_DR 0x01 /* Receiver data ready */
1195 typedef struct SerialState
{
1197 uint8_t rbr
; /* receive register */
1199 uint8_t iir
; /* read only */
1202 uint8_t lsr
; /* read only */
1207 SerialState serial_ports
[1];
1209 void serial_update_irq(void)
1211 SerialState
*s
= &serial_ports
[0];
1213 if ((s
->lsr
& UART_LSR_DR
) && (s
->ier
& UART_IER_RDI
)) {
1214 s
->iir
= UART_IIR_RDI
;
1215 } else if ((s
->lsr
& UART_LSR_THRE
) && (s
->ier
& UART_IER_THRI
)) {
1216 s
->iir
= UART_IIR_THRI
;
1218 s
->iir
= UART_IIR_NO_INT
;
1220 if (s
->iir
!= UART_IIR_NO_INT
) {
1221 pic_set_irq(UART_IRQ
, 1);
1223 pic_set_irq(UART_IRQ
, 0);
1227 void serial_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1229 SerialState
*s
= &serial_ports
[0];
1237 if (s
->lcr
& UART_LCR_DLAB
) {
1238 s
->divider
= (s
->divider
& 0xff00) | val
;
1240 s
->lsr
&= ~UART_LSR_THRE
;
1241 serial_update_irq();
1245 ret
= write(1, &ch
, 1);
1247 s
->lsr
|= UART_LSR_THRE
;
1248 s
->lsr
|= UART_LSR_TEMT
;
1249 serial_update_irq();
1253 if (s
->lcr
& UART_LCR_DLAB
) {
1254 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
1257 serial_update_irq();
1279 uint32_t serial_ioport_read(CPUX86State
*env
, uint32_t addr
)
1281 SerialState
*s
= &serial_ports
[0];
1288 if (s
->lcr
& UART_LCR_DLAB
) {
1289 ret
= s
->divider
& 0xff;
1292 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
1293 serial_update_irq();
1297 if (s
->lcr
& UART_LCR_DLAB
) {
1298 ret
= (s
->divider
>> 8) & 0xff;
1325 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1326 static int term_got_escape
;
1328 void term_print_help(void)
1331 "C-a h print this help\n"
1332 "C-a x exit emulatior\n"
1333 "C-a s save disk data back to file (if -snapshot)\n"
1334 "C-a b send break (magic sysrq)\n"
1335 "C-a C-a send C-a\n"
1339 /* called when a char is received */
1340 void serial_received_byte(SerialState
*s
, int ch
)
1342 if (term_got_escape
) {
1343 term_got_escape
= 0;
1354 for (i
= 0; i
< MAX_DISKS
; i
++) {
1356 bdrv_commit(bs_table
[i
]);
1363 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
1364 serial_update_irq();
1369 } else if (ch
== TERM_ESCAPE
) {
1370 term_got_escape
= 1;
1374 s
->lsr
|= UART_LSR_DR
;
1375 serial_update_irq();
1379 void serial_init(void)
1381 SerialState
*s
= &serial_ports
[0];
1383 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
1385 register_ioport_write(0x3f8, 8, serial_ioport_write
, 1);
1386 register_ioport_read(0x3f8, 8, serial_ioport_read
, 1);
1389 /***********************************************************/
1390 /* ne2000 emulation */
1392 #define NE2000_IOPORT 0x300
1393 #define NE2000_IRQ 9
1395 #define MAX_ETH_FRAME_SIZE 1514
1397 #define E8390_CMD 0x00 /* The command register (for all pages) */
1398 /* Page 0 register offsets. */
1399 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1400 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1401 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1402 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1403 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1404 #define EN0_TSR 0x04 /* Transmit status reg RD */
1405 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1406 #define EN0_NCR 0x05 /* Number of collision reg RD */
1407 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1408 #define EN0_FIFO 0x06 /* FIFO RD */
1409 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1410 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1411 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1412 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1413 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1414 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1415 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1416 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1417 #define EN0_RSR 0x0c /* rx status reg RD */
1418 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1419 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1420 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1421 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1422 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1423 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1424 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1426 #define EN1_PHYS 0x11
1427 #define EN1_CURPAG 0x17
1428 #define EN1_MULT 0x18
1430 /* Register accessed at EN_CMD, the 8390 base addr. */
1431 #define E8390_STOP 0x01 /* Stop and reset the chip */
1432 #define E8390_START 0x02 /* Start the chip, clear reset */
1433 #define E8390_TRANS 0x04 /* Transmit a frame */
1434 #define E8390_RREAD 0x08 /* Remote read */
1435 #define E8390_RWRITE 0x10 /* Remote write */
1436 #define E8390_NODMA 0x20 /* Remote DMA */
1437 #define E8390_PAGE0 0x00 /* Select page chip registers */
1438 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1439 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1441 /* Bits in EN0_ISR - Interrupt status register */
1442 #define ENISR_RX 0x01 /* Receiver, no error */
1443 #define ENISR_TX 0x02 /* Transmitter, no error */
1444 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1445 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1446 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1447 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1448 #define ENISR_RDC 0x40 /* remote dma complete */
1449 #define ENISR_RESET 0x80 /* Reset completed */
1450 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1452 /* Bits in received packet status byte and EN0_RSR*/
1453 #define ENRSR_RXOK 0x01 /* Received a good packet */
1454 #define ENRSR_CRC 0x02 /* CRC error */
1455 #define ENRSR_FAE 0x04 /* frame alignment error */
1456 #define ENRSR_FO 0x08 /* FIFO overrun */
1457 #define ENRSR_MPA 0x10 /* missed pkt */
1458 #define ENRSR_PHY 0x20 /* physical/multicast address */
1459 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1460 #define ENRSR_DEF 0x80 /* deferring */
1462 /* Transmitted packet status, EN0_TSR. */
1463 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1464 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1465 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1466 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1467 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1468 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1469 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1470 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1472 #define NE2000_MEM_SIZE 32768
1474 typedef struct NE2000State
{
1487 uint8_t phys
[6]; /* mac address */
1489 uint8_t mult
[8]; /* multicast mask array */
1490 uint8_t mem
[NE2000_MEM_SIZE
];
1493 NE2000State ne2000_state
;
1495 char network_script
[1024];
1497 void ne2000_reset(void)
1499 NE2000State
*s
= &ne2000_state
;
1502 s
->isr
= ENISR_RESET
;
1512 /* duplicate prom data */
1513 for(i
= 15;i
>= 0; i
--) {
1514 s
->mem
[2 * i
] = s
->mem
[i
];
1515 s
->mem
[2 * i
+ 1] = s
->mem
[i
];
1519 void ne2000_update_irq(NE2000State
*s
)
1522 isr
= s
->isr
& s
->imr
;
1524 pic_set_irq(NE2000_IRQ
, 1);
1526 pic_set_irq(NE2000_IRQ
, 0);
1532 int fd
, ret
, pid
, status
;
1534 fd
= open("/dev/net/tun", O_RDWR
);
1536 fprintf(stderr
, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1539 memset(&ifr
, 0, sizeof(ifr
));
1540 ifr
.ifr_flags
= IFF_TAP
| IFF_NO_PI
;
1541 pstrcpy(ifr
.ifr_name
, IFNAMSIZ
, "tun%d");
1542 ret
= ioctl(fd
, TUNSETIFF
, (void *) &ifr
);
1544 fprintf(stderr
, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1548 printf("Connected to host network interface: %s\n", ifr
.ifr_name
);
1549 fcntl(fd
, F_SETFL
, O_NONBLOCK
);
1552 /* try to launch network init script */
1556 execl(network_script
, network_script
, ifr
.ifr_name
, NULL
);
1559 while (waitpid(pid
, &status
, 0) != pid
);
1560 if (!WIFEXITED(status
) ||
1561 WEXITSTATUS(status
) != 0) {
1562 fprintf(stderr
, "%s: could not launch network script for '%s'\n",
1563 network_script
, ifr
.ifr_name
);
1569 void net_send_packet(NE2000State
*s
, const uint8_t *buf
, int size
)
1572 printf("NE2000: sending packet size=%d\n", size
);
1574 write(net_fd
, buf
, size
);
1577 /* return true if the NE2000 can receive more data */
1578 int ne2000_can_receive(NE2000State
*s
)
1580 int avail
, index
, boundary
;
1582 if (s
->cmd
& E8390_STOP
)
1584 index
= s
->curpag
<< 8;
1585 boundary
= s
->boundary
<< 8;
1586 if (index
< boundary
)
1587 avail
= boundary
- index
;
1589 avail
= (s
->stop
- s
->start
) - (index
- boundary
);
1590 if (avail
< (MAX_ETH_FRAME_SIZE
+ 4))
1595 void ne2000_receive(NE2000State
*s
, uint8_t *buf
, int size
)
1598 int total_len
, next
, avail
, len
, index
;
1600 #if defined(DEBUG_NE2000)
1601 printf("NE2000: received len=%d\n", size
);
1604 index
= s
->curpag
<< 8;
1605 /* 4 bytes for header */
1606 total_len
= size
+ 4;
1607 /* address for next packet (4 bytes for CRC) */
1608 next
= index
+ ((total_len
+ 4 + 255) & ~0xff);
1609 if (next
>= s
->stop
)
1610 next
-= (s
->stop
- s
->start
);
1611 /* prepare packet header */
1613 p
[0] = ENRSR_RXOK
; /* receive status */
1616 p
[3] = total_len
>> 8;
1619 /* write packet data */
1621 avail
= s
->stop
- index
;
1625 memcpy(s
->mem
+ index
, buf
, len
);
1628 if (index
== s
->stop
)
1632 s
->curpag
= next
>> 8;
1634 /* now we can signal we have receive something */
1636 ne2000_update_irq(s
);
1639 void ne2000_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1641 NE2000State
*s
= &ne2000_state
;
1646 printf("NE2000: write addr=0x%x val=0x%02x\n", addr
, val
);
1648 if (addr
== E8390_CMD
) {
1649 /* control register */
1651 if (val
& E8390_START
) {
1652 /* test specific case: zero length transfert */
1653 if ((val
& (E8390_RREAD
| E8390_RWRITE
)) &&
1655 s
->isr
|= ENISR_RDC
;
1656 ne2000_update_irq(s
);
1658 if (val
& E8390_TRANS
) {
1659 net_send_packet(s
, s
->mem
+ (s
->tpsr
<< 8), s
->tcnt
);
1660 /* signal end of transfert */
1663 ne2000_update_irq(s
);
1668 offset
= addr
| (page
<< 4);
1671 s
->start
= val
<< 8;
1681 ne2000_update_irq(s
);
1687 s
->tcnt
= (s
->tcnt
& 0xff00) | val
;
1690 s
->tcnt
= (s
->tcnt
& 0x00ff) | (val
<< 8);
1693 s
->rsar
= (s
->rsar
& 0xff00) | val
;
1696 s
->rsar
= (s
->rsar
& 0x00ff) | (val
<< 8);
1699 s
->rcnt
= (s
->rcnt
& 0xff00) | val
;
1702 s
->rcnt
= (s
->rcnt
& 0x00ff) | (val
<< 8);
1709 ne2000_update_irq(s
);
1711 case EN1_PHYS
... EN1_PHYS
+ 5:
1712 s
->phys
[offset
- EN1_PHYS
] = val
;
1717 case EN1_MULT
... EN1_MULT
+ 7:
1718 s
->mult
[offset
- EN1_MULT
] = val
;
1724 uint32_t ne2000_ioport_read(CPUX86State
*env
, uint32_t addr
)
1726 NE2000State
*s
= &ne2000_state
;
1727 int offset
, page
, ret
;
1730 if (addr
== E8390_CMD
) {
1734 offset
= addr
| (page
<< 4);
1745 case EN1_PHYS
... EN1_PHYS
+ 5:
1746 ret
= s
->phys
[offset
- EN1_PHYS
];
1751 case EN1_MULT
... EN1_MULT
+ 7:
1752 ret
= s
->mult
[offset
- EN1_MULT
];
1760 printf("NE2000: read addr=0x%x val=%02x\n", addr
, ret
);
1765 void ne2000_asic_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1767 NE2000State
*s
= &ne2000_state
;
1771 printf("NE2000: asic write val=0x%04x\n", val
);
1773 p
= s
->mem
+ s
->rsar
;
1774 if (s
->dcfg
& 0x01) {
1787 if (s
->rsar
== s
->stop
)
1790 /* signal end of transfert */
1791 s
->isr
|= ENISR_RDC
;
1792 ne2000_update_irq(s
);
1796 uint32_t ne2000_asic_ioport_read(CPUX86State
*env
, uint32_t addr
)
1798 NE2000State
*s
= &ne2000_state
;
1802 p
= s
->mem
+ s
->rsar
;
1803 if (s
->dcfg
& 0x01) {
1805 ret
= p
[0] | (p
[1] << 8);
1815 if (s
->rsar
== s
->stop
)
1818 /* signal end of transfert */
1819 s
->isr
|= ENISR_RDC
;
1820 ne2000_update_irq(s
);
1823 printf("NE2000: asic read val=0x%04x\n", ret
);
1828 void ne2000_reset_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
1830 /* nothing to do (end of reset pulse) */
1833 uint32_t ne2000_reset_ioport_read(CPUX86State
*env
, uint32_t addr
)
1839 void ne2000_init(void)
1841 register_ioport_write(NE2000_IOPORT
, 16, ne2000_ioport_write
, 1);
1842 register_ioport_read(NE2000_IOPORT
, 16, ne2000_ioport_read
, 1);
1844 register_ioport_write(NE2000_IOPORT
+ 0x10, 1, ne2000_asic_ioport_write
, 1);
1845 register_ioport_read(NE2000_IOPORT
+ 0x10, 1, ne2000_asic_ioport_read
, 1);
1846 register_ioport_write(NE2000_IOPORT
+ 0x10, 2, ne2000_asic_ioport_write
, 2);
1847 register_ioport_read(NE2000_IOPORT
+ 0x10, 2, ne2000_asic_ioport_read
, 2);
1849 register_ioport_write(NE2000_IOPORT
+ 0x1f, 1, ne2000_reset_ioport_write
, 1);
1850 register_ioport_read(NE2000_IOPORT
+ 0x1f, 1, ne2000_reset_ioport_read
, 1);
1854 /***********************************************************/
1857 /* Bits of HD_STATUS */
1858 #define ERR_STAT 0x01
1859 #define INDEX_STAT 0x02
1860 #define ECC_STAT 0x04 /* Corrected error */
1861 #define DRQ_STAT 0x08
1862 #define SEEK_STAT 0x10
1863 #define SRV_STAT 0x10
1864 #define WRERR_STAT 0x20
1865 #define READY_STAT 0x40
1866 #define BUSY_STAT 0x80
1868 /* Bits for HD_ERROR */
1869 #define MARK_ERR 0x01 /* Bad address mark */
1870 #define TRK0_ERR 0x02 /* couldn't find track 0 */
1871 #define ABRT_ERR 0x04 /* Command aborted */
1872 #define MCR_ERR 0x08 /* media change request */
1873 #define ID_ERR 0x10 /* ID field not found */
1874 #define MC_ERR 0x20 /* media changed */
1875 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
1876 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1877 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1879 /* Bits of HD_NSECTOR */
1883 #define TAG_MASK 0xf8
1885 #define IDE_CMD_RESET 0x04
1886 #define IDE_CMD_DISABLE_IRQ 0x02
1888 /* ATA/ATAPI Commands pre T13 Spec */
1889 #define WIN_NOP 0x00
1891 * 0x01->0x02 Reserved
1893 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1895 * 0x04->0x07 Reserved
1897 #define WIN_SRST 0x08 /* ATAPI soft reset command */
1898 #define WIN_DEVICE_RESET 0x08
1900 * 0x09->0x0F Reserved
1902 #define WIN_RECAL 0x10
1903 #define WIN_RESTORE WIN_RECAL
1905 * 0x10->0x1F Reserved
1907 #define WIN_READ 0x20 /* 28-Bit */
1908 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1909 #define WIN_READ_LONG 0x22 /* 28-Bit */
1910 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1911 #define WIN_READ_EXT 0x24 /* 48-Bit */
1912 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
1913 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1914 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1918 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1920 * 0x2A->0x2F Reserved
1922 #define WIN_WRITE 0x30 /* 28-Bit */
1923 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1924 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
1925 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1926 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
1927 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1928 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1929 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1930 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1931 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1933 * 0x3A->0x3B Reserved
1935 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1937 * 0x3D->0x3F Reserved
1939 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1940 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1941 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1943 * 0x43->0x4F Reserved
1945 #define WIN_FORMAT 0x50
1947 * 0x51->0x5F Reserved
1949 #define WIN_INIT 0x60
1951 * 0x61->0x5F Reserved
1953 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1954 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1955 #define WIN_DIAGNOSE 0x90
1956 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
1957 #define WIN_DOWNLOAD_MICROCODE 0x92
1958 #define WIN_STANDBYNOW2 0x94
1959 #define WIN_STANDBY2 0x96
1960 #define WIN_SETIDLE2 0x97
1961 #define WIN_CHECKPOWERMODE2 0x98
1962 #define WIN_SLEEPNOW2 0x99
1966 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1967 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1968 #define WIN_QUEUED_SERVICE 0xA2
1969 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
1970 #define CFA_ERASE_SECTORS 0xC0
1971 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1972 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1973 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1974 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1975 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1976 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1977 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1978 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1979 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1980 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1981 #define WIN_GETMEDIASTATUS 0xDA
1982 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1983 #define WIN_POSTBOOT 0xDC
1984 #define WIN_PREBOOT 0xDD
1985 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1986 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1987 #define WIN_STANDBYNOW1 0xE0
1988 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
1989 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
1990 #define WIN_SETIDLE1 0xE3
1991 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
1992 #define WIN_CHECKPOWERMODE1 0xE5
1993 #define WIN_SLEEPNOW1 0xE6
1994 #define WIN_FLUSH_CACHE 0xE7
1995 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
1996 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
1997 /* SET_FEATURES 0x22 or 0xDD */
1998 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
1999 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
2000 #define WIN_MEDIAEJECT 0xED
2001 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
2002 #define WIN_SETFEATURES 0xEF /* set special drive features */
2003 #define EXABYTE_ENABLE_NEST 0xF0
2004 #define WIN_SECURITY_SET_PASS 0xF1
2005 #define WIN_SECURITY_UNLOCK 0xF2
2006 #define WIN_SECURITY_ERASE_PREPARE 0xF3
2007 #define WIN_SECURITY_ERASE_UNIT 0xF4
2008 #define WIN_SECURITY_FREEZE_LOCK 0xF5
2009 #define WIN_SECURITY_DISABLE 0xF6
2010 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
2011 #define WIN_SET_MAX 0xF9
2012 #define DISABLE_SEAGATE 0xFB
2014 /* set to 1 set disable mult support */
2015 #define MAX_MULT_SECTORS 8
2019 typedef void EndTransferFunc(struct IDEState
*);
2021 typedef struct IDEState
{
2023 int cylinders
, heads
, sectors
;
2030 uint16_t nsector
; /* 0 is 256 to ease computations */
2036 /* 0x3f6 command, only meaningful for drive 0 */
2038 /* depends on bit 4 in select, only meaningful for drive 0 */
2039 struct IDEState
*cur_drive
;
2040 BlockDriverState
*bs
;
2041 int req_nb_sectors
; /* number of sectors per interrupt */
2042 EndTransferFunc
*end_transfer_func
;
2045 uint8_t io_buffer
[MAX_MULT_SECTORS
*512 + 4];
2048 IDEState ide_state
[MAX_DISKS
];
2050 static void padstr(char *str
, const char *src
, int len
)
2053 for(i
= 0; i
< len
; i
++) {
2058 *(char *)((long)str
^ 1) = v
;
2063 static void ide_identify(IDEState
*s
)
2066 unsigned int oldsize
;
2068 memset(s
->io_buffer
, 0, 512);
2069 p
= (uint16_t *)s
->io_buffer
;
2070 stw_raw(p
+ 0, 0x0040);
2071 stw_raw(p
+ 1, s
->cylinders
);
2072 stw_raw(p
+ 3, s
->heads
);
2073 stw_raw(p
+ 4, 512 * s
->sectors
); /* sectors */
2074 stw_raw(p
+ 5, 512); /* sector size */
2075 stw_raw(p
+ 6, s
->sectors
);
2076 stw_raw(p
+ 20, 3); /* buffer type */
2077 stw_raw(p
+ 21, 512); /* cache size in sectors */
2078 stw_raw(p
+ 22, 4); /* ecc bytes */
2079 padstr((uint8_t *)(p
+ 27), "QEMU HARDDISK", 40);
2080 #if MAX_MULT_SECTORS > 1
2081 stw_raw(p
+ 47, MAX_MULT_SECTORS
);
2083 stw_raw(p
+ 48, 1); /* dword I/O */
2084 stw_raw(p
+ 49, 1 << 9); /* LBA supported, no DMA */
2085 stw_raw(p
+ 51, 0x200); /* PIO transfer cycle */
2086 stw_raw(p
+ 52, 0x200); /* DMA transfer cycle */
2087 stw_raw(p
+ 54, s
->cylinders
);
2088 stw_raw(p
+ 55, s
->heads
);
2089 stw_raw(p
+ 56, s
->sectors
);
2090 oldsize
= s
->cylinders
* s
->heads
* s
->sectors
;
2091 stw_raw(p
+ 57, oldsize
);
2092 stw_raw(p
+ 58, oldsize
>> 16);
2093 if (s
->mult_sectors
)
2094 stw_raw(p
+ 59, 0x100 | s
->mult_sectors
);
2095 stw_raw(p
+ 60, s
->nb_sectors
);
2096 stw_raw(p
+ 61, s
->nb_sectors
>> 16);
2097 stw_raw(p
+ 80, (1 << 1) | (1 << 2));
2098 stw_raw(p
+ 82, (1 << 14));
2099 stw_raw(p
+ 83, (1 << 14));
2100 stw_raw(p
+ 84, (1 << 14));
2101 stw_raw(p
+ 85, (1 << 14));
2103 stw_raw(p
+ 87, (1 << 14));
2106 static inline void ide_abort_command(IDEState
*s
)
2108 s
->status
= READY_STAT
| ERR_STAT
;
2109 s
->error
= ABRT_ERR
;
2112 static inline void ide_set_irq(IDEState
*s
)
2114 if (!(ide_state
[0].cmd
& IDE_CMD_DISABLE_IRQ
)) {
2115 pic_set_irq(s
->irq
, 1);
2119 /* prepare data transfer and tell what to do after */
2120 static void ide_transfer_start(IDEState
*s
, int size
,
2121 EndTransferFunc
*end_transfer_func
)
2123 s
->end_transfer_func
= end_transfer_func
;
2124 s
->data_ptr
= s
->io_buffer
;
2125 s
->data_end
= s
->io_buffer
+ size
;
2126 s
->status
|= DRQ_STAT
;
2129 static void ide_transfer_stop(IDEState
*s
)
2131 s
->end_transfer_func
= ide_transfer_stop
;
2132 s
->data_ptr
= s
->io_buffer
;
2133 s
->data_end
= s
->io_buffer
;
2134 s
->status
&= ~DRQ_STAT
;
2137 static int64_t ide_get_sector(IDEState
*s
)
2140 if (s
->select
& 0x40) {
2142 sector_num
= ((s
->select
& 0x0f) << 24) | (s
->hcyl
<< 16) |
2143 (s
->lcyl
<< 8) | s
->sector
;
2145 sector_num
= ((s
->hcyl
<< 8) | s
->lcyl
) * s
->heads
* s
->sectors
+
2146 (s
->select
& 0x0f) * s
->sectors
+
2152 static void ide_set_sector(IDEState
*s
, int64_t sector_num
)
2154 unsigned int cyl
, r
;
2155 if (s
->select
& 0x40) {
2156 s
->select
= (s
->select
& 0xf0) | (sector_num
>> 24);
2157 s
->hcyl
= (sector_num
>> 16);
2158 s
->lcyl
= (sector_num
>> 8);
2159 s
->sector
= (sector_num
);
2161 cyl
= sector_num
/ (s
->heads
* s
->sectors
);
2162 r
= sector_num
% (s
->heads
* s
->sectors
);
2165 s
->select
= (s
->select
& 0xf0) | (r
/ s
->sectors
);
2166 s
->sector
= (r
% s
->sectors
) + 1;
2170 static void ide_sector_read(IDEState
*s
)
2175 s
->status
= READY_STAT
| SEEK_STAT
;
2176 sector_num
= ide_get_sector(s
);
2179 /* no more sector to read from disk */
2180 ide_transfer_stop(s
);
2182 #if defined(DEBUG_IDE)
2183 printf("read sector=%Ld\n", sector_num
);
2185 if (n
> s
->req_nb_sectors
)
2186 n
= s
->req_nb_sectors
;
2187 ret
= bdrv_read(s
->bs
, sector_num
, s
->io_buffer
, n
);
2188 ide_transfer_start(s
, 512 * n
, ide_sector_read
);
2190 ide_set_sector(s
, sector_num
+ n
);
2195 static void ide_sector_write(IDEState
*s
)
2200 s
->status
= READY_STAT
| SEEK_STAT
;
2201 sector_num
= ide_get_sector(s
);
2202 #if defined(DEBUG_IDE)
2203 printf("write sector=%Ld\n", sector_num
);
2206 if (n
> s
->req_nb_sectors
)
2207 n
= s
->req_nb_sectors
;
2208 ret
= bdrv_write(s
->bs
, sector_num
, s
->io_buffer
, n
);
2210 if (s
->nsector
== 0) {
2211 /* no more sector to write */
2212 ide_transfer_stop(s
);
2215 if (n1
> s
->req_nb_sectors
)
2216 n1
= s
->req_nb_sectors
;
2217 ide_transfer_start(s
, 512 * n1
, ide_sector_write
);
2219 ide_set_sector(s
, sector_num
+ n
);
2223 void ide_ioport_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2225 IDEState
*s
= ide_state
[0].cur_drive
;
2230 printf("IDE: write addr=0x%x val=0x%02x\n", addr
, val
);
2254 unit
= (val
>> 4) & 1;
2255 s
= &ide_state
[unit
];
2256 ide_state
[0].cur_drive
= s
;
2262 #if defined(DEBUG_IDE)
2263 printf("ide: CMD=%02x\n", val
);
2270 s
->status
= READY_STAT
;
2271 ide_transfer_start(s
, 512, ide_transfer_stop
);
2273 ide_abort_command(s
);
2279 s
->status
= READY_STAT
;
2283 if (s
->nsector
> MAX_MULT_SECTORS
||
2285 (s
->nsector
& (s
->nsector
- 1)) != 0) {
2286 ide_abort_command(s
);
2288 s
->mult_sectors
= s
->nsector
;
2289 s
->status
= READY_STAT
;
2295 s
->req_nb_sectors
= 1;
2299 case WIN_WRITE_ONCE
:
2300 s
->status
= SEEK_STAT
;
2301 s
->req_nb_sectors
= 1;
2302 ide_transfer_start(s
, 512, ide_sector_write
);
2305 if (!s
->mult_sectors
)
2307 s
->req_nb_sectors
= s
->mult_sectors
;
2311 if (!s
->mult_sectors
)
2313 s
->status
= SEEK_STAT
;
2314 s
->req_nb_sectors
= s
->mult_sectors
;
2316 if (n
> s
->req_nb_sectors
)
2317 n
= s
->req_nb_sectors
;
2318 ide_transfer_start(s
, 512 * n
, ide_sector_write
);
2320 case WIN_READ_NATIVE_MAX
:
2321 ide_set_sector(s
, s
->nb_sectors
- 1);
2322 s
->status
= READY_STAT
;
2327 ide_abort_command(s
);
2334 uint32_t ide_ioport_read(CPUX86State
*env
, uint32_t addr
)
2336 IDEState
*s
= ide_state
[0].cur_drive
;
2348 ret
= s
->nsector
& 0xff;
2365 pic_set_irq(s
->irq
, 0);
2369 printf("ide: read addr=0x%x val=%02x\n", addr
, ret
);
2374 uint32_t ide_status_read(CPUX86State
*env
, uint32_t addr
)
2376 IDEState
*s
= ide_state
[0].cur_drive
;
2380 printf("ide: read status val=%02x\n", ret
);
2385 void ide_cmd_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2391 printf("ide: write control val=%02x\n", val
);
2393 /* common for both drives */
2394 if (!(ide_state
[0].cmd
& IDE_CMD_RESET
) &&
2395 (val
& IDE_CMD_RESET
)) {
2396 /* reset low to high */
2397 for(i
= 0;i
< 2; i
++) {
2399 s
->status
= BUSY_STAT
| SEEK_STAT
;
2402 } else if ((ide_state
[0].cmd
& IDE_CMD_RESET
) &&
2403 !(val
& IDE_CMD_RESET
)) {
2405 for(i
= 0;i
< 2; i
++) {
2407 s
->status
= READY_STAT
;
2408 /* set hard disk drive ID */
2409 s
->select
&= 0xf0; /* clear head */
2412 if (s
->nb_sectors
== 0) {
2413 /* no disk present */
2423 ide_state
[0].cmd
= val
;
2426 void ide_data_writew(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2428 IDEState
*s
= ide_state
[0].cur_drive
;
2432 *(uint16_t *)p
= tswap16(val
);
2435 if (p
>= s
->data_end
)
2436 s
->end_transfer_func(s
);
2439 uint32_t ide_data_readw(CPUX86State
*env
, uint32_t addr
)
2441 IDEState
*s
= ide_state
[0].cur_drive
;
2446 ret
= tswap16(*(uint16_t *)p
);
2449 if (p
>= s
->data_end
)
2450 s
->end_transfer_func(s
);
2454 void ide_data_writel(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2456 IDEState
*s
= ide_state
[0].cur_drive
;
2460 *(uint32_t *)p
= tswap32(val
);
2463 if (p
>= s
->data_end
)
2464 s
->end_transfer_func(s
);
2467 uint32_t ide_data_readl(CPUX86State
*env
, uint32_t addr
)
2469 IDEState
*s
= ide_state
[0].cur_drive
;
2474 ret
= tswap32(*(uint32_t *)p
);
2477 if (p
>= s
->data_end
)
2478 s
->end_transfer_func(s
);
2482 void ide_reset(IDEState
*s
)
2484 s
->mult_sectors
= MAX_MULT_SECTORS
;
2485 s
->status
= READY_STAT
;
2491 uint8_t boot_ind
; /* 0x80 - active */
2492 uint8_t head
; /* starting head */
2493 uint8_t sector
; /* starting sector */
2494 uint8_t cyl
; /* starting cylinder */
2495 uint8_t sys_ind
; /* What partition type */
2496 uint8_t end_head
; /* end head */
2497 uint8_t end_sector
; /* end sector */
2498 uint8_t end_cyl
; /* end cylinder */
2499 uint32_t start_sect
; /* starting sector counting from 0 */
2500 uint32_t nr_sects
; /* nr of sectors in partition */
2501 } __attribute__((packed
));
2503 /* try to guess the IDE geometry from the MSDOS partition table */
2504 void ide_guess_geometry(IDEState
*s
)
2508 struct partition
*p
;
2511 if (s
->cylinders
!= 0)
2513 ret
= bdrv_read(s
->bs
, 0, buf
, 1);
2516 /* test msdos magic */
2517 if (buf
[510] != 0x55 || buf
[511] != 0xaa)
2519 for(i
= 0; i
< 4; i
++) {
2520 p
= ((struct partition
*)(buf
+ 0x1be)) + i
;
2521 nr_sects
= tswap32(p
->nr_sects
);
2522 if (nr_sects
&& p
->end_head
) {
2523 /* We make the assumption that the partition terminates on
2524 a cylinder boundary */
2525 s
->heads
= p
->end_head
+ 1;
2526 s
->sectors
= p
->end_sector
& 63;
2527 s
->cylinders
= s
->nb_sectors
/ (s
->heads
* s
->sectors
);
2529 printf("guessed partition: CHS=%d %d %d\n",
2530 s
->cylinders
, s
->heads
, s
->sectors
);
2542 for(i
= 0; i
< MAX_DISKS
; i
++) {
2544 s
->bs
= bs_table
[i
];
2546 bdrv_get_geometry(s
->bs
, &nb_sectors
);
2547 s
->nb_sectors
= nb_sectors
;
2548 ide_guess_geometry(s
);
2549 if (s
->cylinders
== 0) {
2550 /* if no geometry, use a LBA compatible one */
2551 cylinders
= nb_sectors
/ (16 * 63);
2552 if (cylinders
> 16383)
2554 else if (cylinders
< 2)
2556 s
->cylinders
= cylinders
;
2564 register_ioport_write(0x1f0, 8, ide_ioport_write
, 1);
2565 register_ioport_read(0x1f0, 8, ide_ioport_read
, 1);
2566 register_ioport_read(0x3f6, 1, ide_status_read
, 1);
2567 register_ioport_write(0x3f6, 1, ide_cmd_write
, 1);
2570 register_ioport_write(0x1f0, 2, ide_data_writew
, 2);
2571 register_ioport_read(0x1f0, 2, ide_data_readw
, 2);
2572 register_ioport_write(0x1f0, 4, ide_data_writel
, 4);
2573 register_ioport_read(0x1f0, 4, ide_data_readl
, 4);
2576 /***********************************************************/
2577 /* keyboard emulation */
2579 /* Keyboard Controller Commands */
2580 #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
2581 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
2582 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
2583 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
2584 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
2585 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
2586 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
2587 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
2588 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
2589 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
2590 #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
2591 #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
2592 #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
2593 #define KBD_CCMD_WRITE_OBUF 0xD2
2594 #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
2595 initiated by the auxiliary device */
2596 #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
2597 #define KBD_CCMD_ENABLE_A20 0xDD
2598 #define KBD_CCMD_DISABLE_A20 0xDF
2599 #define KBD_CCMD_RESET 0xFE
2601 /* Keyboard Commands */
2602 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
2603 #define KBD_CMD_ECHO 0xEE
2604 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
2605 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
2606 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
2607 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
2608 #define KBD_CMD_RESET 0xFF /* Reset */
2610 /* Keyboard Replies */
2611 #define KBD_REPLY_POR 0xAA /* Power on reset */
2612 #define KBD_REPLY_ACK 0xFA /* Command ACK */
2613 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
2615 /* Status Register Bits */
2616 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
2617 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
2618 #define KBD_STAT_SELFTEST 0x04 /* Self test successful */
2619 #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
2620 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
2621 #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
2622 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
2623 #define KBD_STAT_PERR 0x80 /* Parity error */
2625 /* Controller Mode Register Bits */
2626 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
2627 #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
2628 #define KBD_MODE_SYS 0x04 /* The system flag (?) */
2629 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
2630 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
2631 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
2632 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
2633 #define KBD_MODE_RFU 0x80
2635 /* Mouse Commands */
2636 #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
2637 #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
2638 #define AUX_SET_RES 0xE8 /* Set resolution */
2639 #define AUX_GET_SCALE 0xE9 /* Get scaling factor */
2640 #define AUX_SET_STREAM 0xEA /* Set stream mode */
2641 #define AUX_POLL 0xEB /* Poll */
2642 #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
2643 #define AUX_SET_WRAP 0xEE /* Set wrap mode */
2644 #define AUX_SET_REMOTE 0xF0 /* Set remote mode */
2645 #define AUX_GET_TYPE 0xF2 /* Get type */
2646 #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
2647 #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
2648 #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
2649 #define AUX_SET_DEFAULT 0xF6
2650 #define AUX_RESET 0xFF /* Reset aux device */
2651 #define AUX_ACK 0xFA /* Command byte ACK. */
2653 #define MOUSE_STATUS_REMOTE 0x40
2654 #define MOUSE_STATUS_ENABLED 0x20
2655 #define MOUSE_STATUS_SCALE21 0x10
2657 #define KBD_QUEUE_SIZE 256
2660 uint8_t data
[KBD_QUEUE_SIZE
];
2661 int rptr
, wptr
, count
;
2664 typedef struct KBDState
{
2666 uint8_t write_cmd
; /* if non zero, write data to port 60 is expected */
2669 /* keyboard state */
2673 int mouse_write_cmd
;
2674 uint8_t mouse_status
;
2675 uint8_t mouse_resolution
;
2676 uint8_t mouse_sample_rate
;
2678 uint8_t mouse_type
; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
2679 uint8_t mouse_detect_state
;
2680 int mouse_dx
; /* current values, needed for 'poll' mode */
2683 uint8_t mouse_buttons
;
2687 int reset_requested
;
2690 /* update irq and KBD_STAT_[MOUSE_]OBF */
2691 static void kbd_update_irq(KBDState
*s
)
2693 int irq12_level
, irq1_level
;
2697 s
->status
&= ~(KBD_STAT_OBF
| KBD_STAT_MOUSE_OBF
);
2698 if (s
->queues
[0].count
!= 0 ||
2699 s
->queues
[1].count
!= 0) {
2700 s
->status
|= KBD_STAT_OBF
;
2701 if (s
->queues
[1].count
!= 0) {
2702 s
->status
|= KBD_STAT_MOUSE_OBF
;
2703 if (s
->mode
& KBD_MODE_MOUSE_INT
)
2706 if (s
->mode
& KBD_MODE_KBD_INT
)
2710 pic_set_irq(1, irq1_level
);
2711 pic_set_irq(12, irq12_level
);
2714 static void kbd_queue(KBDState
*s
, int b
, int aux
)
2716 KBDQueue
*q
= &kbd_state
.queues
[aux
];
2718 #if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
2720 printf("mouse event: 0x%02x\n", b
);
2723 printf("kbd event: 0x%02x\n", b
);
2726 if (q
->count
>= KBD_QUEUE_SIZE
)
2728 q
->data
[q
->wptr
] = b
;
2729 if (++q
->wptr
== KBD_QUEUE_SIZE
)
2735 void kbd_put_keycode(int keycode
)
2737 KBDState
*s
= &kbd_state
;
2738 kbd_queue(s
, keycode
, 0);
2741 uint32_t kbd_read_status(CPUX86State
*env
, uint32_t addr
)
2743 KBDState
*s
= &kbd_state
;
2746 #if defined(DEBUG_KBD) && 0
2747 printf("kbd: read status=0x%02x\n", val
);
2752 void kbd_write_command(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
2754 KBDState
*s
= &kbd_state
;
2757 printf("kbd: write cmd=0x%02x\n", val
);
2760 case KBD_CCMD_READ_MODE
:
2761 kbd_queue(s
, s
->mode
, 0);
2763 case KBD_CCMD_WRITE_MODE
:
2764 case KBD_CCMD_WRITE_OBUF
:
2765 case KBD_CCMD_WRITE_AUX_OBUF
:
2766 case KBD_CCMD_WRITE_MOUSE
:
2767 case KBD_CCMD_WRITE_OUTPORT
:
2770 case KBD_CCMD_MOUSE_DISABLE
:
2771 s
->mode
|= KBD_MODE_DISABLE_MOUSE
;
2773 case KBD_CCMD_MOUSE_ENABLE
:
2774 s
->mode
&= ~KBD_MODE_DISABLE_MOUSE
;
2776 case KBD_CCMD_TEST_MOUSE
:
2777 kbd_queue(s
, 0x00, 0);
2779 case KBD_CCMD_SELF_TEST
:
2780 s
->status
|= KBD_STAT_SELFTEST
;
2781 kbd_queue(s
, 0x55, 0);
2783 case KBD_CCMD_KBD_TEST
:
2784 kbd_queue(s
, 0x00, 0);
2786 case KBD_CCMD_KBD_DISABLE
:
2787 s
->mode
|= KBD_MODE_DISABLE_KBD
;
2789 case KBD_CCMD_KBD_ENABLE
:
2790 s
->mode
&= ~KBD_MODE_DISABLE_KBD
;
2792 case KBD_CCMD_READ_INPORT
:
2793 kbd_queue(s
, 0x00, 0);
2795 case KBD_CCMD_READ_OUTPORT
:
2796 /* XXX: check that */
2797 val
= 0x01 | (a20_enabled
<< 1);
2798 if (s
->status
& KBD_STAT_OBF
)
2800 if (s
->status
& KBD_STAT_MOUSE_OBF
)
2802 kbd_queue(s
, val
, 0);
2804 case KBD_CCMD_ENABLE_A20
:
2807 case KBD_CCMD_DISABLE_A20
:
2810 case KBD_CCMD_RESET
:
2811 reset_requested
= 1;
2812 cpu_x86_interrupt(global_env
, CPU_INTERRUPT_EXIT
);
2815 fprintf(stderr
, "vl: unsupported keyboard cmd=0x%02x\n", val
);
2820 uint32_t kbd_read_data(CPUX86State
*env
, uint32_t addr
)
2822 KBDState
*s
= &kbd_state
;
2826 q
= &s
->queues
[0]; /* first check KBD data */
2828 q
= &s
->queues
[1]; /* then check AUX data */
2829 if (q
->count
== 0) {
2830 /* XXX: return something else ? */
2833 val
= q
->data
[q
->rptr
];
2834 if (++q
->rptr
== KBD_QUEUE_SIZE
)
2837 /* reading deasserts IRQ */
2838 if (q
== &s
->queues
[0])
2843 /* reassert IRQs if data left */
2846 printf("kbd: read data=0x%02x\n", val
);
2851 static void kbd_reset_keyboard(KBDState
*s
)
2853 s
->scan_enabled
= 1;
2856 static void kbd_write_keyboard(KBDState
*s
, int val
)
2858 switch(s
->kbd_write_cmd
) {
2863 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2866 kbd_queue(s
, KBD_REPLY_RESEND
, 0);
2869 kbd_queue(s
, KBD_CMD_ECHO
, 0);
2871 case KBD_CMD_ENABLE
:
2872 s
->scan_enabled
= 1;
2873 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2875 case KBD_CMD_SET_LEDS
:
2876 case KBD_CMD_SET_RATE
:
2877 s
->kbd_write_cmd
= val
;
2879 case KBD_CMD_RESET_DISABLE
:
2880 kbd_reset_keyboard(s
);
2881 s
->scan_enabled
= 0;
2882 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2884 case KBD_CMD_RESET_ENABLE
:
2885 kbd_reset_keyboard(s
);
2886 s
->scan_enabled
= 1;
2887 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2890 kbd_reset_keyboard(s
);
2891 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2892 kbd_queue(s
, KBD_REPLY_POR
, 0);
2895 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2899 case KBD_CMD_SET_LEDS
:
2900 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2901 s
->kbd_write_cmd
= -1;
2903 case KBD_CMD_SET_RATE
:
2904 kbd_queue(s
, KBD_REPLY_ACK
, 0);
2905 s
->kbd_write_cmd
= -1;
2910 static void kbd_mouse_send_packet(KBDState
*s
)
2918 /* XXX: increase range to 8 bits ? */
2921 else if (dx1
< -127)
2925 else if (dy1
< -127)
2927 b
= 0x08 | ((dx1
< 0) << 4) | ((dy1
< 0) << 5) | (s
->mouse_buttons
& 0x07);
2929 kbd_queue(s
, dx1
& 0xff, 1);
2930 kbd_queue(s
, dy1
& 0xff, 1);
2931 /* extra byte for IMPS/2 or IMEX */
2932 switch(s
->mouse_type
) {
2938 else if (dz1
< -127)
2940 kbd_queue(s
, dz1
& 0xff, 1);
2947 b
= (dz1
& 0x0f) | ((s
->mouse_buttons
& 0x18) << 1);
2958 void kbd_mouse_event(int dx
, int dy
, int dz
, int buttons_state
)
2960 KBDState
*s
= &kbd_state
;
2962 /* check if deltas are recorded when disabled */
2963 if (!(s
->mouse_status
& MOUSE_STATUS_ENABLED
))
2969 s
->mouse_buttons
= buttons_state
;
2971 if (!(s
->mouse_status
& MOUSE_STATUS_REMOTE
) &&
2972 (s
->queues
[1].count
< (KBD_QUEUE_SIZE
- 16))) {
2974 /* if not remote, send event. Multiple events are sent if
2976 kbd_mouse_send_packet(s
);
2977 if (s
->mouse_dx
== 0 && s
->mouse_dy
== 0 && s
->mouse_dz
== 0)
2983 static void kbd_write_mouse(KBDState
*s
, int val
)
2986 printf("kbd: write mouse 0x%02x\n", val
);
2988 switch(s
->mouse_write_cmd
) {
2992 if (s
->mouse_wrap
) {
2993 if (val
== AUX_RESET_WRAP
) {
2995 kbd_queue(s
, AUX_ACK
, 1);
2997 } else if (val
!= AUX_RESET
) {
2998 kbd_queue(s
, val
, 1);
3003 case AUX_SET_SCALE11
:
3004 s
->mouse_status
&= ~MOUSE_STATUS_SCALE21
;
3005 kbd_queue(s
, AUX_ACK
, 1);
3007 case AUX_SET_SCALE21
:
3008 s
->mouse_status
|= MOUSE_STATUS_SCALE21
;
3009 kbd_queue(s
, AUX_ACK
, 1);
3011 case AUX_SET_STREAM
:
3012 s
->mouse_status
&= ~MOUSE_STATUS_REMOTE
;
3013 kbd_queue(s
, AUX_ACK
, 1);
3017 kbd_queue(s
, AUX_ACK
, 1);
3019 case AUX_SET_REMOTE
:
3020 s
->mouse_status
|= MOUSE_STATUS_REMOTE
;
3021 kbd_queue(s
, AUX_ACK
, 1);
3024 kbd_queue(s
, AUX_ACK
, 1);
3025 kbd_queue(s
, s
->mouse_type
, 1);
3028 case AUX_SET_SAMPLE
:
3029 s
->mouse_write_cmd
= val
;
3030 kbd_queue(s
, AUX_ACK
, 1);
3033 kbd_queue(s
, AUX_ACK
, 1);
3034 kbd_queue(s
, s
->mouse_status
, 1);
3035 kbd_queue(s
, s
->mouse_resolution
, 1);
3036 kbd_queue(s
, s
->mouse_sample_rate
, 1);
3039 kbd_queue(s
, AUX_ACK
, 1);
3040 kbd_mouse_send_packet(s
);
3042 case AUX_ENABLE_DEV
:
3043 s
->mouse_status
|= MOUSE_STATUS_ENABLED
;
3044 kbd_queue(s
, AUX_ACK
, 1);
3046 case AUX_DISABLE_DEV
:
3047 s
->mouse_status
&= ~MOUSE_STATUS_ENABLED
;
3048 kbd_queue(s
, AUX_ACK
, 1);
3050 case AUX_SET_DEFAULT
:
3051 s
->mouse_sample_rate
= 100;
3052 s
->mouse_resolution
= 2;
3053 s
->mouse_status
= 0;
3054 kbd_queue(s
, AUX_ACK
, 1);
3057 s
->mouse_sample_rate
= 100;
3058 s
->mouse_resolution
= 2;
3059 s
->mouse_status
= 0;
3060 kbd_queue(s
, AUX_ACK
, 1);
3061 kbd_queue(s
, 0xaa, 1);
3062 kbd_queue(s
, s
->mouse_type
, 1);
3068 case AUX_SET_SAMPLE
:
3069 s
->mouse_sample_rate
= val
;
3071 /* detect IMPS/2 or IMEX */
3072 switch(s
->mouse_detect_state
) {
3076 s
->mouse_detect_state
= 1;
3080 s
->mouse_detect_state
= 2;
3081 else if (val
== 200)
3082 s
->mouse_detect_state
= 3;
3084 s
->mouse_detect_state
= 0;
3088 s
->mouse_type
= 3; /* IMPS/2 */
3089 s
->mouse_detect_state
= 0;
3093 s
->mouse_type
= 4; /* IMEX */
3094 s
->mouse_detect_state
= 0;
3098 kbd_queue(s
, AUX_ACK
, 1);
3099 s
->mouse_write_cmd
= -1;
3102 s
->mouse_resolution
= val
;
3103 kbd_queue(s
, AUX_ACK
, 1);
3104 s
->mouse_write_cmd
= -1;
3109 void kbd_write_data(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
3111 KBDState
*s
= &kbd_state
;
3114 printf("kbd: write data=0x%02x\n", val
);
3117 switch(s
->write_cmd
) {
3119 kbd_write_keyboard(s
, val
);
3121 case KBD_CCMD_WRITE_MODE
:
3125 case KBD_CCMD_WRITE_OBUF
:
3126 kbd_queue(s
, val
, 0);
3128 case KBD_CCMD_WRITE_AUX_OBUF
:
3129 kbd_queue(s
, val
, 1);
3131 case KBD_CCMD_WRITE_OUTPORT
:
3132 a20_enabled
= (val
>> 1) & 1;
3134 reset_requested
= 1;
3135 cpu_x86_interrupt(global_env
, CPU_INTERRUPT_EXIT
);
3138 case KBD_CCMD_WRITE_MOUSE
:
3139 kbd_write_mouse(s
, val
);
3147 void kbd_reset(KBDState
*s
)
3152 s
->kbd_write_cmd
= -1;
3153 s
->mouse_write_cmd
= -1;
3154 s
->mode
= KBD_MODE_KBD_INT
| KBD_MODE_MOUSE_INT
;
3155 s
->status
= KBD_STAT_CMD
| KBD_STAT_UNLOCKED
;
3156 for(i
= 0; i
< 2; i
++) {
3166 kbd_reset(&kbd_state
);
3167 register_ioport_read(0x60, 1, kbd_read_data
, 1);
3168 register_ioport_write(0x60, 1, kbd_write_data
, 1);
3169 register_ioport_read(0x64, 1, kbd_read_status
, 1);
3170 register_ioport_write(0x64, 1, kbd_write_command
, 1);
3173 /***********************************************************/
3174 /* Bochs BIOS debug ports */
3176 void bochs_bios_write(CPUX86State
*env
, uint32_t addr
, uint32_t val
)
3179 /* Bochs BIOS messages */
3182 fprintf(stderr
, "BIOS panic at rombios.c, line %d\n", val
);
3187 fprintf(stderr
, "%c", val
);
3191 /* LGPL'ed VGA BIOS messages */
3194 fprintf(stderr
, "VGA BIOS panic, line %d\n", val
);
3199 fprintf(stderr
, "%c", val
);
3205 void bochs_bios_init(void)
3207 register_ioport_write(0x400, 1, bochs_bios_write
, 2);
3208 register_ioport_write(0x401, 1, bochs_bios_write
, 2);
3209 register_ioport_write(0x402, 1, bochs_bios_write
, 1);
3210 register_ioport_write(0x403, 1, bochs_bios_write
, 1);
3212 register_ioport_write(0x501, 1, bochs_bios_write
, 2);
3213 register_ioport_write(0x502, 1, bochs_bios_write
, 2);
3214 register_ioport_write(0x500, 1, bochs_bios_write
, 1);
3215 register_ioport_write(0x503, 1, bochs_bios_write
, 1);
3218 /***********************************************************/
3221 /* init terminal so that we can grab keys */
3222 static struct termios oldtty
;
3224 static void term_exit(void)
3226 tcsetattr (0, TCSANOW
, &oldtty
);
3229 static void term_init(void)
3233 tcgetattr (0, &tty
);
3236 tty
.c_iflag
&= ~(IGNBRK
|BRKINT
|PARMRK
|ISTRIP
3237 |INLCR
|IGNCR
|ICRNL
|IXON
);
3238 tty
.c_oflag
|= OPOST
;
3239 tty
.c_lflag
&= ~(ECHO
|ECHONL
|ICANON
|IEXTEN
);
3240 /* if graphical mode, we allow Ctrl-C handling */
3242 tty
.c_lflag
&= ~ISIG
;
3243 tty
.c_cflag
&= ~(CSIZE
|PARENB
);
3246 tty
.c_cc
[VTIME
] = 0;
3248 tcsetattr (0, TCSANOW
, &tty
);
3252 fcntl(0, F_SETFL
, O_NONBLOCK
);
3255 static void dumb_update(DisplayState
*ds
, int x
, int y
, int w
, int h
)
3259 static void dumb_resize(DisplayState
*ds
, int w
, int h
)
3263 static void dumb_refresh(DisplayState
*ds
)
3265 vga_update_display();
3268 void dumb_display_init(DisplayState
*ds
)
3273 ds
->dpy_update
= dumb_update
;
3274 ds
->dpy_resize
= dumb_resize
;
3275 ds
->dpy_refresh
= dumb_refresh
;
3278 #if !defined(CONFIG_SOFTMMU)
3279 /***********************************************************/
3280 /* cpu signal handler */
3281 static void host_segv_handler(int host_signum
, siginfo_t
*info
,
3284 if (cpu_signal_handler(host_signum
, info
, puc
))
3291 static int timer_irq_pending
;
3292 static int timer_irq_count
;
3294 static int timer_ms
;
3295 static int gui_refresh_pending
, gui_refresh_count
;
3297 static void host_alarm_handler(int host_signum
, siginfo_t
*info
,
3300 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
3301 some drift between cpu_get_ticks() and the interrupt time. So
3302 we queue some interrupts to avoid missing some */
3303 timer_irq_count
+= pit_get_out_edges(&pit_channels
[0]);
3304 if (timer_irq_count
) {
3305 if (timer_irq_count
> 2)
3306 timer_irq_count
= 2;
3308 timer_irq_pending
= 1;
3310 gui_refresh_count
+= timer_ms
;
3311 if (gui_refresh_count
>= GUI_REFRESH_INTERVAL
) {
3312 gui_refresh_count
= 0;
3313 gui_refresh_pending
= 1;
3316 if (gui_refresh_pending
|| timer_irq_pending
) {
3317 /* just exit from the cpu to have a chance to handle timers */
3318 cpu_x86_interrupt(global_env
, CPU_INTERRUPT_EXIT
);
3322 unsigned long mmap_addr
= PHYS_RAM_BASE
;
3324 void *get_mmap_addr(unsigned long size
)
3328 mmap_addr
+= ((size
+ 4095) & ~4095) + 4096;
3329 return (void *)addr
;
3332 /* main execution loop */
3334 CPUState
*cpu_gdbstub_get_env(void *opaque
)
3339 int main_loop(void *opaque
)
3341 struct pollfd ufds
[3], *pf
, *serial_ufd
, *net_ufd
, *gdb_ufd
;
3342 int ret
, n
, timeout
, serial_ok
;
3344 CPUState
*env
= global_env
;
3347 /* initialize terminal only there so that the user has a
3348 chance to stop QEMU with Ctrl-C before the gdb connection
3357 ret
= cpu_x86_exec(env
);
3358 if (reset_requested
) {
3359 ret
= EXCP_INTERRUPT
;
3362 if (ret
== EXCP_DEBUG
) {
3366 /* if hlt instruction, we wait until the next IRQ */
3367 if (ret
== EXCP_HLT
)
3371 /* poll any events */
3374 if (serial_ok
&& !(serial_ports
[0].lsr
& UART_LSR_DR
)) {
3377 pf
->events
= POLLIN
;
3381 if (net_fd
> 0 && ne2000_can_receive(&ne2000_state
)) {
3384 pf
->events
= POLLIN
;
3388 if (gdbstub_fd
> 0) {
3390 pf
->fd
= gdbstub_fd
;
3391 pf
->events
= POLLIN
;
3395 ret
= poll(ufds
, pf
- ufds
, timeout
);
3397 if (serial_ufd
&& (serial_ufd
->revents
& POLLIN
)) {
3398 n
= read(0, &ch
, 1);
3400 serial_received_byte(&serial_ports
[0], ch
);
3402 /* Closed, stop polling. */
3406 if (net_ufd
&& (net_ufd
->revents
& POLLIN
)) {
3407 uint8_t buf
[MAX_ETH_FRAME_SIZE
];
3409 n
= read(net_fd
, buf
, MAX_ETH_FRAME_SIZE
);
3412 memset(buf
+ n
, 0, 60 - n
);
3415 ne2000_receive(&ne2000_state
, buf
, n
);
3418 if (gdb_ufd
&& (gdb_ufd
->revents
& POLLIN
)) {
3420 /* stop emulation if requested by gdb */
3421 n
= read(gdbstub_fd
, buf
, 1);
3423 ret
= EXCP_INTERRUPT
;
3430 if (timer_irq_pending
) {
3433 timer_irq_pending
= 0;
3437 if (gui_refresh_pending
) {
3438 display_state
.dpy_refresh(&display_state
);
3439 gui_refresh_pending
= 0;
3442 cpu_disable_ticks();
3448 printf("QEMU PC emulator version " QEMU_VERSION
", Copyright (c) 2003 Fabrice Bellard\n"
3449 "usage: %s [options] [disk_image]\n"
3451 "'disk_image' is a raw hard image image for IDE hard disk 0\n"
3453 "Standard options:\n"
3454 "-hda file use 'file' as IDE hard disk 0 image\n"
3455 "-hdb file use 'file' as IDE hard disk 1 image\n"
3456 "-snapshot write to temporary files instead of disk image files\n"
3457 "-m megs set virtual RAM size to megs MB\n"
3458 "-n script set network init script [default=%s]\n"
3459 "-tun-fd fd this fd talks to tap/tun, use it.\n"
3460 "-nographic disable graphical output\n"
3462 "Linux boot specific (does not require PC BIOS):\n"
3463 "-kernel bzImage use 'bzImage' as kernel image\n"
3464 "-append cmdline use 'cmdline' as kernel command line\n"
3465 "-initrd file use 'file' as initial ram disk\n"
3467 "Debug/Expert options:\n"
3468 "-s wait gdb connection to port %d\n"
3469 "-p port change gdb connection port\n"
3470 "-d output log in /tmp/vl.log\n"
3471 "-hdachs c,h,s force hard disk 0 geometry (usually qemu can guess it)\n"
3472 "-L path set the directory for the BIOS and VGA BIOS\n"
3474 "During emulation, use C-a h to get terminal commands:\n",
3475 #ifdef CONFIG_SOFTMMU
3480 DEFAULT_NETWORK_SCRIPT
,
3481 DEFAULT_GDBSTUB_PORT
);
3483 #ifndef CONFIG_SOFTMMU
3485 "NOTE: this version of QEMU is faster but it needs slightly patched OSes to\n"
3486 "work. Please use the 'qemu' executable to have a more accurate (but slower)\n"
3492 struct option long_options
[] = {
3493 { "initrd", 1, NULL
, 0, },
3494 { "hda", 1, NULL
, 0, },
3495 { "hdb", 1, NULL
, 0, },
3496 { "snapshot", 0, NULL
, 0, },
3497 { "hdachs", 1, NULL
, 0, },
3498 { "nographic", 0, NULL
, 0, },
3499 { "kernel", 1, NULL
, 0, },
3500 { "append", 1, NULL
, 0, },
3501 { "tun-fd", 1, NULL
, 0, },
3502 { NULL
, 0, NULL
, 0 },
3506 /* SDL use the pthreads and they modify sigaction. We don't
3508 #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)
3509 extern void __libc_sigaction();
3510 #define sigaction(sig, act, oact) __libc_sigaction(sig, act, oact)
3512 extern void __sigaction();
3513 #define sigaction(sig, act, oact) __sigaction(sig, act, oact)
3515 #endif /* CONFIG_SDL */
3517 int main(int argc
, char **argv
)
3519 int c
, ret
, initrd_size
, i
, use_gdbstub
, gdbstub_port
, long_index
;
3520 int snapshot
, linux_boot
, total_ram_size
;
3521 struct linux_params
*params
;
3522 struct sigaction act
;
3523 struct itimerval itv
;
3525 const char *tmpdir
, *initrd_filename
;
3526 const char *hd_filename
[MAX_DISKS
];
3527 const char *kernel_filename
, *kernel_cmdline
;
3528 DisplayState
*ds
= &display_state
;
3530 /* we never want that malloc() uses mmap() */
3531 mallopt(M_MMAP_THRESHOLD
, 4096 * 1024);
3532 initrd_filename
= NULL
;
3533 for(i
= 0; i
< MAX_DISKS
; i
++)
3534 hd_filename
[i
] = NULL
;
3535 phys_ram_size
= 32 * 1024 * 1024;
3536 vga_ram_size
= VGA_RAM_SIZE
;
3537 pstrcpy(network_script
, sizeof(network_script
), DEFAULT_NETWORK_SCRIPT
);
3539 gdbstub_port
= DEFAULT_GDBSTUB_PORT
;
3542 kernel_filename
= NULL
;
3543 kernel_cmdline
= "";
3545 c
= getopt_long_only(argc
, argv
, "hm:dn:sp:L:", long_options
, &long_index
);
3550 switch(long_index
) {
3552 initrd_filename
= optarg
;
3555 hd_filename
[0] = optarg
;
3558 hd_filename
[1] = optarg
;
3565 int cyls
, heads
, secs
;
3568 cyls
= strtol(p
, (char **)&p
, 0);
3572 heads
= strtol(p
, (char **)&p
, 0);
3576 secs
= strtol(p
, (char **)&p
, 0);
3579 ide_state
[0].cylinders
= cyls
;
3580 ide_state
[0].heads
= heads
;
3581 ide_state
[0].sectors
= secs
;
3589 kernel_filename
= optarg
;
3592 kernel_cmdline
= optarg
;
3595 net_fd
= atoi(optarg
);
3603 phys_ram_size
= atoi(optarg
) * 1024 * 1024;
3604 if (phys_ram_size
<= 0)
3606 if (phys_ram_size
> PHYS_RAM_MAX_SIZE
) {
3607 fprintf(stderr
, "vl: at most %d MB RAM can be simulated\n",
3608 PHYS_RAM_MAX_SIZE
/ (1024 * 1024));
3613 cpu_set_log(CPU_LOG_ALL
);
3616 pstrcpy(network_script
, sizeof(network_script
), optarg
);
3622 gdbstub_port
= atoi(optarg
);
3630 if (optind
< argc
) {
3631 hd_filename
[0] = argv
[optind
++];
3634 linux_boot
= (kernel_filename
!= NULL
);
3636 if (!linux_boot
&& hd_filename
[0] == '\0')
3640 setvbuf(stdout
, NULL
, _IOLBF
, 0);
3642 /* init network tun interface */
3646 /* init the memory */
3647 tmpdir
= getenv("QEMU_TMPDIR");
3650 snprintf(phys_ram_file
, sizeof(phys_ram_file
), "%s/vlXXXXXX", tmpdir
);
3651 if (mkstemp(phys_ram_file
) < 0) {
3652 fprintf(stderr
, "Could not create temporary memory file '%s'\n",
3656 phys_ram_fd
= open(phys_ram_file
, O_CREAT
| O_TRUNC
| O_RDWR
, 0600);
3657 if (phys_ram_fd
< 0) {
3658 fprintf(stderr
, "Could not open temporary memory file '%s'\n",
3662 total_ram_size
= phys_ram_size
+ vga_ram_size
;
3663 ftruncate(phys_ram_fd
, total_ram_size
);
3664 unlink(phys_ram_file
);
3665 phys_ram_base
= mmap(get_mmap_addr(total_ram_size
),
3667 PROT_WRITE
| PROT_READ
, MAP_SHARED
| MAP_FIXED
,
3669 if (phys_ram_base
== MAP_FAILED
) {
3670 fprintf(stderr
, "Could not map physical memory\n");
3674 /* open the virtual block devices */
3675 for(i
= 0; i
< MAX_DISKS
; i
++) {
3676 if (hd_filename
[i
]) {
3677 bs_table
[i
] = bdrv_open(hd_filename
[i
], snapshot
);
3679 fprintf(stderr
, "vl: could not open hard disk image '%s\n",
3686 /* init CPU state */
3689 cpu_single_env
= env
;
3694 cpu_register_physical_memory(0, phys_ram_size
, 0);
3697 /* now we can load the kernel */
3698 ret
= load_kernel(kernel_filename
, phys_ram_base
+ KERNEL_LOAD_ADDR
);
3700 fprintf(stderr
, "vl: could not load kernel '%s'\n",
3707 if (initrd_filename
) {
3708 initrd_size
= load_image(initrd_filename
, phys_ram_base
+ INITRD_LOAD_ADDR
);
3709 if (initrd_size
< 0) {
3710 fprintf(stderr
, "vl: could not load initial ram disk '%s'\n",
3716 /* init kernel params */
3717 params
= (void *)(phys_ram_base
+ KERNEL_PARAMS_ADDR
);
3718 memset(params
, 0, sizeof(struct linux_params
));
3719 params
->mount_root_rdonly
= 0;
3720 params
->cl_magic
= 0xA33F;
3721 params
->cl_offset
= params
->commandline
- (uint8_t *)params
;
3722 params
->alt_mem_k
= (phys_ram_size
/ 1024) - 1024;
3723 pstrcat(params
->commandline
, sizeof(params
->commandline
), kernel_cmdline
);
3724 params
->loader_type
= 0x01;
3725 if (initrd_size
> 0) {
3726 params
->initrd_start
= INITRD_LOAD_ADDR
;
3727 params
->initrd_size
= initrd_size
;
3729 params
->orig_video_lines
= 25;
3730 params
->orig_video_cols
= 80;
3732 /* setup basic memory access */
3733 env
->cr
[0] = 0x00000033;
3734 cpu_x86_init_mmu(env
);
3736 memset(params
->idt_table
, 0, sizeof(params
->idt_table
));
3738 params
->gdt_table
[2] = 0x00cf9a000000ffffLL
; /* KERNEL_CS */
3739 params
->gdt_table
[3] = 0x00cf92000000ffffLL
; /* KERNEL_DS */
3740 /* for newer kernels (2.6.0) CS/DS are at different addresses */
3741 params
->gdt_table
[12] = 0x00cf9a000000ffffLL
; /* KERNEL_CS */
3742 params
->gdt_table
[13] = 0x00cf92000000ffffLL
; /* KERNEL_DS */
3744 env
->idt
.base
= (void *)((uint8_t *)params
->idt_table
- phys_ram_base
);
3745 env
->idt
.limit
= sizeof(params
->idt_table
) - 1;
3746 env
->gdt
.base
= (void *)((uint8_t *)params
->gdt_table
- phys_ram_base
);
3747 env
->gdt
.limit
= sizeof(params
->gdt_table
) - 1;
3749 cpu_x86_load_seg_cache(env
, R_CS
, KERNEL_CS
, NULL
, 0xffffffff, 0x00cf9a00);
3750 cpu_x86_load_seg_cache(env
, R_DS
, KERNEL_DS
, NULL
, 0xffffffff, 0x00cf9200);
3751 cpu_x86_load_seg_cache(env
, R_ES
, KERNEL_DS
, NULL
, 0xffffffff, 0x00cf9200);
3752 cpu_x86_load_seg_cache(env
, R_SS
, KERNEL_DS
, NULL
, 0xffffffff, 0x00cf9200);
3753 cpu_x86_load_seg_cache(env
, R_FS
, KERNEL_DS
, NULL
, 0xffffffff, 0x00cf9200);
3754 cpu_x86_load_seg_cache(env
, R_GS
, KERNEL_DS
, NULL
, 0xffffffff, 0x00cf9200);
3756 env
->eip
= KERNEL_LOAD_ADDR
;
3757 env
->regs
[R_ESI
] = KERNEL_PARAMS_ADDR
;
3766 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, BIOS_FILENAME
);
3767 ret
= load_image(buf
, phys_ram_base
+ 0x000f0000);
3768 if (ret
!= 0x10000) {
3769 fprintf(stderr
, "vl: could not load PC bios '%s'\n", buf
);
3774 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, VGABIOS_FILENAME
);
3775 ret
= load_image(buf
, phys_ram_base
+ 0x000c0000);
3777 /* setup basic memory access */
3778 env
->cr
[0] = 0x60000010;
3779 cpu_x86_init_mmu(env
);
3781 env
->idt
.limit
= 0xffff;
3782 env
->gdt
.limit
= 0xffff;
3783 env
->ldt
.limit
= 0xffff;
3785 /* not correct (CS base=0xffff0000) */
3786 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
3787 cpu_x86_load_seg_cache(env
, R_DS
, 0, NULL
, 0xffff, 0);
3788 cpu_x86_load_seg_cache(env
, R_ES
, 0, NULL
, 0xffff, 0);
3789 cpu_x86_load_seg_cache(env
, R_SS
, 0, NULL
, 0xffff, 0);
3790 cpu_x86_load_seg_cache(env
, R_FS
, 0, NULL
, 0xffff, 0);
3791 cpu_x86_load_seg_cache(env
, R_GS
, 0, NULL
, 0xffff, 0);
3794 env
->regs
[R_EDX
] = 0x600; /* indicate P6 processor */
3803 dumb_display_init(ds
);
3806 sdl_display_init(ds
);
3808 dumb_display_init(ds
);
3811 /* init basic PC hardware */
3812 register_ioport_write(0x80, 1, ioport80_write
, 1);
3814 vga_init(ds
, phys_ram_base
+ phys_ram_size
, phys_ram_size
,
3824 /* setup cpu signal handlers for MMU / self modifying code handling */
3825 sigfillset(&act
.sa_mask
);
3826 act
.sa_flags
= SA_SIGINFO
;
3827 #if !defined(CONFIG_SOFTMMU)
3828 act
.sa_sigaction
= host_segv_handler
;
3829 sigaction(SIGSEGV
, &act
, NULL
);
3830 sigaction(SIGBUS
, &act
, NULL
);
3833 act
.sa_sigaction
= host_alarm_handler
;
3834 sigaction(SIGALRM
, &act
, NULL
);
3836 itv
.it_interval
.tv_sec
= 0;
3837 itv
.it_interval
.tv_usec
= 1000;
3838 itv
.it_value
.tv_sec
= 0;
3839 itv
.it_value
.tv_usec
= 10 * 1000;
3840 setitimer(ITIMER_REAL
, &itv
, NULL
);
3841 /* we probe the tick duration of the kernel to inform the user if
3842 the emulated kernel requested a too high timer frequency */
3843 getitimer(ITIMER_REAL
, &itv
);
3844 timer_ms
= itv
.it_interval
.tv_usec
/ 1000;
3845 pit_min_timer_count
= ((uint64_t)itv
.it_interval
.tv_usec
* PIT_FREQ
) /
3849 cpu_gdbstub(NULL
, main_loop
, gdbstub_port
);