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hw/opentitan: Update the interrupt layout
2021-05-11
Alistai
r
Francis
hw/opentit
a
n: Updat
e
the i
n
t
e
r
r
up
t
layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
a
i
r Fran
c
is
MAINTAINERS:
U
p
d
ate the RISC
-
V CPU M
a
intainers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
a
ir
Francis
targ
e
t/riscv: Us
e
RISCV
E
xc
e
pt
i
on en
u
m for CSR
a
c
c
ess
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Francis
t
a
rget/riscv: Use the RIS
C
VExc
e
pti
o
n enum for CSR
o
perations
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
targ
e
t/riscv: Fix 32-b
i
t HS mode access
p
e
rmissions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
list
a
ir
F
ranci
s
t
arget/ris
c
v: Use the RISCV
E
xcept
i
on enu
m
for CSR
p
redi
c
ates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
s
t
ai
r
Fr
a
ncis
tar
g
et/r
i
s
c
v
: Convert the
R
ISC-V exc
e
p
t
i
ons to an
e
num
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Alistair Fr
a
ncis
MAINTAINE
R
S: Ad
d
a SiF
i
ve
ma
c
hine sect
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Al
i
stai
r
Francis
linux-us
e
r/signal:
Decod
e
wa
i
tid si_
c
od
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Alistair Fra
n
cis
riscv
:
Pa
s
s R
I
SCVHartArraySta
t
e by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Francis
r
i
scv/opentitan:
U
pdate the
O
penTitan memo
r
y lay
o
ut
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
s
tair Fra
n
cis
hw/r
i
scv: Use the C
P
U to determine if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir
Fr
a
ncis
tar
g
et
/
riscv:
c
pu: Set XLEN indep
e
nd
e
n
t
ly from target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lista
i
r
Francis
tar
g
et/riscv: c
s
r
: Remo
v
e compile
t
ime XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Fran
c
is
targ
e
t/r
i
scv:
cpu_helper: Remove compi
l
e
t
ime XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/riscv
:
c
p
u:
R
emove compile
t
ime
X
L
E
N
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
lista
i
r Fra
n
cis
target/risc
v
: Specify
the XLEN for CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair Fra
n
cis
target/riscv: Add a
riscv_c
p
u
_
is_3
2
bit() helper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair
Francis
t
arget/riscv: fpu_help
e
r: Match functi
o
n
defs in
H
E
LPER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Francis
hw/r
i
scv: sifive_u: Remov
e
compile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r
F
ra
n
cis
hw/riscv: spike: Re
m
ove
c
o
m
pile
t
ime XLEN check
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Fra
n
cis
hw/riscv:
v
irt:
Remove compile time
XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
hw/
r
iscv
:
boot: Rem
o
ve compile time
XLE
N
chec
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Franc
i
s
risc
v
:
virt: Remove
t
ar
g
et macro cond
i
ti
o
na
l
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir
Fr
a
nci
s
riscv: sp
i
ke:
R
e
m
ove t
a
rget m
a
c
r
o co
n
d
it
i
ona
l
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
tai
r
Francis
t
arget/riscv:
Add a
T
Y
P
E_RISCV_CPU_BASE CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
is
t
a
ir Francis
hw/ri
s
cv: Expand the is 32-b
i
t check to
support
more
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fr
a
ncis
i
n
tc/ibex_p
l
ic:
C
lear
interrupts that occur during
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
A
l
i
s
tair Francis
register: R
e
move unnecessary NULL ch
e
c
k
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Al
i
st
a
ir Francis
intc
/
i
b
ex_plic: Ensure we
d
o
n't
l
oose inter
r
up
t
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
A
listair
F
r
anci
s
intc
/
ibex_pl
i
c: Fix some typos in the
c
omments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
listair Franc
i
s
hw
/
intc/ibex_plic: Clear the claim re
g
ister when
r
e
ad
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair
F
r
ancis
target/riscv: Sp
l
it the Hypervisor execute load hel
p
ers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
target/riscv: Remove the hyp l
o
ad an
d
s
t
ore fun
c
tion
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Franc
i
s
t
a
rget
/
r
i
scv: Remove t
h
e HS_TWO_STAGE fla
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Franci
s
target/riscv:
S
et the virtualised MMU mo
d
e when
d
oin
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
targ
e
t/riscv: Add a virtu
a
l
i
sed MMU Mod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alis
t
air Francis
linux-user/syscall: Fix missing targe
t
_to_host_t
i
mesp
e
c64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
hw/riscv: Load the kerne
l
after the
firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Fr
a
ncis
hw/riscv: Add a ri
s
c
v_is_32_bit() function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair
Francis
hw/riscv
:
Return the end a
d
dre
s
s
o
f
the load
e
d firmwar
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Franc
i
s
hw/
r
iscv: si
f
ive_u: Allow specifying
t
he CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
t
a
ir Francis
riscv: C
o
nvert i
n
te
r
rupt logs to use
q
e
m
u_log_
m
ask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
Alistair Franci
s
c
o
re/register: Specify ins
t
ance_si
z
e i
n
the TypeI
n
fo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
t
air Fra
n
cis
target/r
i
scv
:
Support the Virtual Instruct
i
on fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
i
r
Francis
target/risc
v
:
R
eturn the e
x
ce
p
tio
n
from invali
d
CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fr
a
nci
s
target/riscv:
S
uppor
t
the v0
.
6 Hypervisor extension
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair Fr
a
ncis
target/riscv: Only support little endian guests
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
i
s
tair
F
ra
n
ci
s
target/riscv: Onl
y
support a sin
g
le VSXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
lis
t
air Francis
target/riscv: Update the
C
SR
s
to the v0
.
6 Hyp ext
e
ns
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv
:
Update the Hypervisor trap ret
u
rn/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
ir Fra
n
cis
target/riscv: F
i
x
t
h
e
interru
p
t cause code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv: Conv
e
rt MSTATUS MTL to GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
t
a
rget/r
i
scv:
Don't allow gues
t
to write t
o
htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair
F
r
a
n
cis
target/risc
v
: Do two-s
t
age l
o
okups on hlv
/
h
l
vx/hs
v
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fra
n
cis
target/risc
v
: Allow
ge
n
erat
i
ng hlv/hlvx
/
hsv instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fra
n
cis
t
a
r
get/
r
iscv: Allow setting a two-s
t
age look
u
p
in th
e
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
lis
t
a
ir Fr
a
n
cis
hw/intc: ibex
_
plic: Honour source
pri
o
rities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
is
t
a
ir Francis
hw/intc: ib
e
x_plic: Don't allow r
e
pea
t
interrupts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair
Fran
c
is
h
w
/
i
ntc: ibex_
p
l
ic: Update the pen
d
ing ir
q
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Ali
s
tair Francis
hw/
s
d
/pl181: Repl
a
c
e fprintf(stder
r
, "*\n") with error_r
e
port()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alista
i
r Francis
h
w/char:
C
onvert the Ibex UART to use the registerf
i
elds A
P
I
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alista
i
r
F
rancis
hw/
c
har: Convert the I
b
ex UART to
us
e
the
q
dev
Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Ali
s
tair Fr
a
ncis
hw/ri
s
cv: A
l
low 64 bit access to SiFive CLI
N
T
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alis
t
air Franc
i
s
t
arget/ris
c
v: Use a smaller guess size
f
or no-
M
MU PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alista
i
r F
r
a
n
cis
riscv/openti
t
an:
C
onne
c
t the UART d
e
vice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair Francis
riscv/opentitan: Co
n
nect the PLIC devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
hw/intc: Initial comm
i
t of lo
w
RISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
t
air Fr
a
n
cis
hw/char: Initial commit
o
f
I
b
ex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
ri
s
cv/opentitan: F
i
x the R
O
M size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir Francis
ta
r
g
et/riscv: Implement ch
e
cks for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
ir
Franc
i
s
targ
e
t
/riscv
:
M
ove the hfen
c
e
i
nstructions
t
o
the
rvh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alis
t
air Fr
a
ncis
target/
r
iscv: Report errors validating 2nd-stage
P
TEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fra
n
cis
targe
t
/
riscv: Set acc
e
ss as
data_load
when validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Ali
s
tair Francis
sifive_e: S
u
pport
the re
v
B machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alis
t
air Fr
a
ncis
r
is
c
v:
I
nitial commit
of OpenTi
t
an m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
ist
a
i
r Francis
targ
e
t/ri
s
cv:
A
dd the lo
w
RIS
C
Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fr
a
nc
i
s
target/riscv: Don't set P
M
P feature in
the
cpu init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Al
i
stair Francis
target/r
i
s
cv: D
i
sa
b
le the MMU correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Al
i
stair
Francis
target/riscv: Don't o
v
e
r
write the reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
is
t
air Franci
s
riscv/boot
:
Add a mi
s
s
i
ng
header
i
nclud
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair Fra
n
cis
r
i
sc
v
: sifive_e: Manually
d
efine the machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alistair
F
rancis
docs: deprecate
d
: Upda
t
e
the
-
bio
s
docume
n
t
ation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alist
a
ir Francis
target
/
riscv: Drop suppor
t
for
I
SA spec
v
ersi
o
n
1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
istair Francis
t
a
rget/riscv: Rem
o
ve the deprecated CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Ali
s
tair
Francis
h
w/riscv:
spike: Remo
v
e depreca
t
ed IS
A
specific m
a
chines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
A
listai
r
Franci
s
risc
v
: AND
s
tage-1 and
s
tage-2 prote
c
tion flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistai
r
Fr
a
nc
i
s
riscv: Don't use st
a
ge-2 PTE
l
ookup p
r
ote
c
tion flag
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-04-29
Alistair Francis
r
i
sc
v
/sif
i
ve_u: Add a serial prop
e
rty
to the sifive_u
S
o
C
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
Alist
a
ir Fra
n
cis
riscv/sifive_u:
Fix u
p
file order
i
n
g
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-30
A
l
i
stair Francis
lin
u
x-user: Su
p
port futex_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistair
F
rancis
linux-
u
ser/riscv: Update th
e
s
y
scal
l
_n
r
's to
th
e
5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Al
i
s
t
air Francis
l
i
nux-u
s
er/s
y
scall: Add s
u
pport f
o
r
c
loc
k
_ge
t
time64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alis
t
air F
r
an
c
is
linux-user: Protect mo
r
e
s
y
scalls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-17
Alista
i
r Francis
tar
g
et/riscv
:
Correctly implem
e
nt TSR
t
r
ap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Al
i
sta
i
r Franci
s
target/riscv: A
l
low e
n
abling
the Hypervisor extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Franc
i
s
tar
g
et/
r
iscv:
Add the
M
ST
A
TUS_MPV_I
S
SET helper macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fran
c
is
target/riscv: A
d
d support for th
e
32-bit M
S
TATUSH CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alis
t
air Fran
c
is
targe
t
/riscv: Set htv
a
l and mtval2 o
n
execptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
listair
Fra
n
cis
t
arget/ris
c
v: Raise the new execptio
n
s when 2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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