| commit | d4cad544992225105d88c3d744bce1b08947dd24 | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 31 Mar 2021 15:00:11 +0000 (31 11:00 -0400) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 11 May 2021 10:02:06 +0000 (11 20:02 +1000) | ||
| tree | 64fbfe4e098d81844b0d22bc4b0e7fb71a2211c8 | treesnapshot (tar.gz zip) |
| parent | ab2c91286c0fca38e10af0908573e776c395445d | commitdiff |
hw/opentitan: Update the interrupt layout
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
| hw/intc/ibex_plic.c | diffblobblamehistory | |
| hw/riscv/opentitan.c | diffblobblamehistory | |
| include/hw/riscv/opentitan.h | diffblobblamehistory |