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target/riscv: Remove the hardcoded HGATP_MODE macro
2021-05-11
Alist
a
ir
F
r
ancis
target/
r
is
c
v:
R
emove the
hardcod
e
d
HGATP
_
MODE macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
ist
a
ir Fr
a
ncis
target/ri
s
cv: Remove the hardco
d
ed SSTATUS_SD macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
listair F
r
ancis
target/ris
c
v
:
Remove the
h
ar
d
cod
e
d
RVXLEN macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alista
i
r Francis
t
a
rget/
r
is
c
v: Add ePMP supp
o
rt for the Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
ncis
targ
e
t/riscv/pmp: Remove outdated comment
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
ista
i
r Franci
s
t
a
rget/ris
c
v:
A
dd
t
he ePMP
feature
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Franci
s
target/riscv:
Fix the PMP is loc
k
ed che
c
k when u
s
ing TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
listair
Fran
c
i
s
hw/ri
s
cv: Enable VIRTIO_VGA for
R
ISC-V virt mach
i
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
h
w/ope
n
titan: Up
d
ate the
i
nterrup
t
lay
o
ut
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fra
n
cis
M
AINTAIN
E
RS: Update the RISC-V
CPU Mai
n
t
a
ine
r
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistai
r
Francis
target/riscv:
U
se RISCV
E
x
ception enum for C
S
R access
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target
/
riscv: Use the RISCVE
x
ceptio
n
enum for CSR operations
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Franc
i
s
t
a
rget/risc
v
:
Fix 32-
b
it HS
m
ode
a
cce
s
s permis
s
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istair
Francis
target
/
r
is
c
v:
Use the RISCVE
x
ceptio
n
e
n
u
m for C
S
R predicates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target/riscv: Convert the RISC-V
e
xcep
t
ions to
an en
u
m
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Al
i
sta
i
r
Fr
a
nci
s
MAI
N
TAI
N
ERS:
A
dd a SiFive machine section
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alis
t
air Francis
linux-user/signal: D
e
code waitid si_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
A
l
ista
i
r
F
rancis
riscv:
Pass R
I
SCVHartArr
a
yState by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r Fra
n
cis
ri
s
cv/opentitan:
U
p
d
ate t
h
e
O
penT
i
ta
n
memo
r
y
layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Franc
i
s
hw/riscv: Use the C
P
U to determ
i
ne if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
t
arget/r
i
scv: cpu:
Set XLEN independently fr
o
m
target
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fran
c
is
ta
r
ge
t
/ri
s
cv: csr
:
Remove comp
i
le
time
X
LEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
sta
i
r Francis
target/r
i
scv:
c
pu_helper: Remove compile t
i
me X
L
EN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alista
i
r Francis
target/risc
v
: cpu
:
R
e
move compil
e
ti
m
e
XLEN che
c
ks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alist
a
ir
F
rancis
target/riscv: Sp
e
cify the XLEN for CP
U
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
Franc
i
s
target/r
i
scv: Add a
r
iscv_cp
u
_is_32bit() helper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/ri
s
cv:
fpu_helper: Mat
c
h
fu
n
ction defs i
n
HE
L
PER
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Fra
n
cis
hw/riscv: s
i
five_u: Remove compile time
XLE
N
checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair
F
rancis
hw
/
riscv: spike: Rem
o
v
e
compil
e
t
i
me XLEN chec
k
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
is
t
air Francis
hw/riscv:
virt: Remove comp
i
le time
X
L
EN c
h
ecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
ancis
hw/riscv: boot: Remove
compile time XLEN checks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Al
i
stair Francis
r
iscv: vi
r
t: Remove target macro conditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistai
r
Fr
a
n
cis
riscv:
s
p
i
ke: Remove target macro conditionals
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair Francis
t
a
rget/riscv: Add a TY
P
E_RISCV_C
P
U_
B
ASE CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Franc
i
s
hw/r
i
scv: Expand the is 32-bit check to supp
o
rt
more
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
a
n
cis
intc/ibex_plic: Cl
e
ar interrupts that o
c
cu
r
during
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-17
Alistair Fra
n
cis
re
g
i
s
t
er:
R
emove
unnecessar
y
NULL c
h
eck
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair
F
r
a
ncis
intc
/
ibex_plic: E
n
s
u
re we don't lo
o
se int
e
rrupt
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
intc/i
b
ex
_
plic
:
Fix some typos in
t
he comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Al
i
st
a
ir F
r
ancis
hw/intc/ibex_plic
:
Clear
t
he clai
m
regi
s
ter when
r
ead
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Ali
s
tair Franc
i
s
t
a
rge
t
/
r
i
s
cv: Split the Hype
r
visor e
x
ecu
t
e load helpers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
listair Fra
n
c
i
s
target/ri
s
cv: Remove the hyp loa
d
and store
functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair F
r
ancis
target/riscv: Remove the HS_T
W
O_STAGE
f
lag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Al
i
stair
Francis
t
a
rget/riscv: Set the virtualised MMU mode w
h
en d
o
i
ng
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair F
r
anci
s
t
arget/riscv: A
d
d a virtua
l
ised
M
MU Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Alistair Francis
l
inux-user/s
y
scall
:
Fix missing target
_
to_host_
t
i
mespec
6
4
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair
F
ranc
i
s
h
w
/riscv: Lo
a
d the kernel after the firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistair Francis
hw/riscv: Add a
r
is
c
v
_
is_32_bit()
fun
c
t
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tair Francis
hw/
r
iscv: R
e
turn
the end address of the loaded firmware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alistai
r
Fra
n
cis
hw/ri
s
c
v
: sifive_u: Al
l
ow
specifying
t
he
C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tai
r
Francis
riscv: Convert interrupt logs to
u
s
e
q
e
m
u_log
_
mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
listair
F
rancis
core/register: Sp
e
c
i
fy
i
n
s
tance_si
z
e in the Ty
p
e
I
nfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
targe
t
/riscv: Suppo
r
t t
h
e
V
irtual Instruction fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
istair Francis
ta
r
ge
t
/
ri
s
cv: Return t
h
e exception from
invalid CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Franc
i
s
t
arget/r
i
scv: Support t
h
e v0
.
6
H
yp
e
rvi
s
o
r
exte
n
sio
n
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
target/riscv: Only suppo
r
t litt
l
e endian g
u
e
s
ts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alista
i
r Francis
t
arget
/
riscv
:
Only support
a sin
g
le VSXL length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
ista
i
r Franc
i
s
t
a
rg
e
t/riscv: U
p
date the CSRs to the
v
0
.
6
H
yp ext
e
nsion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alis
t
a
i
r Fr
a
ncis
t
arget/ri
s
c
v
: Updat
e
the
H
ypervisor
trap return/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair Francis
t
arget/riscv: Fix the interrupt cause cod
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
t
a
rget/r
i
scv: Convert MSTATUS MTL to G
V
A
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Franc
i
s
t
a
rge
t
/
r
iscv:
D
on'
t
allow
guest to write to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
rancis
target/riscv: Do two
-
s
t
age lookups
o
n
hlv
/
hlv
x
/hsv
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair Fr
a
nci
s
target/riscv:
Allow generatin
g
hl
v
/
h
lvx/
h
s
v
i
n
st
r
uctions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
targ
e
t/risc
v
: Allow setting a two-stage lookup
i
n the
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistai
r
F
r
a
ncis
hw/intc: ibex_p
l
ic:
H
onou
r
sourc
e
p
r
iorities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
A
l
ist
a
ir Francis
hw/intc: i
b
ex_plic:
Don't
a
ll
o
w repeat interrupts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Ali
s
tair Francis
hw/intc: ibex_plic: Update
the pending
i
rqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
Alistai
r
Francis
hw/
s
d
/pl181: Repl
a
ce fp
r
intf(stderr, "
*
\n") with error_repo
r
t()
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair Franci
s
hw/char
:
Convert th
e
Ibex UART to use
t
he
registerf
i
elds
API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistair F
r
anc
i
s
hw/
c
har: Co
n
v
e
r
t the Ibex UART to us
e
the qdev Cl
o
ck
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alista
i
r Franc
i
s
hw/
r
iscv: Allow 6
4
b
i
t
acces
s
to SiFive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
i
s
tair Francis
target/riscv
:
Use
a sma
l
ler
g
ues
s
size for no-M
M
U
PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistai
r
Fr
a
n
c
is
riscv/opentitan:
C
onnect the U
A
RT d
e
vi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-19
Alistair Francis
risc
v
/o
p
e
n
tita
n
: Conne
c
t the PLIC device
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-06-19
Alistair
F
rancis
hw
/
intc
:
In
i
tial
comm
i
t of lowRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair
F
rancis
hw/cha
r
:
Ini
t
ial com
m
it o
f
I
bex UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alista
i
r
Franc
i
s
ris
c
v/opentitan: Fix the ROM
s
iz
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
A
l
istair Francis
target/
r
i
scv: Implement c
h
ec
k
s fo
r
hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Franci
s
target/r
i
scv
:
Move the hfenc
e
instru
c
tions to the
r
vh
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-19
Alistair Fran
c
is
target/
r
i
s
cv: Report errors validating 2nd-stage PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-06-19
Alistair
Fran
c
is
targ
e
t/ri
s
cv: Set access
as data_load when validati
n
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-19
A
listair Francis
sifive_e: Suppor
t
the revB machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-06-03
Ali
s
tair Francis
r
iscv: Initial
commit of OpenTitan machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-06-03
Ali
s
tai
r
Fra
n
cis
target/
r
iscv:
Add the lowRISC Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-06-03
Al
i
st
a
ir Franci
s
target
/
riscv: Don't set PMP feat
u
re in the cpu init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-06-03
Alista
i
r Franci
s
t
arge
t
/riscv: Disable the MMU
c
o
r
rectly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
A
l
i
stair Fr
a
nc
i
s
target/riscv: Don't overwrite
the
reset
v
ector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-03
A
list
a
ir Fran
c
i
s
r
isc
v
/bo
o
t: Add a missing
h
eade
r
inc
l
ude
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-03
Alistair Francis
ris
c
v
:
sifive_e
:
Manua
l
ly define the
m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-03
Alistair Francis
d
o
cs:
deprecated: Update the -bios d
o
cu
m
entation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-03
Alistair Francis
target/ris
c
v
: Drop
s
upport for ISA spec version
1
.
0
9
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-06-03
Alist
a
ir Franc
i
s
target
/
riscv:
R
emove t
h
e
deprec
a
ted CPUs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-06-03
Alista
i
r
Franci
s
hw/riscv: s
p
ike:
R
emove depre
c
ated ISA
s
p
ecific machines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
Alistair Francis
riscv: AND stage
-
1
an
d
s
t
a
g
e-2 p
r
o
t
ection flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
Alistair Francis
r
i
scv:
Don't use
stag
e
-2 PTE look
u
p
p
rotection flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-04-29
Alis
t
air Franc
i
s
risc
v
/
sifive
_
u: Add
a
serial prop
e
rty
to the
s
ifive_u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-04-29
Alist
a
ir Francis
riscv/sifive_u:
F
ix up file ordering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-03-30
Alistair Fran
c
i
s
linux
-
use
r
: Support fut
e
x_time64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-03-20
Alistai
r
Francis
linux-user/ris
c
v: Update
t
he
s
ys
c
all_nr's
to
the 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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