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target/riscv: cpu: Fixup indentation
2022-04-22 Alistair Francistarget/riscv: cpu: Fixup indentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Implement the stval/mtval illegal instruction
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Fixup setting GVA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: virt: Allow support for 32 cores
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/riscv: Use error_fatal for SoC realisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Enable the Hypervisor extension by default
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francistarget/riscv: Mark the Hypervisor extension as non...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup remaining functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the read function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Cleanup the write function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-01-08 Alistair Francishw/intc: sifive_plic: Add a reset function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: opentitan: Fixup the PLIC context addresses
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: virt: Use the PLIC config helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: microchip_pfsoc: Use the PLIC config helper...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: sifive_u: Use the PLIC config helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: boot: Add a PLIC config string function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-28 Alistair Francishw/riscv: virt: Don't use a macro for the PLIC configuration
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the irq_request function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: sifive_plic: Cleanup the realize function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: sifive_plic: Move the properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/intc: Remove the Ibex PLIC
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-22 Alistair Francishw/riscv: opentitan: Update to the latest build
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Alistair Francistarget/riscv: Organise the CPU properties
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-21 Alistair Francistarget/riscv: Remove some unused macros
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-10-06 Alistair Francishw/riscv: shakti_c: Mark as not user creatable
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-21 Alistair Francishw/riscv: opentitan: Correct the USB Dev address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francissifive_u: Connect the SiFive PWM device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/timer: Add SiFive PWM support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_timer: Convert the timer to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_plic: Convert the PLIC to use RISC...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: ibex_plic: Convert the PLIC to use RISC-V...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francishw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Expose interrupt pending bits as GPIO...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-09-20 Alistair Francistarget/riscv: Update the ePMP CSR address
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv/boot: Check the error of fdt_pack()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the flash alias
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francishw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-07-14 Alistair Francischar: ibex_uart: Update the register layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/riscv: OpenTitan: Connect the mtime and mtimecmp...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/timer: Initial commit of Ibex Timer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francishw/char/ibex_uart: Make the register layout private
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francistarget/riscv: Use target_ulong for the DisasContext...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francistarget/riscv/pmp: Add assert for ePMP operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francisdocs/system: Move the RISC-V -bios information to removed
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the RV64H decode comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add ePMP support for the Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv/pmp: Remove outdated comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add the ePMP feature
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the PMP is locked check when using TOR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/opentitan: Update the interrupt layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair FrancisMAINTAINERS: Update the RISC-V CPU Maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR predicates
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Alistair FrancisMAINTAINERS: Add a SiFive machine section
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-02-13 Alistair Francislinux-user/signal: Decode waitid si_code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-01-16 Alistair Francisriscv: Pass RISCVHartArrayState by pointer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francisriscv/opentitan: Update the OpenTitan memory layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: Use the CPU to determine if 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: cpu: Set XLEN independently from target
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: csr: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: cpu_helper: Remove compile time XLEN...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: cpu: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: Specify the XLEN for CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: fpu_helper: Match function defs in HELPER...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: sifive_u: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: spike: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: virt: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: boot: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francisriscv: virt: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francisriscv: spike: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francistarget/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francishw/riscv: Expand the is 32-bit check to support more...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-12-18 Alistair Francisintc/ibex_plic: Clear interrupts that occur during...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-17 Alistair Francisregister: Remove unnecessary NULL check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-14 Alistair Francisintc/ibex_plic: Ensure we don't loose interrupts
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-14 Alistair Francisintc/ibex_plic: Fix some typos in the comments
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-09 Alistair Francishw/intc/ibex_plic: Clear the claim register when read
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-09 Alistair Francistarget/riscv: Split the Hypervisor execute load helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-09 Alistair Francistarget/riscv: Remove the hyp load and store functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-09 Alistair Francistarget/riscv: Remove the HS_TWO_STAGE flag
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-09 Alistair Francistarget/riscv: Set the virtualised MMU mode when doing...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-09 Alistair Francistarget/riscv: Add a virtualised MMU Mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-04 Alistair Francislinux-user/syscall: Fix missing target_to_host_timespec64...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Load the kernel after the firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Add a riscv_is_32_bit() function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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