repo.or.cz
/
qemu
/
kevin.git
/
search
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
log
|
graphiclog1
|
graphiclog2
|
commit
|
commitdiff
|
tree
|
refs
|
edit
|
fork
first
·
prev
·
next
target/ppc: Clean up local variable shadowing in kvm_arch_*_registers()
2023-09-29
Alistair
Francis
softmmu/devic
e
_tree: Fixu
p
local v
a
ria
b
les sh
a
dowing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2023-09-29
Alistair Francis
ta
r
get/riscv: vector_helper: Fixup lo
c
al vari
a
bles
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2023-09-29
Alis
t
air Francis
target/riscv: cp
u
: Fixup local varia
b
les shadow
i
ng
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2023-09-29
A
listair F
r
anci
s
hw/riscv: open
t
itan: F
i
xup local variables shadowing
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2023-02-23
Alistair
F
ra
n
cis
MAI
N
TAINERS: Add som
e
RISC-V reviewe
r
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2023-02-06
Alistair Francis
hw/ri
s
c
v: boot: D
o
n't use CSRs if they are disabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-10-14
A
l
ista
i
r
Franc
i
s
t
a
rget
/
r
i
s
cv: pmp:
F
i
xup TLB size calc
u
lation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-09-26
A
l
istair F
r
a
n
cis
h
w
/r
i
s
c
v: op
e
ntitan: Ex
p
ose the resetvec as a SoC propert
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-09-26
Alistai
r
Francis
hw
/
riscv: open
t
itan: Fix
u
p
resetvec
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-09-26
Alistair Fra
n
cis
targe
t
/
ris
c
v
: Set the CPU re
s
etvec direct
l
y
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-07-03
Alistair Francis
h
w
/riscv: boo
t
: Reduce FDT ad
d
ress
alignment constra
i
nt
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-07-03
Al
i
stair Francis
target/riscv: I
b
ex
:
Support
p
riv
v
e
rsion 1
.
1
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-07-03
Alistair Franc
i
s
target/riscv: F
i
xup
MSECCFG minimum
p
riv check
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
Ali
s
tair Francis
t
a
rget/riscv: t
r
ans_rvv:
A
v
oid ass
e
rt for RV32 and
e64
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
Alist
a
ir
Francis
target/risc
v
:
D
on't e
x
p
o
se the CP
U
p
ro
p
erties on names
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
Alistair Francis
h
w/intc: sifive_plic: Av
o
id over
f
l
o
wing the addr_
c
o
nfi
g
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-06-09
Alistai
r
Francis
MA
I
NTA
I
N
E
R
S: C
o
ver hw
/
c
o
r
e/u
b
oot_image
.
h
wit
h
in Generic
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alistair Francis
hw/ri
s
cv: Enable TPM
backends
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alista
i
r
Fra
n
cis
hw/riscv
:
vir
t
: Add device
p
lug
s
uppor
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Ali
s
tair
F
r
ancis
hw/
r
iscv
:
virt: Add suppor
t
fo
r
generating platform
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alistair Francis
hw/ris
c
v: v
i
rt:
C
r
e
ate a platfo
r
m
bus
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alistair
F
r
ancis
h
w/co
r
e:
M
ove the ARM sysbus-f
d
t to core
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-29
Alistai
r
F
r
an
c
is
hw/risc
v
: vi
r
t: Add a ma
c
hi
n
e done notifier
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-22
Alistair Fra
n
cis
target/ris
c
v: Allow software access
t
o MI
P
SEIP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-04-22
Ali
s
tai
r
Francis
target
/
ris
c
v:
cpu:
F
ixup indentation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistai
r
Fr
a
n
c
is
targe
t
/r
i
scv:
I
mpleme
n
t the stv
a
l/mtval
illeg
a
l instr
u
ctio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Francis
t
a
r
g
et/r
i
scv: Fixup setting GVA
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alistair Fra
n
cis
targ
e
t
/
r
iscv: Set
t
he opcode in DisasCont
e
xt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Ali
s
tair Francis
hw/riscv: virt: Allow support
for 32 cores
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alista
i
r F
r
anc
i
s
hw/riscv: Us
e
e
r
ror_fatal for SoC r
e
a
lisation
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
l
is
t
a
ir Franci
s
tar
g
e
t
/riscv: Enable
the Hypervi
s
or extension b
y
default
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
l
istair Francis
target/risc
v
: Mark
t
he Hype
r
visor extension as
n
on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Ali
s
t
a
ir Fra
n
cis
hw/i
n
tc
:
sifive_plic: Cleanup rem
a
ining
f
u
nc
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
listair Francis
hw/intc: si
f
ive_pl
i
c: Cl
e
anu
p
the r
e
ad fun
c
tion
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
Alist
a
ir Francis
h
w
/int
c
:
s
ifive_plic:
Cleanup the wri
t
e function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2022-01-08
A
l
istai
r
Francis
hw/intc: sifive
_
plic: Add a res
e
t function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistair Fra
n
c
i
s
hw/r
i
s
c
v:
o
p
entitan: Fixup t
h
e PLI
C
c
ontext
addresses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistair Francis
h
w/ri
s
c
v
:
v
irt: Use
t
he PLIC co
n
fig hel
p
er function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
A
listai
r
Francis
hw/risc
v
:
m
icrochip_pfsoc: Use the PLIC c
o
n
f
ig he
l
per
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alist
a
ir
F
ran
c
is
hw/ri
s
cv: sifive_u: Use the PLIC config helper function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
A
listair Francis
hw/riscv: boot: Add a
P
LIC config st
r
i
n
g fun
c
tio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-28
Alistai
r
Francis
hw/riscv:
virt: Don't u
s
e a
m
a
cro
f
or the PLIC configuration
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistair Francis
hw/in
t
c: sifive_pli
c
: Cleanup the irq_request funct
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistai
r
Francis
hw
/
intc: sif
i
ve_plic: Clea
n
up
the
r
eal
i
z
e function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistair F
r
a
ncis
h
w/intc: sifiv
e
_
p
lic: Move the p
r
operties
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
Alistair Fra
n
ci
s
hw/int
c
: Remove the Ibe
x
PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-22
A
li
s
tair F
r
an
c
i
s
hw/
r
iscv:
opentitan: U
p
date to th
e
latest buil
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-21
Alistair Fra
n
cis
target/riscv: Organise the C
P
U properties
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-21
Alista
i
r Fran
c
is
target/riscv: Remove some u
n
used macros
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-10-06
Ali
s
tair Francis
hw/
r
is
c
v:
s
hakti_
c
: Mark
as not user cre
a
table
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-21
Ali
s
tair Fran
c
is
hw
/
ri
s
cv: opentitan: Correct the USB Dev addr
e
s
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Francis
sifi
v
e_u: Connect t
h
e SiFive PWM devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistai
r
Fran
c
is
hw/t
i
mer: Add SiFive PWM support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair
F
ran
c
i
s
hw/int
c
: ibex_tim
e
r: Conver
t
the time
r
to us
e
R
I
SC
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Fran
c
is
h
w/intc:
sifive_plic: Convert the PLIC
t
o
use R
I
SC
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alist
a
ir F
r
ancis
hw/intc:
i
b
ex
_
p
lic: Convert th
e
PLIC
t
o use R
I
SC-
V
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair F
r
an
c
i
s
hw/intc: sifive_clin
t
: Use RISC-V
CPU GPIO lin
e
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
A
l
i
st
a
ir Francis
target/riscv: Expose
interrupt
p
ending bits a
s
G
P
IO
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Alistair Franc
i
s
t
arget/riscv: Update
t
he ePMP CSR addres
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Al
i
sta
i
r F
r
ancis
hw/riscv
/
b
o
ot: Ch
e
ck th
e
error of fdt_
p
ack()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Ali
s
tair Fr
a
nci
s
hw/r
i
scv:
o
pentitan: Add t
h
e flash alias
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Al
i
stair F
r
a
n
cis
hw/riscv: op
e
ntitan: A
d
d the u
n
implement rv_cor
e
_
i
bex_peri
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-07-14
Ali
s
ta
i
r F
r
ancis
char: ibex_uart: Update the r
e
gis
t
er layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Al
i
stair Fra
n
cis
hw/riscv
:
OpenTitan: Connect the mtim
e
and mtimec
m
p
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alistair Francis
hw/timer: Initial commit of Ibex
Timer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Al
i
stair
F
rancis
hw/char/ibex_uart:
M
ake the regi
s
ter
l
a
yout priva
t
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-24
Alistair
F
r
ancis
target/riscv:
U
se
t
a
r
get_ulong for the DisasCont
e
xt
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-07
Alistair F
r
ancis
target/ri
s
cv/pmp: Add assert
f
or e
P
MP operations
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-06-07
A
lista
i
r Francis
docs/system
:
Move the
RISC
-
V -
b
ios info
r
mation
t
o removed
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
Francis
t
a
rget/riscv: Fix t
h
e
R
V6
4
H decode comm
e
nt
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair
F
r
ancis
target
/
riscv: C
o
n
solidat
e
RV32/64 1
6
-
b
it instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
air F
r
ancis
t
arget/riscv: Conso
l
id
a
te RV32/64 32-bit instructions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alista
i
r Francis
t
arg
e
t/riscv: Remove an unu
s
ed
CA
S
E_OP_32_64 macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
ta
r
get/riscv: Rem
o
ve the unuse
d
HSTATUS_WPRI m
a
cro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alist
a
ir Francis
ta
r
get/riscv: Remove the hardcoded SAT
P
_MO
D
E m
a
cro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
l
istair Francis
targ
e
t/ris
c
v: Remove
t
h
e h
a
r
dcode
d
MS
T
AT
U
S_SD macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair F
r
anc
i
s
t
arge
t
/riscv: R
e
m
o
v
e
the h
a
rdco
d
ed HGAT
P
_MODE macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
tair Francis
target/riscv: Remove
t
h
e
ha
r
dcoded
S
STAT
U
S_SD macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
t
ar
g
et/risc
v
: Remove th
e
hardcoded RVX
L
EN macro
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target/riscv: Add ePMP suppor
t
for
t
he
I
bex CP
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Ali
s
tair Franci
s
t
a
r
get/riscv/
p
mp:
R
e
move outdated comment
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Fr
a
ncis
tar
g
et/riscv: Ad
d
t
h
e eP
M
P feature
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alista
i
r Franc
i
s
t
arget/risc
v
:
F
ix t
h
e PMP is
lo
c
ked check when using TOR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
hw/riscv:
Enab
l
e
V
I
RTI
O
_VGA for RISC-V
v
irt m
a
chine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
listair Fra
n
cis
hw/opentitan: Update the in
t
e
rrupt layout
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
A
listair Fran
c
is
M
A
INTAINERS
:
Up
d
ate the RISC-V CPU
M
aint
a
iners
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target/
r
iscv: Use RI
S
CVException enu
m
fo
r
CSR acce
s
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alis
t
a
ir Francis
ta
r
get/ris
c
v: Use
t
h
e
RISCVExcep
t
io
n
enum for CSR operat
i
ons
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Al
i
s
t
air Francis
target/riscv:
Fix 32-
b
it HS m
o
de
a
ccess per
m
i
s
sion
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target/ris
c
v
: Use
the RISCVExc
e
p
t
ion enum for CSR pr
e
di
c
ates
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-05-11
Alistair Francis
target/
r
iscv: Convert t
h
e RISC-
V
exceptions t
o
an enum
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-03-04
Ali
s
t
a
ir Franc
i
s
MAINTAINERS: Add a SiFive m
a
chi
n
e section
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-02-13
Alistai
r
Fr
a
ncis
linu
x
-use
r
/signal: Dec
o
de
w
aitid
s
i_code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2021-01-16
Ali
s
tair Franc
i
s
riscv: Pass
RISCVHartA
r
r
a
y
S
t
ate by pointer
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair F
r
ancis
riscv/o
p
entitan
:
Update the
O
p
enTit
a
n mem
o
ry layo
u
t
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair Fr
a
ncis
hw/riscv: U
s
e the CPU to determine if 32-bit
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Alistair Francis
target/riscv: cp
u
: Set XLEN independently from
t
arget
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
istair Francis
target/riscv:
c
sr:
Remove compile
t
ime X
L
EN c
h
ecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
A
l
i
stair Fr
a
ncis
targ
e
t
/
r
iscv: cpu_helper: Remove compile
t
ime XLEN
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Ali
s
t
a
i
r Francis
target/riscv:
cpu: Remove c
o
mp
i
le time
X
LEN
c
hecks
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
next