2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 # define LOG_DISAS(...) do { } while (0)
49 /*****************************************************************************/
50 /* Code translation helpers */
52 /* global register indexes */
53 static TCGv_env cpu_env
;
54 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i64 cpu_fpr
[32];
63 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
64 static TCGv_i64 cpu_vsr
[32];
65 static TCGv_i32 cpu_crf
[8];
70 #if defined(TARGET_PPC64)
73 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
74 static TCGv cpu_reserve
;
75 static TCGv cpu_fpscr
;
76 static TCGv_i32 cpu_access_type
;
78 #include "exec/gen-icount.h"
80 void ppc_translate_init(void)
84 size_t cpu_reg_names_size
;
85 static int done_init
= 0;
90 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
93 cpu_reg_names_size
= sizeof(cpu_reg_names
);
95 for (i
= 0; i
< 8; i
++) {
96 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
97 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
98 offsetof(CPUPPCState
, crf
[i
]), p
);
100 cpu_reg_names_size
-= 5;
103 for (i
= 0; i
< 32; i
++) {
104 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
105 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
106 offsetof(CPUPPCState
, gpr
[i
]), p
);
107 p
+= (i
< 10) ? 3 : 4;
108 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
109 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
110 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
111 offsetof(CPUPPCState
, gprh
[i
]), p
);
112 p
+= (i
< 10) ? 4 : 5;
113 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
115 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
116 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
117 offsetof(CPUPPCState
, fpr
[i
]), p
);
118 p
+= (i
< 10) ? 4 : 5;
119 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
121 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
124 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
126 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
127 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
129 p
+= (i
< 10) ? 6 : 7;
130 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
132 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
135 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
137 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
138 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
140 p
+= (i
< 10) ? 6 : 7;
141 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
142 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
143 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
144 offsetof(CPUPPCState
, vsr
[i
]), p
);
145 p
+= (i
< 10) ? 5 : 6;
146 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
149 cpu_nip
= tcg_global_mem_new(cpu_env
,
150 offsetof(CPUPPCState
, nip
), "nip");
152 cpu_msr
= tcg_global_mem_new(cpu_env
,
153 offsetof(CPUPPCState
, msr
), "msr");
155 cpu_ctr
= tcg_global_mem_new(cpu_env
,
156 offsetof(CPUPPCState
, ctr
), "ctr");
158 cpu_lr
= tcg_global_mem_new(cpu_env
,
159 offsetof(CPUPPCState
, lr
), "lr");
161 #if defined(TARGET_PPC64)
162 cpu_cfar
= tcg_global_mem_new(cpu_env
,
163 offsetof(CPUPPCState
, cfar
), "cfar");
166 cpu_xer
= tcg_global_mem_new(cpu_env
,
167 offsetof(CPUPPCState
, xer
), "xer");
168 cpu_so
= tcg_global_mem_new(cpu_env
,
169 offsetof(CPUPPCState
, so
), "SO");
170 cpu_ov
= tcg_global_mem_new(cpu_env
,
171 offsetof(CPUPPCState
, ov
), "OV");
172 cpu_ca
= tcg_global_mem_new(cpu_env
,
173 offsetof(CPUPPCState
, ca
), "CA");
175 cpu_reserve
= tcg_global_mem_new(cpu_env
,
176 offsetof(CPUPPCState
, reserve_addr
),
179 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
180 offsetof(CPUPPCState
, fpscr
), "fpscr");
182 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
183 offsetof(CPUPPCState
, access_type
), "access_type");
188 /* internal defines */
189 struct DisasContext
{
190 struct TranslationBlock
*tb
;
194 /* Routine used to access memory */
199 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask
;
202 #if defined(TARGET_PPC64)
211 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled
;
213 uint64_t insns_flags
;
214 uint64_t insns_flags2
;
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext
*ctx
)
220 #if defined(TARGET_WORDS_BIGENDIAN)
223 return !ctx
->le_mode
;
227 /* True when active word size < size of target_long. */
229 # define NARROW_MODE(C) (!(C)->sf_mode)
231 # define NARROW_MODE(C) 0
234 struct opc_handler_t
{
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 /* instruction type */
241 /* extended instruction type */
244 void (*handler
)(DisasContext
*ctx
);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248 #if defined(DO_PPC_STATISTICS)
253 static inline void gen_reset_fpstatus(void)
255 gen_helper_reset_fpstatus(cpu_env
);
258 static inline void gen_compute_fprf(TCGv_i64 arg
)
260 gen_helper_compute_fprf(cpu_env
, arg
);
261 gen_helper_float_check_status(cpu_env
);
264 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
266 if (ctx
->access_type
!= access_type
) {
267 tcg_gen_movi_i32(cpu_access_type
, access_type
);
268 ctx
->access_type
= access_type
;
272 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
274 if (NARROW_MODE(ctx
)) {
277 tcg_gen_movi_tl(cpu_nip
, nip
);
280 void gen_update_current_nip(void *opaque
)
282 DisasContext
*ctx
= opaque
;
284 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
287 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
290 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
291 gen_update_nip(ctx
, ctx
->nip
);
293 t0
= tcg_const_i32(excp
);
294 t1
= tcg_const_i32(error
);
295 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
296 tcg_temp_free_i32(t0
);
297 tcg_temp_free_i32(t1
);
298 ctx
->exception
= (excp
);
301 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
304 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
305 gen_update_nip(ctx
, ctx
->nip
);
307 t0
= tcg_const_i32(excp
);
308 gen_helper_raise_exception(cpu_env
, t0
);
309 tcg_temp_free_i32(t0
);
310 ctx
->exception
= (excp
);
313 static inline void gen_debug_exception(DisasContext
*ctx
)
317 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
318 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
319 gen_update_nip(ctx
, ctx
->nip
);
321 t0
= tcg_const_i32(EXCP_DEBUG
);
322 gen_helper_raise_exception(cpu_env
, t0
);
323 tcg_temp_free_i32(t0
);
326 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
328 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_INVAL
| error
);
331 /* Stop translation */
332 static inline void gen_stop_exception(DisasContext
*ctx
)
334 gen_update_nip(ctx
, ctx
->nip
);
335 ctx
->exception
= POWERPC_EXCP_STOP
;
338 #ifndef CONFIG_USER_ONLY
339 /* No need to update nip here, as execution flow will change */
340 static inline void gen_sync_exception(DisasContext
*ctx
)
342 ctx
->exception
= POWERPC_EXCP_SYNC
;
346 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
347 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
349 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
350 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
352 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
353 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
355 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
356 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
358 typedef struct opcode_t
{
359 unsigned char opc1
, opc2
, opc3
;
360 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
361 unsigned char pad
[5];
363 unsigned char pad
[1];
365 opc_handler_t handler
;
369 /*****************************************************************************/
370 /*** Instruction decoding ***/
371 #define EXTRACT_HELPER(name, shift, nb) \
372 static inline uint32_t name(uint32_t opcode) \
374 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
377 #define EXTRACT_SHELPER(name, shift, nb) \
378 static inline int32_t name(uint32_t opcode) \
380 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
383 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
384 static inline uint32_t name(uint32_t opcode) \
386 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
387 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
390 EXTRACT_HELPER(opc1
, 26, 6);
392 EXTRACT_HELPER(opc2
, 1, 5);
394 EXTRACT_HELPER(opc3
, 6, 5);
395 /* Update Cr0 flags */
396 EXTRACT_HELPER(Rc
, 0, 1);
397 /* Update Cr6 flags (Altivec) */
398 EXTRACT_HELPER(Rc21
, 10, 1);
400 EXTRACT_HELPER(rD
, 21, 5);
402 EXTRACT_HELPER(rS
, 21, 5);
404 EXTRACT_HELPER(rA
, 16, 5);
406 EXTRACT_HELPER(rB
, 11, 5);
408 EXTRACT_HELPER(rC
, 6, 5);
410 EXTRACT_HELPER(crfD
, 23, 3);
411 EXTRACT_HELPER(crfS
, 18, 3);
412 EXTRACT_HELPER(crbD
, 21, 5);
413 EXTRACT_HELPER(crbA
, 16, 5);
414 EXTRACT_HELPER(crbB
, 11, 5);
416 EXTRACT_HELPER(_SPR
, 11, 10);
417 static inline uint32_t SPR(uint32_t opcode
)
419 uint32_t sprn
= _SPR(opcode
);
421 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
423 /*** Get constants ***/
424 /* 16 bits signed immediate value */
425 EXTRACT_SHELPER(SIMM
, 0, 16);
426 /* 16 bits unsigned immediate value */
427 EXTRACT_HELPER(UIMM
, 0, 16);
428 /* 5 bits signed immediate value */
429 EXTRACT_HELPER(SIMM5
, 16, 5);
430 /* 5 bits signed immediate value */
431 EXTRACT_HELPER(UIMM5
, 16, 5);
433 EXTRACT_HELPER(NB
, 11, 5);
435 EXTRACT_HELPER(SH
, 11, 5);
436 /* Vector shift count */
437 EXTRACT_HELPER(VSH
, 6, 4);
439 EXTRACT_HELPER(MB
, 6, 5);
441 EXTRACT_HELPER(ME
, 1, 5);
443 EXTRACT_HELPER(TO
, 21, 5);
445 EXTRACT_HELPER(CRM
, 12, 8);
447 #ifndef CONFIG_USER_ONLY
448 EXTRACT_HELPER(SR
, 16, 4);
452 EXTRACT_HELPER(FPBF
, 23, 3);
453 EXTRACT_HELPER(FPIMM
, 12, 4);
454 EXTRACT_HELPER(FPL
, 25, 1);
455 EXTRACT_HELPER(FPFLM
, 17, 8);
456 EXTRACT_HELPER(FPW
, 16, 1);
458 /*** Jump target decoding ***/
459 /* Immediate address */
460 static inline target_ulong
LI(uint32_t opcode
)
462 return (opcode
>> 0) & 0x03FFFFFC;
465 static inline uint32_t BD(uint32_t opcode
)
467 return (opcode
>> 0) & 0xFFFC;
470 EXTRACT_HELPER(BO
, 21, 5);
471 EXTRACT_HELPER(BI
, 16, 5);
472 /* Absolute/relative address */
473 EXTRACT_HELPER(AA
, 1, 1);
475 EXTRACT_HELPER(LK
, 0, 1);
478 EXTRACT_HELPER(DCM
, 10, 6)
481 EXTRACT_HELPER(RMC
, 9, 2)
483 /* Create a mask between <start> and <end> bits */
484 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
488 #if defined(TARGET_PPC64)
489 if (likely(start
== 0)) {
490 ret
= UINT64_MAX
<< (63 - end
);
491 } else if (likely(end
== 63)) {
492 ret
= UINT64_MAX
>> start
;
495 if (likely(start
== 0)) {
496 ret
= UINT32_MAX
<< (31 - end
);
497 } else if (likely(end
== 31)) {
498 ret
= UINT32_MAX
>> start
;
502 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
503 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
504 if (unlikely(start
> end
))
511 EXTRACT_HELPER_SPLIT(xT
, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xS
, 0, 1, 21, 5);
513 EXTRACT_HELPER_SPLIT(xA
, 2, 1, 16, 5);
514 EXTRACT_HELPER_SPLIT(xB
, 1, 1, 11, 5);
515 EXTRACT_HELPER_SPLIT(xC
, 3, 1, 6, 5);
516 EXTRACT_HELPER(DM
, 8, 2);
517 EXTRACT_HELPER(UIM
, 16, 2);
518 EXTRACT_HELPER(SHW
, 8, 2);
519 EXTRACT_HELPER(SP
, 19, 2);
520 /*****************************************************************************/
521 /* PowerPC instructions table */
523 #if defined(DO_PPC_STATISTICS)
524 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
537 .oname = stringify(name), \
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
550 .handler = &gen_##name, \
551 .oname = stringify(name), \
553 .oname = stringify(name), \
555 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
565 .handler = &gen_##name, \
571 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
581 .handler = &gen_##name, \
583 .oname = stringify(name), \
585 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
596 .handler = &gen_##name, \
598 .oname = stringify(name), \
600 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
610 .handler = &gen_##name, \
616 /* SPR load/store helpers */
617 static inline void gen_load_spr(TCGv t
, int reg
)
619 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
622 static inline void gen_store_spr(int reg
, TCGv t
)
624 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
627 /* Invalid instruction */
628 static void gen_invalid(DisasContext
*ctx
)
630 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
633 static opc_handler_t invalid_handler
= {
634 .inval1
= 0xFFFFFFFF,
635 .inval2
= 0xFFFFFFFF,
638 .handler
= gen_invalid
,
641 /*** Integer comparison ***/
643 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
645 TCGv t0
= tcg_temp_new();
646 TCGv_i32 t1
= tcg_temp_new_i32();
648 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
650 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
651 tcg_gen_trunc_tl_i32(t1
, t0
);
652 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
653 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
655 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
656 tcg_gen_trunc_tl_i32(t1
, t0
);
657 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
658 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
660 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
661 tcg_gen_trunc_tl_i32(t1
, t0
);
662 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
663 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
666 tcg_temp_free_i32(t1
);
669 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
671 TCGv t0
= tcg_const_tl(arg1
);
672 gen_op_cmp(arg0
, t0
, s
, crf
);
676 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
682 tcg_gen_ext32s_tl(t0
, arg0
);
683 tcg_gen_ext32s_tl(t1
, arg1
);
685 tcg_gen_ext32u_tl(t0
, arg0
);
686 tcg_gen_ext32u_tl(t1
, arg1
);
688 gen_op_cmp(t0
, t1
, s
, crf
);
693 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
695 TCGv t0
= tcg_const_tl(arg1
);
696 gen_op_cmp32(arg0
, t0
, s
, crf
);
700 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
702 if (NARROW_MODE(ctx
)) {
703 gen_op_cmpi32(reg
, 0, 1, 0);
705 gen_op_cmpi(reg
, 0, 1, 0);
710 static void gen_cmp(DisasContext
*ctx
)
712 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
713 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
714 1, crfD(ctx
->opcode
));
716 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
717 1, crfD(ctx
->opcode
));
722 static void gen_cmpi(DisasContext
*ctx
)
724 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
725 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
726 1, crfD(ctx
->opcode
));
728 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
729 1, crfD(ctx
->opcode
));
734 static void gen_cmpl(DisasContext
*ctx
)
736 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
737 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
738 0, crfD(ctx
->opcode
));
740 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
741 0, crfD(ctx
->opcode
));
746 static void gen_cmpli(DisasContext
*ctx
)
748 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
749 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
750 0, crfD(ctx
->opcode
));
752 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
753 0, crfD(ctx
->opcode
));
757 /* isel (PowerPC 2.03 specification) */
758 static void gen_isel(DisasContext
*ctx
)
760 uint32_t bi
= rC(ctx
->opcode
);
761 uint32_t mask
= 0x08 >> (bi
& 0x03);
762 TCGv t0
= tcg_temp_new();
765 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
766 tcg_gen_andi_tl(t0
, t0
, mask
);
768 zr
= tcg_const_tl(0);
769 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
770 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
771 cpu_gpr
[rB(ctx
->opcode
)]);
776 /* cmpb: PowerPC 2.05 specification */
777 static void gen_cmpb(DisasContext
*ctx
)
779 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
780 cpu_gpr
[rB(ctx
->opcode
)]);
783 /*** Integer arithmetic ***/
785 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
786 TCGv arg1
, TCGv arg2
, int sub
)
788 TCGv t0
= tcg_temp_new();
790 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
791 tcg_gen_xor_tl(t0
, arg1
, arg2
);
793 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
795 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
798 if (NARROW_MODE(ctx
)) {
799 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
801 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
802 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
805 /* Common add function */
806 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
807 TCGv arg2
, bool add_ca
, bool compute_ca
,
808 bool compute_ov
, bool compute_rc0
)
812 if (compute_ca
|| compute_ov
) {
817 if (NARROW_MODE(ctx
)) {
818 /* Caution: a non-obvious corner case of the spec is that we
819 must produce the *entire* 64-bit addition, but produce the
820 carry into bit 32. */
821 TCGv t1
= tcg_temp_new();
822 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
823 tcg_gen_add_tl(t0
, arg1
, arg2
);
825 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
827 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
829 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
830 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
832 TCGv zero
= tcg_const_tl(0);
834 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
835 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
837 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
842 tcg_gen_add_tl(t0
, arg1
, arg2
);
844 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
849 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
851 if (unlikely(compute_rc0
)) {
852 gen_set_Rc0(ctx
, t0
);
855 if (!TCGV_EQUAL(t0
, ret
)) {
856 tcg_gen_mov_tl(ret
, t0
);
860 /* Add functions with two operands */
861 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
864 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
865 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
866 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 /* Add functions with one operand and one immediate */
869 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
870 add_ca, compute_ca, compute_ov) \
871 static void glue(gen_, name)(DisasContext *ctx) \
873 TCGv t0 = tcg_const_tl(const_val); \
874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
875 cpu_gpr[rA(ctx->opcode)], t0, \
876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
880 /* add add. addo addo. */
881 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
882 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
883 /* addc addc. addco addco. */
884 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
885 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
886 /* adde adde. addeo addeo. */
887 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
888 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
889 /* addme addme. addmeo addmeo. */
890 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
891 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
892 /* addze addze. addzeo addzeo.*/
893 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
894 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
896 static void gen_addi(DisasContext
*ctx
)
898 target_long simm
= SIMM(ctx
->opcode
);
900 if (rA(ctx
->opcode
) == 0) {
902 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
904 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
905 cpu_gpr
[rA(ctx
->opcode
)], simm
);
909 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
911 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
912 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
913 c
, 0, 1, 0, compute_rc0
);
917 static void gen_addic(DisasContext
*ctx
)
919 gen_op_addic(ctx
, 0);
922 static void gen_addic_(DisasContext
*ctx
)
924 gen_op_addic(ctx
, 1);
928 static void gen_addis(DisasContext
*ctx
)
930 target_long simm
= SIMM(ctx
->opcode
);
932 if (rA(ctx
->opcode
) == 0) {
934 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
936 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
937 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
941 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
942 TCGv arg2
, int sign
, int compute_ov
)
944 TCGLabel
*l1
= gen_new_label();
945 TCGLabel
*l2
= gen_new_label();
946 TCGv_i32 t0
= tcg_temp_local_new_i32();
947 TCGv_i32 t1
= tcg_temp_local_new_i32();
949 tcg_gen_trunc_tl_i32(t0
, arg1
);
950 tcg_gen_trunc_tl_i32(t1
, arg2
);
951 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
953 TCGLabel
*l3
= gen_new_label();
954 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
955 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
957 tcg_gen_div_i32(t0
, t0
, t1
);
959 tcg_gen_divu_i32(t0
, t0
, t1
);
962 tcg_gen_movi_tl(cpu_ov
, 0);
967 tcg_gen_sari_i32(t0
, t0
, 31);
969 tcg_gen_movi_i32(t0
, 0);
972 tcg_gen_movi_tl(cpu_ov
, 1);
973 tcg_gen_movi_tl(cpu_so
, 1);
976 tcg_gen_extu_i32_tl(ret
, t0
);
977 tcg_temp_free_i32(t0
);
978 tcg_temp_free_i32(t1
);
979 if (unlikely(Rc(ctx
->opcode
) != 0))
980 gen_set_Rc0(ctx
, ret
);
983 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
984 static void glue(gen_, name)(DisasContext *ctx) \
986 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
990 /* divwu divwu. divwuo divwuo. */
991 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
992 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
993 /* divw divw. divwo divwo. */
994 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
995 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
997 /* div[wd]eu[o][.] */
998 #define GEN_DIVE(name, hlpr, compute_ov) \
999 static void gen_##name(DisasContext *ctx) \
1001 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1002 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1004 tcg_temp_free_i32(t0); \
1005 if (unlikely(Rc(ctx->opcode) != 0)) { \
1006 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1010 GEN_DIVE(divweu
, divweu
, 0);
1011 GEN_DIVE(divweuo
, divweu
, 1);
1012 GEN_DIVE(divwe
, divwe
, 0);
1013 GEN_DIVE(divweo
, divwe
, 1);
1015 #if defined(TARGET_PPC64)
1016 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1017 TCGv arg2
, int sign
, int compute_ov
)
1019 TCGLabel
*l1
= gen_new_label();
1020 TCGLabel
*l2
= gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1024 TCGLabel
*l3
= gen_new_label();
1025 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1026 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1028 tcg_gen_div_i64(ret
, arg1
, arg2
);
1030 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1033 tcg_gen_movi_tl(cpu_ov
, 0);
1038 tcg_gen_sari_i64(ret
, arg1
, 63);
1040 tcg_gen_movi_i64(ret
, 0);
1043 tcg_gen_movi_tl(cpu_ov
, 1);
1044 tcg_gen_movi_tl(cpu_so
, 1);
1047 if (unlikely(Rc(ctx
->opcode
) != 0))
1048 gen_set_Rc0(ctx
, ret
);
1050 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1051 static void glue(gen_, name)(DisasContext *ctx) \
1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
1057 /* divwu divwu. divwuo divwuo. */
1058 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1059 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1060 /* divw divw. divwo divwo. */
1061 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1062 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1064 GEN_DIVE(divdeu
, divdeu
, 0);
1065 GEN_DIVE(divdeuo
, divdeu
, 1);
1066 GEN_DIVE(divde
, divde
, 0);
1067 GEN_DIVE(divdeo
, divde
, 1);
1071 static void gen_mulhw(DisasContext
*ctx
)
1073 TCGv_i32 t0
= tcg_temp_new_i32();
1074 TCGv_i32 t1
= tcg_temp_new_i32();
1076 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1077 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1078 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1079 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1080 tcg_temp_free_i32(t0
);
1081 tcg_temp_free_i32(t1
);
1082 if (unlikely(Rc(ctx
->opcode
) != 0))
1083 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext
*ctx
)
1089 TCGv_i32 t0
= tcg_temp_new_i32();
1090 TCGv_i32 t1
= tcg_temp_new_i32();
1092 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1093 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1094 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1095 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1096 tcg_temp_free_i32(t0
);
1097 tcg_temp_free_i32(t1
);
1098 if (unlikely(Rc(ctx
->opcode
) != 0))
1099 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1103 static void gen_mullw(DisasContext
*ctx
)
1105 #if defined(TARGET_PPC64)
1107 t0
= tcg_temp_new_i64();
1108 t1
= tcg_temp_new_i64();
1109 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1110 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1111 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1115 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1116 cpu_gpr
[rB(ctx
->opcode
)]);
1118 if (unlikely(Rc(ctx
->opcode
) != 0))
1119 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1122 /* mullwo mullwo. */
1123 static void gen_mullwo(DisasContext
*ctx
)
1125 TCGv_i32 t0
= tcg_temp_new_i32();
1126 TCGv_i32 t1
= tcg_temp_new_i32();
1128 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1129 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1130 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1131 #if defined(TARGET_PPC64)
1132 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1134 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1137 tcg_gen_sari_i32(t0
, t0
, 31);
1138 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1139 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1140 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1142 tcg_temp_free_i32(t0
);
1143 tcg_temp_free_i32(t1
);
1144 if (unlikely(Rc(ctx
->opcode
) != 0))
1145 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1149 static void gen_mulli(DisasContext
*ctx
)
1151 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1155 #if defined(TARGET_PPC64)
1157 static void gen_mulhd(DisasContext
*ctx
)
1159 TCGv lo
= tcg_temp_new();
1160 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1161 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1163 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1164 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1168 /* mulhdu mulhdu. */
1169 static void gen_mulhdu(DisasContext
*ctx
)
1171 TCGv lo
= tcg_temp_new();
1172 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1173 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1175 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1176 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1181 static void gen_mulld(DisasContext
*ctx
)
1183 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1184 cpu_gpr
[rB(ctx
->opcode
)]);
1185 if (unlikely(Rc(ctx
->opcode
) != 0))
1186 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1189 /* mulldo mulldo. */
1190 static void gen_mulldo(DisasContext
*ctx
)
1192 TCGv_i64 t0
= tcg_temp_new_i64();
1193 TCGv_i64 t1
= tcg_temp_new_i64();
1195 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1196 cpu_gpr
[rB(ctx
->opcode
)]);
1197 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1199 tcg_gen_sari_i64(t0
, t0
, 63);
1200 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1201 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1203 tcg_temp_free_i64(t0
);
1204 tcg_temp_free_i64(t1
);
1206 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1207 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1212 /* Common subf function */
1213 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1214 TCGv arg2
, bool add_ca
, bool compute_ca
,
1215 bool compute_ov
, bool compute_rc0
)
1219 if (compute_ca
|| compute_ov
) {
1220 t0
= tcg_temp_new();
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx
)) {
1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
1229 TCGv inv1
= tcg_temp_new();
1230 TCGv t1
= tcg_temp_new();
1231 tcg_gen_not_tl(inv1
, arg1
);
1233 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1235 tcg_gen_addi_tl(t0
, arg2
, 1);
1237 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1238 tcg_gen_add_tl(t0
, t0
, inv1
);
1239 tcg_temp_free(inv1
);
1240 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1242 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1244 } else if (add_ca
) {
1245 TCGv zero
, inv1
= tcg_temp_new();
1246 tcg_gen_not_tl(inv1
, arg1
);
1247 zero
= tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1249 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1250 tcg_temp_free(zero
);
1251 tcg_temp_free(inv1
);
1253 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1254 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1256 } else if (add_ca
) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1260 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1261 tcg_gen_subi_tl(t0
, t0
, 1);
1263 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1267 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1269 if (unlikely(compute_rc0
)) {
1270 gen_set_Rc0(ctx
, t0
);
1273 if (!TCGV_EQUAL(t0
, ret
)) {
1274 tcg_gen_mov_tl(ret
, t0
);
1278 /* Sub functions with Two operands functions */
1279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1280 static void glue(gen_, name)(DisasContext *ctx) \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1286 /* Sub functions with one operand and one immediate */
1287 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
1289 static void glue(gen_, name)(DisasContext *ctx) \
1291 TCGv t0 = tcg_const_tl(const_val); \
1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1295 tcg_temp_free(t0); \
1297 /* subf subf. subfo subfo. */
1298 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1299 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1300 /* subfc subfc. subfco subfco. */
1301 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1303 /* subfe subfe. subfeo subfo. */
1304 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1306 /* subfme subfme. subfmeo subfmeo. */
1307 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1309 /* subfze subfze. subfzeo subfzeo.*/
1310 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1314 static void gen_subfic(DisasContext
*ctx
)
1316 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1317 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1322 /* neg neg. nego nego. */
1323 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1325 TCGv zero
= tcg_const_tl(0);
1326 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1327 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1328 tcg_temp_free(zero
);
1331 static void gen_neg(DisasContext
*ctx
)
1333 gen_op_arith_neg(ctx
, 0);
1336 static void gen_nego(DisasContext
*ctx
)
1338 gen_op_arith_neg(ctx
, 1);
1341 /*** Integer logical ***/
1342 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1343 static void glue(gen_, name)(DisasContext *ctx) \
1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
1347 if (unlikely(Rc(ctx->opcode) != 0)) \
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1351 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1352 static void glue(gen_, name)(DisasContext *ctx) \
1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1355 if (unlikely(Rc(ctx->opcode) != 0)) \
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1360 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1362 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1365 static void gen_andi_(DisasContext
*ctx
)
1367 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1368 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1372 static void gen_andis_(DisasContext
*ctx
)
1374 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1375 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1379 static void gen_cntlzw(DisasContext
*ctx
)
1381 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1382 if (unlikely(Rc(ctx
->opcode
) != 0))
1383 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1386 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1387 /* extsb & extsb. */
1388 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1389 /* extsh & extsh. */
1390 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1392 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1394 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1396 #if defined(TARGET_PPC64)
1397 static void gen_pause(DisasContext
*ctx
)
1399 TCGv_i32 t0
= tcg_const_i32(0);
1400 tcg_gen_st_i32(t0
, cpu_env
,
1401 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1402 tcg_temp_free_i32(t0
);
1404 /* Stop translation, this gives other CPUs a chance to run */
1405 gen_exception_err(ctx
, EXCP_HLT
, 1);
1407 #endif /* defined(TARGET_PPC64) */
1410 static void gen_or(DisasContext
*ctx
)
1414 rs
= rS(ctx
->opcode
);
1415 ra
= rA(ctx
->opcode
);
1416 rb
= rB(ctx
->opcode
);
1417 /* Optimisation for mr. ri case */
1418 if (rs
!= ra
|| rs
!= rb
) {
1420 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1422 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1423 if (unlikely(Rc(ctx
->opcode
) != 0))
1424 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1425 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1426 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1427 #if defined(TARGET_PPC64)
1433 /* Set process priority to low */
1437 /* Set process priority to medium-low */
1441 /* Set process priority to normal */
1444 #if !defined(CONFIG_USER_ONLY)
1447 /* Set process priority to very low */
1453 /* Set process priority to medium-hight */
1459 /* Set process priority to high */
1464 if (ctx
->hv
&& !ctx
->pr
) {
1465 /* Set process priority to very high */
1475 TCGv t0
= tcg_temp_new();
1476 gen_load_spr(t0
, SPR_PPR
);
1477 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1478 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1479 gen_store_spr(SPR_PPR
, t0
);
1481 /* Pause us out of TCG otherwise spin loops with smt_low
1482 * eat too much CPU and the kernel hangs
1490 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1493 static void gen_xor(DisasContext
*ctx
)
1495 /* Optimisation for "set to zero" case */
1496 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1497 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1499 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1500 if (unlikely(Rc(ctx
->opcode
) != 0))
1501 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1505 static void gen_ori(DisasContext
*ctx
)
1507 target_ulong uimm
= UIMM(ctx
->opcode
);
1509 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1512 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1516 static void gen_oris(DisasContext
*ctx
)
1518 target_ulong uimm
= UIMM(ctx
->opcode
);
1520 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1524 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1528 static void gen_xori(DisasContext
*ctx
)
1530 target_ulong uimm
= UIMM(ctx
->opcode
);
1532 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1536 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1540 static void gen_xoris(DisasContext
*ctx
)
1542 target_ulong uimm
= UIMM(ctx
->opcode
);
1544 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1548 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1551 /* popcntb : PowerPC 2.03 specification */
1552 static void gen_popcntb(DisasContext
*ctx
)
1554 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1557 static void gen_popcntw(DisasContext
*ctx
)
1559 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1562 #if defined(TARGET_PPC64)
1563 /* popcntd: PowerPC 2.06 specification */
1564 static void gen_popcntd(DisasContext
*ctx
)
1566 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1570 /* prtyw: PowerPC 2.05 specification */
1571 static void gen_prtyw(DisasContext
*ctx
)
1573 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1574 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1575 TCGv t0
= tcg_temp_new();
1576 tcg_gen_shri_tl(t0
, rs
, 16);
1577 tcg_gen_xor_tl(ra
, rs
, t0
);
1578 tcg_gen_shri_tl(t0
, ra
, 8);
1579 tcg_gen_xor_tl(ra
, ra
, t0
);
1580 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1584 #if defined(TARGET_PPC64)
1585 /* prtyd: PowerPC 2.05 specification */
1586 static void gen_prtyd(DisasContext
*ctx
)
1588 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1589 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1590 TCGv t0
= tcg_temp_new();
1591 tcg_gen_shri_tl(t0
, rs
, 32);
1592 tcg_gen_xor_tl(ra
, rs
, t0
);
1593 tcg_gen_shri_tl(t0
, ra
, 16);
1594 tcg_gen_xor_tl(ra
, ra
, t0
);
1595 tcg_gen_shri_tl(t0
, ra
, 8);
1596 tcg_gen_xor_tl(ra
, ra
, t0
);
1597 tcg_gen_andi_tl(ra
, ra
, 1);
1602 #if defined(TARGET_PPC64)
1604 static void gen_bpermd(DisasContext
*ctx
)
1606 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1607 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1611 #if defined(TARGET_PPC64)
1612 /* extsw & extsw. */
1613 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1616 static void gen_cntlzd(DisasContext
*ctx
)
1618 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1619 if (unlikely(Rc(ctx
->opcode
) != 0))
1620 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1624 /*** Integer rotate ***/
1626 /* rlwimi & rlwimi. */
1627 static void gen_rlwimi(DisasContext
*ctx
)
1629 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1630 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1631 uint32_t sh
= SH(ctx
->opcode
);
1632 uint32_t mb
= MB(ctx
->opcode
);
1633 uint32_t me
= ME(ctx
->opcode
);
1635 if (sh
== (31-me
) && mb
<= me
) {
1636 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1641 #if defined(TARGET_PPC64)
1645 mask
= MASK(mb
, me
);
1647 t1
= tcg_temp_new();
1648 if (mask
<= 0xffffffffu
) {
1649 TCGv_i32 t0
= tcg_temp_new_i32();
1650 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1651 tcg_gen_rotli_i32(t0
, t0
, sh
);
1652 tcg_gen_extu_i32_tl(t1
, t0
);
1653 tcg_temp_free_i32(t0
);
1655 #if defined(TARGET_PPC64)
1656 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1657 tcg_gen_rotli_i64(t1
, t1
, sh
);
1659 g_assert_not_reached();
1663 tcg_gen_andi_tl(t1
, t1
, mask
);
1664 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1665 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1668 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1669 gen_set_Rc0(ctx
, t_ra
);
1673 /* rlwinm & rlwinm. */
1674 static void gen_rlwinm(DisasContext
*ctx
)
1676 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1677 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1678 uint32_t sh
= SH(ctx
->opcode
);
1679 uint32_t mb
= MB(ctx
->opcode
);
1680 uint32_t me
= ME(ctx
->opcode
);
1682 if (mb
== 0 && me
== (31 - sh
)) {
1683 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
1684 tcg_gen_ext32u_tl(t_ra
, t_ra
);
1685 } else if (sh
!= 0 && me
== 31 && sh
== (32 - mb
)) {
1686 tcg_gen_ext32u_tl(t_ra
, t_rs
);
1687 tcg_gen_shri_tl(t_ra
, t_ra
, mb
);
1690 #if defined(TARGET_PPC64)
1694 mask
= MASK(mb
, me
);
1697 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1698 } else if (mask
<= 0xffffffffu
) {
1699 TCGv_i32 t0
= tcg_temp_new_i32();
1700 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1701 tcg_gen_rotli_i32(t0
, t0
, sh
);
1702 tcg_gen_andi_i32(t0
, t0
, mask
);
1703 tcg_gen_extu_i32_tl(t_ra
, t0
);
1704 tcg_temp_free_i32(t0
);
1706 #if defined(TARGET_PPC64)
1707 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1708 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1709 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1711 g_assert_not_reached();
1715 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1716 gen_set_Rc0(ctx
, t_ra
);
1720 /* rlwnm & rlwnm. */
1721 static void gen_rlwnm(DisasContext
*ctx
)
1723 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1724 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1725 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1726 uint32_t mb
= MB(ctx
->opcode
);
1727 uint32_t me
= ME(ctx
->opcode
);
1730 #if defined(TARGET_PPC64)
1734 mask
= MASK(mb
, me
);
1736 if (mask
<= 0xffffffffu
) {
1737 TCGv_i32 t0
= tcg_temp_new_i32();
1738 TCGv_i32 t1
= tcg_temp_new_i32();
1739 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1740 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1741 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1742 tcg_gen_rotl_i32(t1
, t1
, t0
);
1743 tcg_gen_extu_i32_tl(t_ra
, t1
);
1744 tcg_temp_free_i32(t0
);
1745 tcg_temp_free_i32(t1
);
1747 #if defined(TARGET_PPC64)
1748 TCGv_i64 t0
= tcg_temp_new_i64();
1749 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1750 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1751 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1752 tcg_temp_free_i64(t0
);
1754 g_assert_not_reached();
1758 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1760 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1761 gen_set_Rc0(ctx
, t_ra
);
1765 #if defined(TARGET_PPC64)
1766 #define GEN_PPC64_R2(name, opc1, opc2) \
1767 static void glue(gen_, name##0)(DisasContext *ctx) \
1769 gen_##name(ctx, 0); \
1772 static void glue(gen_, name##1)(DisasContext *ctx) \
1774 gen_##name(ctx, 1); \
1776 #define GEN_PPC64_R4(name, opc1, opc2) \
1777 static void glue(gen_, name##0)(DisasContext *ctx) \
1779 gen_##name(ctx, 0, 0); \
1782 static void glue(gen_, name##1)(DisasContext *ctx) \
1784 gen_##name(ctx, 0, 1); \
1787 static void glue(gen_, name##2)(DisasContext *ctx) \
1789 gen_##name(ctx, 1, 0); \
1792 static void glue(gen_, name##3)(DisasContext *ctx) \
1794 gen_##name(ctx, 1, 1); \
1797 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
1799 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1800 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1802 if (sh
!= 0 && mb
== 0 && me
== (63 - sh
)) {
1803 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
1804 } else if (sh
!= 0 && me
== 63 && sh
== (64 - mb
)) {
1805 tcg_gen_shri_tl(t_ra
, t_rs
, mb
);
1807 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
1808 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
1810 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1811 gen_set_Rc0(ctx
, t_ra
);
1815 /* rldicl - rldicl. */
1816 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1820 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1821 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1822 gen_rldinm(ctx
, mb
, 63, sh
);
1824 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1826 /* rldicr - rldicr. */
1827 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1831 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1832 me
= MB(ctx
->opcode
) | (men
<< 5);
1833 gen_rldinm(ctx
, 0, me
, sh
);
1835 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1837 /* rldic - rldic. */
1838 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1842 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1843 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1844 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1846 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1848 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
1850 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1851 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1852 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1855 t0
= tcg_temp_new();
1856 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
1857 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
1860 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
1861 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1862 gen_set_Rc0(ctx
, t_ra
);
1866 /* rldcl - rldcl. */
1867 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1871 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1872 gen_rldnm(ctx
, mb
, 63);
1874 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1876 /* rldcr - rldcr. */
1877 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1881 me
= MB(ctx
->opcode
) | (men
<< 5);
1882 gen_rldnm(ctx
, 0, me
);
1884 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1886 /* rldimi - rldimi. */
1887 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1889 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1890 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1891 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
1892 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1893 uint32_t me
= 63 - sh
;
1896 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1898 target_ulong mask
= MASK(mb
, me
);
1899 TCGv t1
= tcg_temp_new();
1901 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
1902 tcg_gen_andi_tl(t1
, t1
, mask
);
1903 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1904 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1907 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1908 gen_set_Rc0(ctx
, t_ra
);
1911 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1914 /*** Integer shift ***/
1917 static void gen_slw(DisasContext
*ctx
)
1921 t0
= tcg_temp_new();
1922 /* AND rS with a mask that is 0 when rB >= 0x20 */
1923 #if defined(TARGET_PPC64)
1924 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1925 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1927 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1928 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1930 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1931 t1
= tcg_temp_new();
1932 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1933 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1936 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1937 if (unlikely(Rc(ctx
->opcode
) != 0))
1938 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1942 static void gen_sraw(DisasContext
*ctx
)
1944 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1945 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1946 if (unlikely(Rc(ctx
->opcode
) != 0))
1947 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1950 /* srawi & srawi. */
1951 static void gen_srawi(DisasContext
*ctx
)
1953 int sh
= SH(ctx
->opcode
);
1954 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1955 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1957 tcg_gen_ext32s_tl(dst
, src
);
1958 tcg_gen_movi_tl(cpu_ca
, 0);
1961 tcg_gen_ext32s_tl(dst
, src
);
1962 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
1963 t0
= tcg_temp_new();
1964 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
1965 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
1967 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
1968 tcg_gen_sari_tl(dst
, dst
, sh
);
1970 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1971 gen_set_Rc0(ctx
, dst
);
1976 static void gen_srw(DisasContext
*ctx
)
1980 t0
= tcg_temp_new();
1981 /* AND rS with a mask that is 0 when rB >= 0x20 */
1982 #if defined(TARGET_PPC64)
1983 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1984 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1986 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1987 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1989 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1990 tcg_gen_ext32u_tl(t0
, t0
);
1991 t1
= tcg_temp_new();
1992 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1993 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1996 if (unlikely(Rc(ctx
->opcode
) != 0))
1997 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2000 #if defined(TARGET_PPC64)
2002 static void gen_sld(DisasContext
*ctx
)
2006 t0
= tcg_temp_new();
2007 /* AND rS with a mask that is 0 when rB >= 0x40 */
2008 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2009 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2010 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2011 t1
= tcg_temp_new();
2012 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2013 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2016 if (unlikely(Rc(ctx
->opcode
) != 0))
2017 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2021 static void gen_srad(DisasContext
*ctx
)
2023 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2024 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2025 if (unlikely(Rc(ctx
->opcode
) != 0))
2026 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2028 /* sradi & sradi. */
2029 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2031 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2032 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2033 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2035 tcg_gen_mov_tl(dst
, src
);
2036 tcg_gen_movi_tl(cpu_ca
, 0);
2039 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2040 t0
= tcg_temp_new();
2041 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2042 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2044 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2045 tcg_gen_sari_tl(dst
, src
, sh
);
2047 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2048 gen_set_Rc0(ctx
, dst
);
2052 static void gen_sradi0(DisasContext
*ctx
)
2057 static void gen_sradi1(DisasContext
*ctx
)
2063 static void gen_srd(DisasContext
*ctx
)
2067 t0
= tcg_temp_new();
2068 /* AND rS with a mask that is 0 when rB >= 0x40 */
2069 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2070 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2071 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2072 t1
= tcg_temp_new();
2073 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2074 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2077 if (unlikely(Rc(ctx
->opcode
) != 0))
2078 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2082 #if defined(TARGET_PPC64)
2083 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2085 TCGv_i32 tmp
= tcg_temp_new_i32();
2086 tcg_gen_trunc_tl_i32(tmp
, cpu_fpscr
);
2087 tcg_gen_shri_i32(cpu_crf
[1], tmp
, 28);
2088 tcg_temp_free_i32(tmp
);
2091 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2093 tcg_gen_shri_tl(cpu_crf
[1], cpu_fpscr
, 28);
2097 /*** Floating-Point arithmetic ***/
2098 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2099 static void gen_f##name(DisasContext *ctx) \
2101 if (unlikely(!ctx->fpu_enabled)) { \
2102 gen_exception(ctx, POWERPC_EXCP_FPU); \
2105 /* NIP cannot be restored if the memory exception comes from an helper */ \
2106 gen_update_nip(ctx, ctx->nip - 4); \
2107 gen_reset_fpstatus(); \
2108 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2109 cpu_fpr[rA(ctx->opcode)], \
2110 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2112 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2113 cpu_fpr[rD(ctx->opcode)]); \
2116 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2118 if (unlikely(Rc(ctx->opcode) != 0)) { \
2119 gen_set_cr1_from_fpscr(ctx); \
2123 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2124 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2125 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2127 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2128 static void gen_f##name(DisasContext *ctx) \
2130 if (unlikely(!ctx->fpu_enabled)) { \
2131 gen_exception(ctx, POWERPC_EXCP_FPU); \
2134 /* NIP cannot be restored if the memory exception comes from an helper */ \
2135 gen_update_nip(ctx, ctx->nip - 4); \
2136 gen_reset_fpstatus(); \
2137 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2138 cpu_fpr[rA(ctx->opcode)], \
2139 cpu_fpr[rB(ctx->opcode)]); \
2141 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2142 cpu_fpr[rD(ctx->opcode)]); \
2145 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2147 if (unlikely(Rc(ctx->opcode) != 0)) { \
2148 gen_set_cr1_from_fpscr(ctx); \
2151 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2152 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2153 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2155 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2156 static void gen_f##name(DisasContext *ctx) \
2158 if (unlikely(!ctx->fpu_enabled)) { \
2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
2164 gen_reset_fpstatus(); \
2165 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2166 cpu_fpr[rA(ctx->opcode)], \
2167 cpu_fpr[rC(ctx->opcode)]); \
2169 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2170 cpu_fpr[rD(ctx->opcode)]); \
2173 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2175 if (unlikely(Rc(ctx->opcode) != 0)) { \
2176 gen_set_cr1_from_fpscr(ctx); \
2179 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2180 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2181 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2183 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2184 static void gen_f##name(DisasContext *ctx) \
2186 if (unlikely(!ctx->fpu_enabled)) { \
2187 gen_exception(ctx, POWERPC_EXCP_FPU); \
2190 /* NIP cannot be restored if the memory exception comes from an helper */ \
2191 gen_update_nip(ctx, ctx->nip - 4); \
2192 gen_reset_fpstatus(); \
2193 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2194 cpu_fpr[rB(ctx->opcode)]); \
2196 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2198 if (unlikely(Rc(ctx->opcode) != 0)) { \
2199 gen_set_cr1_from_fpscr(ctx); \
2203 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2204 static void gen_f##name(DisasContext *ctx) \
2206 if (unlikely(!ctx->fpu_enabled)) { \
2207 gen_exception(ctx, POWERPC_EXCP_FPU); \
2210 /* NIP cannot be restored if the memory exception comes from an helper */ \
2211 gen_update_nip(ctx, ctx->nip - 4); \
2212 gen_reset_fpstatus(); \
2213 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2214 cpu_fpr[rB(ctx->opcode)]); \
2216 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2218 if (unlikely(Rc(ctx->opcode) != 0)) { \
2219 gen_set_cr1_from_fpscr(ctx); \
2224 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2226 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2228 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2231 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2234 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2237 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2240 static void gen_frsqrtes(DisasContext
*ctx
)
2242 if (unlikely(!ctx
->fpu_enabled
)) {
2243 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2246 /* NIP cannot be restored if the memory exception comes from an helper */
2247 gen_update_nip(ctx
, ctx
->nip
- 4);
2248 gen_reset_fpstatus();
2249 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2250 cpu_fpr
[rB(ctx
->opcode
)]);
2251 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2252 cpu_fpr
[rD(ctx
->opcode
)]);
2253 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2254 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2255 gen_set_cr1_from_fpscr(ctx
);
2260 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2262 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2266 static void gen_fsqrt(DisasContext
*ctx
)
2268 if (unlikely(!ctx
->fpu_enabled
)) {
2269 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2272 /* NIP cannot be restored if the memory exception comes from an helper */
2273 gen_update_nip(ctx
, ctx
->nip
- 4);
2274 gen_reset_fpstatus();
2275 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2276 cpu_fpr
[rB(ctx
->opcode
)]);
2277 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2278 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2279 gen_set_cr1_from_fpscr(ctx
);
2283 static void gen_fsqrts(DisasContext
*ctx
)
2285 if (unlikely(!ctx
->fpu_enabled
)) {
2286 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2289 /* NIP cannot be restored if the memory exception comes from an helper */
2290 gen_update_nip(ctx
, ctx
->nip
- 4);
2291 gen_reset_fpstatus();
2292 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2293 cpu_fpr
[rB(ctx
->opcode
)]);
2294 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2295 cpu_fpr
[rD(ctx
->opcode
)]);
2296 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2297 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2298 gen_set_cr1_from_fpscr(ctx
);
2302 /*** Floating-Point multiply-and-add ***/
2303 /* fmadd - fmadds */
2304 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2305 /* fmsub - fmsubs */
2306 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2307 /* fnmadd - fnmadds */
2308 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2309 /* fnmsub - fnmsubs */
2310 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2312 /*** Floating-Point round & convert ***/
2314 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2316 GEN_FLOAT_B(ctiwu
, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206
);
2318 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2320 GEN_FLOAT_B(ctiwuz
, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206
);
2322 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2324 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64
);
2326 GEN_FLOAT_B(cfids
, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206
);
2328 GEN_FLOAT_B(cfidu
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2330 GEN_FLOAT_B(cfidus
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2332 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC2_FP_CVT_S64
);
2334 GEN_FLOAT_B(ctidu
, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2336 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC2_FP_CVT_S64
);
2338 GEN_FLOAT_B(ctiduz
, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2341 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2343 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2345 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2347 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2349 static void gen_ftdiv(DisasContext
*ctx
)
2351 if (unlikely(!ctx
->fpu_enabled
)) {
2352 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2355 gen_helper_ftdiv(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2356 cpu_fpr
[rB(ctx
->opcode
)]);
2359 static void gen_ftsqrt(DisasContext
*ctx
)
2361 if (unlikely(!ctx
->fpu_enabled
)) {
2362 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2365 gen_helper_ftsqrt(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2370 /*** Floating-Point compare ***/
2373 static void gen_fcmpo(DisasContext
*ctx
)
2376 if (unlikely(!ctx
->fpu_enabled
)) {
2377 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2380 /* NIP cannot be restored if the memory exception comes from an helper */
2381 gen_update_nip(ctx
, ctx
->nip
- 4);
2382 gen_reset_fpstatus();
2383 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2384 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2385 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2386 tcg_temp_free_i32(crf
);
2387 gen_helper_float_check_status(cpu_env
);
2391 static void gen_fcmpu(DisasContext
*ctx
)
2394 if (unlikely(!ctx
->fpu_enabled
)) {
2395 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2398 /* NIP cannot be restored if the memory exception comes from an helper */
2399 gen_update_nip(ctx
, ctx
->nip
- 4);
2400 gen_reset_fpstatus();
2401 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2402 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2403 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2404 tcg_temp_free_i32(crf
);
2405 gen_helper_float_check_status(cpu_env
);
2408 /*** Floating-point move ***/
2410 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2411 static void gen_fabs(DisasContext
*ctx
)
2413 if (unlikely(!ctx
->fpu_enabled
)) {
2414 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2417 tcg_gen_andi_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2419 if (unlikely(Rc(ctx
->opcode
))) {
2420 gen_set_cr1_from_fpscr(ctx
);
2425 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2426 static void gen_fmr(DisasContext
*ctx
)
2428 if (unlikely(!ctx
->fpu_enabled
)) {
2429 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2432 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2433 if (unlikely(Rc(ctx
->opcode
))) {
2434 gen_set_cr1_from_fpscr(ctx
);
2439 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2440 static void gen_fnabs(DisasContext
*ctx
)
2442 if (unlikely(!ctx
->fpu_enabled
)) {
2443 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2446 tcg_gen_ori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2448 if (unlikely(Rc(ctx
->opcode
))) {
2449 gen_set_cr1_from_fpscr(ctx
);
2454 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2455 static void gen_fneg(DisasContext
*ctx
)
2457 if (unlikely(!ctx
->fpu_enabled
)) {
2458 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2461 tcg_gen_xori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2463 if (unlikely(Rc(ctx
->opcode
))) {
2464 gen_set_cr1_from_fpscr(ctx
);
2468 /* fcpsgn: PowerPC 2.05 specification */
2469 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2470 static void gen_fcpsgn(DisasContext
*ctx
)
2472 if (unlikely(!ctx
->fpu_enabled
)) {
2473 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2476 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2477 cpu_fpr
[rB(ctx
->opcode
)], 0, 63);
2478 if (unlikely(Rc(ctx
->opcode
))) {
2479 gen_set_cr1_from_fpscr(ctx
);
2483 static void gen_fmrgew(DisasContext
*ctx
)
2486 if (unlikely(!ctx
->fpu_enabled
)) {
2487 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2490 b0
= tcg_temp_new_i64();
2491 tcg_gen_shri_i64(b0
, cpu_fpr
[rB(ctx
->opcode
)], 32);
2492 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2494 tcg_temp_free_i64(b0
);
2497 static void gen_fmrgow(DisasContext
*ctx
)
2499 if (unlikely(!ctx
->fpu_enabled
)) {
2500 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2503 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)],
2504 cpu_fpr
[rB(ctx
->opcode
)],
2505 cpu_fpr
[rA(ctx
->opcode
)],
2509 /*** Floating-Point status & ctrl register ***/
2512 static void gen_mcrfs(DisasContext
*ctx
)
2514 TCGv tmp
= tcg_temp_new();
2516 TCGv_i64 tnew_fpscr
= tcg_temp_new_i64();
2521 if (unlikely(!ctx
->fpu_enabled
)) {
2522 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2525 bfa
= crfS(ctx
->opcode
);
2528 tcg_gen_shri_tl(tmp
, cpu_fpscr
, shift
);
2529 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2530 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2532 tcg_gen_extu_tl_i64(tnew_fpscr
, cpu_fpscr
);
2533 /* Only the exception bits (including FX) should be cleared if read */
2534 tcg_gen_andi_i64(tnew_fpscr
, tnew_fpscr
, ~((0xF << shift
) & FP_EX_CLEAR_BITS
));
2535 /* FEX and VX need to be updated, so don't set fpscr directly */
2536 tmask
= tcg_const_i32(1 << nibble
);
2537 gen_helper_store_fpscr(cpu_env
, tnew_fpscr
, tmask
);
2538 tcg_temp_free_i32(tmask
);
2539 tcg_temp_free_i64(tnew_fpscr
);
2543 static void gen_mffs(DisasContext
*ctx
)
2545 if (unlikely(!ctx
->fpu_enabled
)) {
2546 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2549 gen_reset_fpstatus();
2550 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2551 if (unlikely(Rc(ctx
->opcode
))) {
2552 gen_set_cr1_from_fpscr(ctx
);
2557 static void gen_mtfsb0(DisasContext
*ctx
)
2561 if (unlikely(!ctx
->fpu_enabled
)) {
2562 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2565 crb
= 31 - crbD(ctx
->opcode
);
2566 gen_reset_fpstatus();
2567 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2569 /* NIP cannot be restored if the memory exception comes from an helper */
2570 gen_update_nip(ctx
, ctx
->nip
- 4);
2571 t0
= tcg_const_i32(crb
);
2572 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2573 tcg_temp_free_i32(t0
);
2575 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2576 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2577 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2582 static void gen_mtfsb1(DisasContext
*ctx
)
2586 if (unlikely(!ctx
->fpu_enabled
)) {
2587 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2590 crb
= 31 - crbD(ctx
->opcode
);
2591 gen_reset_fpstatus();
2592 /* XXX: we pretend we can only do IEEE floating-point computations */
2593 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2595 /* NIP cannot be restored if the memory exception comes from an helper */
2596 gen_update_nip(ctx
, ctx
->nip
- 4);
2597 t0
= tcg_const_i32(crb
);
2598 gen_helper_fpscr_setbit(cpu_env
, t0
);
2599 tcg_temp_free_i32(t0
);
2601 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2602 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2603 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2605 /* We can raise a differed exception */
2606 gen_helper_float_check_status(cpu_env
);
2610 static void gen_mtfsf(DisasContext
*ctx
)
2615 if (unlikely(!ctx
->fpu_enabled
)) {
2616 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2619 flm
= FPFLM(ctx
->opcode
);
2620 l
= FPL(ctx
->opcode
);
2621 w
= FPW(ctx
->opcode
);
2622 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2623 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2626 /* NIP cannot be restored if the memory exception comes from an helper */
2627 gen_update_nip(ctx
, ctx
->nip
- 4);
2628 gen_reset_fpstatus();
2630 t0
= tcg_const_i32((ctx
->insns_flags2
& PPC2_ISA205
) ? 0xffff : 0xff);
2632 t0
= tcg_const_i32(flm
<< (w
* 8));
2634 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2635 tcg_temp_free_i32(t0
);
2636 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2637 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2638 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2640 /* We can raise a differed exception */
2641 gen_helper_float_check_status(cpu_env
);
2645 static void gen_mtfsfi(DisasContext
*ctx
)
2651 if (unlikely(!ctx
->fpu_enabled
)) {
2652 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2655 w
= FPW(ctx
->opcode
);
2656 bf
= FPBF(ctx
->opcode
);
2657 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2658 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2661 sh
= (8 * w
) + 7 - bf
;
2662 /* NIP cannot be restored if the memory exception comes from an helper */
2663 gen_update_nip(ctx
, ctx
->nip
- 4);
2664 gen_reset_fpstatus();
2665 t0
= tcg_const_i64(((uint64_t)FPIMM(ctx
->opcode
)) << (4 * sh
));
2666 t1
= tcg_const_i32(1 << sh
);
2667 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2668 tcg_temp_free_i64(t0
);
2669 tcg_temp_free_i32(t1
);
2670 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2671 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2672 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2674 /* We can raise a differed exception */
2675 gen_helper_float_check_status(cpu_env
);
2678 /*** Addressing modes ***/
2679 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2680 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2683 target_long simm
= SIMM(ctx
->opcode
);
2686 if (rA(ctx
->opcode
) == 0) {
2687 if (NARROW_MODE(ctx
)) {
2688 simm
= (uint32_t)simm
;
2690 tcg_gen_movi_tl(EA
, simm
);
2691 } else if (likely(simm
!= 0)) {
2692 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2693 if (NARROW_MODE(ctx
)) {
2694 tcg_gen_ext32u_tl(EA
, EA
);
2697 if (NARROW_MODE(ctx
)) {
2698 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2700 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2705 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2707 if (rA(ctx
->opcode
) == 0) {
2708 if (NARROW_MODE(ctx
)) {
2709 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2711 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2714 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2715 if (NARROW_MODE(ctx
)) {
2716 tcg_gen_ext32u_tl(EA
, EA
);
2721 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2723 if (rA(ctx
->opcode
) == 0) {
2724 tcg_gen_movi_tl(EA
, 0);
2725 } else if (NARROW_MODE(ctx
)) {
2726 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2728 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2732 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2735 tcg_gen_addi_tl(ret
, arg1
, val
);
2736 if (NARROW_MODE(ctx
)) {
2737 tcg_gen_ext32u_tl(ret
, ret
);
2741 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2743 TCGLabel
*l1
= gen_new_label();
2744 TCGv t0
= tcg_temp_new();
2746 /* NIP cannot be restored if the memory exception comes from an helper */
2747 gen_update_nip(ctx
, ctx
->nip
- 4);
2748 tcg_gen_andi_tl(t0
, EA
, mask
);
2749 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2750 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2751 t2
= tcg_const_i32(0);
2752 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2753 tcg_temp_free_i32(t1
);
2754 tcg_temp_free_i32(t2
);
2759 /*** Integer load ***/
2760 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2762 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2765 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2767 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2768 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2771 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2773 TCGMemOp op
= MO_SW
| ctx
->default_tcg_memop_mask
;
2774 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2777 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2779 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2780 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2783 static void gen_qemu_ld32u_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2785 TCGv tmp
= tcg_temp_new();
2786 gen_qemu_ld32u(ctx
, tmp
, addr
);
2787 tcg_gen_extu_tl_i64(val
, tmp
);
2791 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2793 TCGMemOp op
= MO_SL
| ctx
->default_tcg_memop_mask
;
2794 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2797 static void gen_qemu_ld32s_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2799 TCGv tmp
= tcg_temp_new();
2800 gen_qemu_ld32s(ctx
, tmp
, addr
);
2801 tcg_gen_ext_tl_i64(val
, tmp
);
2805 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2807 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2808 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2811 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2813 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2816 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2818 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2819 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2822 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2824 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2825 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2828 static void gen_qemu_st32_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2830 TCGv tmp
= tcg_temp_new();
2831 tcg_gen_trunc_i64_tl(tmp
, val
);
2832 gen_qemu_st32(ctx
, tmp
, addr
);
2836 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2838 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2839 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2842 #define GEN_LD(name, ldop, opc, type) \
2843 static void glue(gen_, name)(DisasContext *ctx) \
2846 gen_set_access_type(ctx, ACCESS_INT); \
2847 EA = tcg_temp_new(); \
2848 gen_addr_imm_index(ctx, EA, 0); \
2849 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2850 tcg_temp_free(EA); \
2853 #define GEN_LDU(name, ldop, opc, type) \
2854 static void glue(gen_, name##u)(DisasContext *ctx) \
2857 if (unlikely(rA(ctx->opcode) == 0 || \
2858 rA(ctx->opcode) == rD(ctx->opcode))) { \
2859 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2862 gen_set_access_type(ctx, ACCESS_INT); \
2863 EA = tcg_temp_new(); \
2864 if (type == PPC_64B) \
2865 gen_addr_imm_index(ctx, EA, 0x03); \
2867 gen_addr_imm_index(ctx, EA, 0); \
2868 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2869 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2870 tcg_temp_free(EA); \
2873 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2874 static void glue(gen_, name##ux)(DisasContext *ctx) \
2877 if (unlikely(rA(ctx->opcode) == 0 || \
2878 rA(ctx->opcode) == rD(ctx->opcode))) { \
2879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2882 gen_set_access_type(ctx, ACCESS_INT); \
2883 EA = tcg_temp_new(); \
2884 gen_addr_reg_index(ctx, EA); \
2885 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2886 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2887 tcg_temp_free(EA); \
2890 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2891 static void glue(gen_, name##x)(DisasContext *ctx) \
2894 gen_set_access_type(ctx, ACCESS_INT); \
2895 EA = tcg_temp_new(); \
2896 gen_addr_reg_index(ctx, EA); \
2897 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2898 tcg_temp_free(EA); \
2900 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2901 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2903 #define GEN_LDS(name, ldop, op, type) \
2904 GEN_LD(name, ldop, op | 0x20, type); \
2905 GEN_LDU(name, ldop, op | 0x21, type); \
2906 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2907 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2909 /* lbz lbzu lbzux lbzx */
2910 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2911 /* lha lhau lhaux lhax */
2912 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2913 /* lhz lhzu lhzux lhzx */
2914 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2915 /* lwz lwzu lwzux lwzx */
2916 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2917 #if defined(TARGET_PPC64)
2919 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2921 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2923 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2925 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2927 static void gen_ld(DisasContext
*ctx
)
2930 if (Rc(ctx
->opcode
)) {
2931 if (unlikely(rA(ctx
->opcode
) == 0 ||
2932 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2933 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2937 gen_set_access_type(ctx
, ACCESS_INT
);
2938 EA
= tcg_temp_new();
2939 gen_addr_imm_index(ctx
, EA
, 0x03);
2940 if (ctx
->opcode
& 0x02) {
2941 /* lwa (lwau is undefined) */
2942 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2945 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2947 if (Rc(ctx
->opcode
))
2948 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2953 static void gen_lq(DisasContext
*ctx
)
2958 /* lq is a legal user mode instruction starting in ISA 2.07 */
2959 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2960 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2962 if (!legal_in_user_mode
&& ctx
->pr
) {
2963 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2967 if (!le_is_supported
&& ctx
->le_mode
) {
2968 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
2972 ra
= rA(ctx
->opcode
);
2973 rd
= rD(ctx
->opcode
);
2974 if (unlikely((rd
& 1) || rd
== ra
)) {
2975 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2979 gen_set_access_type(ctx
, ACCESS_INT
);
2980 EA
= tcg_temp_new();
2981 gen_addr_imm_index(ctx
, EA
, 0x0F);
2983 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2984 64-bit byteswap already. */
2985 if (unlikely(ctx
->le_mode
)) {
2986 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2987 gen_addr_add(ctx
, EA
, EA
, 8);
2988 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2990 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
2991 gen_addr_add(ctx
, EA
, EA
, 8);
2992 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
2998 /*** Integer store ***/
2999 #define GEN_ST(name, stop, opc, type) \
3000 static void glue(gen_, name)(DisasContext *ctx) \
3003 gen_set_access_type(ctx, ACCESS_INT); \
3004 EA = tcg_temp_new(); \
3005 gen_addr_imm_index(ctx, EA, 0); \
3006 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3007 tcg_temp_free(EA); \
3010 #define GEN_STU(name, stop, opc, type) \
3011 static void glue(gen_, stop##u)(DisasContext *ctx) \
3014 if (unlikely(rA(ctx->opcode) == 0)) { \
3015 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3018 gen_set_access_type(ctx, ACCESS_INT); \
3019 EA = tcg_temp_new(); \
3020 if (type == PPC_64B) \
3021 gen_addr_imm_index(ctx, EA, 0x03); \
3023 gen_addr_imm_index(ctx, EA, 0); \
3024 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3025 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3026 tcg_temp_free(EA); \
3029 #define GEN_STUX(name, stop, opc2, opc3, type) \
3030 static void glue(gen_, name##ux)(DisasContext *ctx) \
3033 if (unlikely(rA(ctx->opcode) == 0)) { \
3034 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3037 gen_set_access_type(ctx, ACCESS_INT); \
3038 EA = tcg_temp_new(); \
3039 gen_addr_reg_index(ctx, EA); \
3040 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3041 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3042 tcg_temp_free(EA); \
3045 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3046 static void glue(gen_, name##x)(DisasContext *ctx) \
3049 gen_set_access_type(ctx, ACCESS_INT); \
3050 EA = tcg_temp_new(); \
3051 gen_addr_reg_index(ctx, EA); \
3052 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3053 tcg_temp_free(EA); \
3055 #define GEN_STX(name, stop, opc2, opc3, type) \
3056 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3058 #define GEN_STS(name, stop, op, type) \
3059 GEN_ST(name, stop, op | 0x20, type); \
3060 GEN_STU(name, stop, op | 0x21, type); \
3061 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3062 GEN_STX(name, stop, 0x17, op | 0x00, type)
3064 /* stb stbu stbux stbx */
3065 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
3066 /* sth sthu sthux sthx */
3067 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
3068 /* stw stwu stwux stwx */
3069 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
3070 #if defined(TARGET_PPC64)
3071 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
3072 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
3074 static void gen_std(DisasContext
*ctx
)
3079 rs
= rS(ctx
->opcode
);
3080 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
3081 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3082 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3084 if (!(ctx
->insns_flags
& PPC_64BX
)) {
3085 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3088 if (!legal_in_user_mode
&& ctx
->pr
) {
3089 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3093 if (!le_is_supported
&& ctx
->le_mode
) {
3094 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
3098 if (unlikely(rs
& 1)) {
3099 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3102 gen_set_access_type(ctx
, ACCESS_INT
);
3103 EA
= tcg_temp_new();
3104 gen_addr_imm_index(ctx
, EA
, 0x03);
3106 /* We only need to swap high and low halves. gen_qemu_st64 does
3107 necessary 64-bit byteswap already. */
3108 if (unlikely(ctx
->le_mode
)) {
3109 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3110 gen_addr_add(ctx
, EA
, EA
, 8);
3111 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3113 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3114 gen_addr_add(ctx
, EA
, EA
, 8);
3115 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3120 if (Rc(ctx
->opcode
)) {
3121 if (unlikely(rA(ctx
->opcode
) == 0)) {
3122 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3126 gen_set_access_type(ctx
, ACCESS_INT
);
3127 EA
= tcg_temp_new();
3128 gen_addr_imm_index(ctx
, EA
, 0x03);
3129 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3130 if (Rc(ctx
->opcode
))
3131 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
3136 /*** Integer load and store with byte reverse ***/
3139 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3141 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3142 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3144 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
3147 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3149 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3150 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3152 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
3154 #if defined(TARGET_PPC64)
3156 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3158 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3159 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3161 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
3162 #endif /* TARGET_PPC64 */
3165 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3167 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3168 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3170 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3173 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3175 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3176 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3178 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3180 #if defined(TARGET_PPC64)
3182 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3184 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3185 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3187 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
3188 #endif /* TARGET_PPC64 */
3190 /*** Integer load and store multiple ***/
3193 static void gen_lmw(DisasContext
*ctx
)
3197 gen_set_access_type(ctx
, ACCESS_INT
);
3198 /* NIP cannot be restored if the memory exception comes from an helper */
3199 gen_update_nip(ctx
, ctx
->nip
- 4);
3200 t0
= tcg_temp_new();
3201 t1
= tcg_const_i32(rD(ctx
->opcode
));
3202 gen_addr_imm_index(ctx
, t0
, 0);
3203 gen_helper_lmw(cpu_env
, t0
, t1
);
3205 tcg_temp_free_i32(t1
);
3209 static void gen_stmw(DisasContext
*ctx
)
3213 gen_set_access_type(ctx
, ACCESS_INT
);
3214 /* NIP cannot be restored if the memory exception comes from an helper */
3215 gen_update_nip(ctx
, ctx
->nip
- 4);
3216 t0
= tcg_temp_new();
3217 t1
= tcg_const_i32(rS(ctx
->opcode
));
3218 gen_addr_imm_index(ctx
, t0
, 0);
3219 gen_helper_stmw(cpu_env
, t0
, t1
);
3221 tcg_temp_free_i32(t1
);
3224 /*** Integer load and store strings ***/
3227 /* PowerPC32 specification says we must generate an exception if
3228 * rA is in the range of registers to be loaded.
3229 * In an other hand, IBM says this is valid, but rA won't be loaded.
3230 * For now, I'll follow the spec...
3232 static void gen_lswi(DisasContext
*ctx
)
3236 int nb
= NB(ctx
->opcode
);
3237 int start
= rD(ctx
->opcode
);
3238 int ra
= rA(ctx
->opcode
);
3244 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
3245 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3248 gen_set_access_type(ctx
, ACCESS_INT
);
3249 /* NIP cannot be restored if the memory exception comes from an helper */
3250 gen_update_nip(ctx
, ctx
->nip
- 4);
3251 t0
= tcg_temp_new();
3252 gen_addr_register(ctx
, t0
);
3253 t1
= tcg_const_i32(nb
);
3254 t2
= tcg_const_i32(start
);
3255 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3257 tcg_temp_free_i32(t1
);
3258 tcg_temp_free_i32(t2
);
3262 static void gen_lswx(DisasContext
*ctx
)
3265 TCGv_i32 t1
, t2
, t3
;
3266 gen_set_access_type(ctx
, ACCESS_INT
);
3267 /* NIP cannot be restored if the memory exception comes from an helper */
3268 gen_update_nip(ctx
, ctx
->nip
- 4);
3269 t0
= tcg_temp_new();
3270 gen_addr_reg_index(ctx
, t0
);
3271 t1
= tcg_const_i32(rD(ctx
->opcode
));
3272 t2
= tcg_const_i32(rA(ctx
->opcode
));
3273 t3
= tcg_const_i32(rB(ctx
->opcode
));
3274 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3276 tcg_temp_free_i32(t1
);
3277 tcg_temp_free_i32(t2
);
3278 tcg_temp_free_i32(t3
);
3282 static void gen_stswi(DisasContext
*ctx
)
3286 int nb
= NB(ctx
->opcode
);
3287 gen_set_access_type(ctx
, ACCESS_INT
);
3288 /* NIP cannot be restored if the memory exception comes from an helper */
3289 gen_update_nip(ctx
, ctx
->nip
- 4);
3290 t0
= tcg_temp_new();
3291 gen_addr_register(ctx
, t0
);
3294 t1
= tcg_const_i32(nb
);
3295 t2
= tcg_const_i32(rS(ctx
->opcode
));
3296 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3298 tcg_temp_free_i32(t1
);
3299 tcg_temp_free_i32(t2
);
3303 static void gen_stswx(DisasContext
*ctx
)
3307 gen_set_access_type(ctx
, ACCESS_INT
);
3308 /* NIP cannot be restored if the memory exception comes from an helper */
3309 gen_update_nip(ctx
, ctx
->nip
- 4);
3310 t0
= tcg_temp_new();
3311 gen_addr_reg_index(ctx
, t0
);
3312 t1
= tcg_temp_new_i32();
3313 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3314 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3315 t2
= tcg_const_i32(rS(ctx
->opcode
));
3316 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3318 tcg_temp_free_i32(t1
);
3319 tcg_temp_free_i32(t2
);
3322 /*** Memory synchronisation ***/
3324 static void gen_eieio(DisasContext
*ctx
)
3328 #if !defined(CONFIG_USER_ONLY)
3329 static inline void gen_check_tlb_flush(DisasContext
*ctx
)
3334 if (!ctx
->lazy_tlb_flush
) {
3337 l
= gen_new_label();
3338 t
= tcg_temp_new_i32();
3339 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3340 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3341 gen_helper_check_tlb_flush(cpu_env
);
3343 tcg_temp_free_i32(t
);
3346 static inline void gen_check_tlb_flush(DisasContext
*ctx
) { }
3350 static void gen_isync(DisasContext
*ctx
)
3353 * We need to check for a pending TLB flush. This can only happen in
3354 * kernel mode however so check MSR_PR
3357 gen_check_tlb_flush(ctx
);
3359 gen_stop_exception(ctx
);
3362 #define LARX(name, len, loadop) \
3363 static void gen_##name(DisasContext *ctx) \
3366 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3367 gen_set_access_type(ctx, ACCESS_RES); \
3368 t0 = tcg_temp_local_new(); \
3369 gen_addr_reg_index(ctx, t0); \
3371 gen_check_align(ctx, t0, (len)-1); \
3373 gen_qemu_##loadop(ctx, gpr, t0); \
3374 tcg_gen_mov_tl(cpu_reserve, t0); \
3375 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3376 tcg_temp_free(t0); \
3380 LARX(lbarx
, 1, ld8u
);
3381 LARX(lharx
, 2, ld16u
);
3382 LARX(lwarx
, 4, ld32u
);
3385 #if defined(CONFIG_USER_ONLY)
3386 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3389 TCGv t0
= tcg_temp_new();
3390 uint32_t save_exception
= ctx
->exception
;
3392 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3393 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3394 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3396 gen_update_nip(ctx
, ctx
->nip
-4);
3397 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3398 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3399 ctx
->exception
= save_exception
;
3402 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3407 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3408 l1
= gen_new_label();
3409 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3410 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3411 #if defined(TARGET_PPC64)
3413 gen_qemu_st64(ctx
, cpu_gpr
[reg
], EA
);
3417 gen_qemu_st32(ctx
, cpu_gpr
[reg
], EA
);
3418 } else if (size
== 2) {
3419 gen_qemu_st16(ctx
, cpu_gpr
[reg
], EA
);
3420 #if defined(TARGET_PPC64)
3421 } else if (size
== 16) {
3422 TCGv gpr1
, gpr2
, EA8
;
3423 if (unlikely(ctx
->le_mode
)) {
3424 gpr1
= cpu_gpr
[reg
+1];
3425 gpr2
= cpu_gpr
[reg
];
3427 gpr1
= cpu_gpr
[reg
];
3428 gpr2
= cpu_gpr
[reg
+1];
3430 gen_qemu_st64(ctx
, gpr1
, EA
);
3431 EA8
= tcg_temp_local_new();
3432 gen_addr_add(ctx
, EA8
, EA
, 8);
3433 gen_qemu_st64(ctx
, gpr2
, EA8
);
3437 gen_qemu_st8(ctx
, cpu_gpr
[reg
], EA
);
3440 tcg_gen_movi_tl(cpu_reserve
, -1);
3444 #define STCX(name, len) \
3445 static void gen_##name(DisasContext *ctx) \
3448 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3449 gen_inval_exception(ctx, \
3450 POWERPC_EXCP_INVAL_INVAL); \
3453 gen_set_access_type(ctx, ACCESS_RES); \
3454 t0 = tcg_temp_local_new(); \
3455 gen_addr_reg_index(ctx, t0); \
3457 gen_check_align(ctx, t0, (len)-1); \
3459 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3460 tcg_temp_free(t0); \
3467 #if defined(TARGET_PPC64)
3469 LARX(ldarx
, 8, ld64
);
3472 static void gen_lqarx(DisasContext
*ctx
)
3475 int rd
= rD(ctx
->opcode
);
3478 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3479 (rd
== rB(ctx
->opcode
)))) {
3480 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3484 gen_set_access_type(ctx
, ACCESS_RES
);
3485 EA
= tcg_temp_local_new();
3486 gen_addr_reg_index(ctx
, EA
);
3487 gen_check_align(ctx
, EA
, 15);
3488 if (unlikely(ctx
->le_mode
)) {
3489 gpr1
= cpu_gpr
[rd
+1];
3493 gpr2
= cpu_gpr
[rd
+1];
3495 gen_qemu_ld64(ctx
, gpr1
, EA
);
3496 tcg_gen_mov_tl(cpu_reserve
, EA
);
3498 gen_addr_add(ctx
, EA
, EA
, 8);
3499 gen_qemu_ld64(ctx
, gpr2
, EA
);
3501 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3502 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3510 #endif /* defined(TARGET_PPC64) */
3513 static void gen_sync(DisasContext
*ctx
)
3515 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3518 * We may need to check for a pending TLB flush.
3520 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3522 * Additionally, this can only happen in kernel mode however so
3523 * check MSR_PR as well.
3525 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3526 gen_check_tlb_flush(ctx
);
3531 static void gen_wait(DisasContext
*ctx
)
3533 TCGv_i32 t0
= tcg_const_i32(1);
3534 tcg_gen_st_i32(t0
, cpu_env
,
3535 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3536 tcg_temp_free_i32(t0
);
3537 /* Stop translation, as the CPU is supposed to sleep from now */
3538 gen_exception_err(ctx
, EXCP_HLT
, 1);
3541 /*** Floating-point load ***/
3542 #define GEN_LDF(name, ldop, opc, type) \
3543 static void glue(gen_, name)(DisasContext *ctx) \
3546 if (unlikely(!ctx->fpu_enabled)) { \
3547 gen_exception(ctx, POWERPC_EXCP_FPU); \
3550 gen_set_access_type(ctx, ACCESS_FLOAT); \
3551 EA = tcg_temp_new(); \
3552 gen_addr_imm_index(ctx, EA, 0); \
3553 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3554 tcg_temp_free(EA); \
3557 #define GEN_LDUF(name, ldop, opc, type) \
3558 static void glue(gen_, name##u)(DisasContext *ctx) \
3561 if (unlikely(!ctx->fpu_enabled)) { \
3562 gen_exception(ctx, POWERPC_EXCP_FPU); \
3565 if (unlikely(rA(ctx->opcode) == 0)) { \
3566 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3569 gen_set_access_type(ctx, ACCESS_FLOAT); \
3570 EA = tcg_temp_new(); \
3571 gen_addr_imm_index(ctx, EA, 0); \
3572 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3573 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3574 tcg_temp_free(EA); \
3577 #define GEN_LDUXF(name, ldop, opc, type) \
3578 static void glue(gen_, name##ux)(DisasContext *ctx) \
3581 if (unlikely(!ctx->fpu_enabled)) { \
3582 gen_exception(ctx, POWERPC_EXCP_FPU); \
3585 if (unlikely(rA(ctx->opcode) == 0)) { \
3586 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3589 gen_set_access_type(ctx, ACCESS_FLOAT); \
3590 EA = tcg_temp_new(); \
3591 gen_addr_reg_index(ctx, EA); \
3592 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3593 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3594 tcg_temp_free(EA); \
3597 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3598 static void glue(gen_, name##x)(DisasContext *ctx) \
3601 if (unlikely(!ctx->fpu_enabled)) { \
3602 gen_exception(ctx, POWERPC_EXCP_FPU); \
3605 gen_set_access_type(ctx, ACCESS_FLOAT); \
3606 EA = tcg_temp_new(); \
3607 gen_addr_reg_index(ctx, EA); \
3608 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3609 tcg_temp_free(EA); \
3612 #define GEN_LDFS(name, ldop, op, type) \
3613 GEN_LDF(name, ldop, op | 0x20, type); \
3614 GEN_LDUF(name, ldop, op | 0x21, type); \
3615 GEN_LDUXF(name, ldop, op | 0x01, type); \
3616 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3618 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3620 TCGv t0
= tcg_temp_new();
3621 TCGv_i32 t1
= tcg_temp_new_i32();
3622 gen_qemu_ld32u(ctx
, t0
, arg2
);
3623 tcg_gen_trunc_tl_i32(t1
, t0
);
3625 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3626 tcg_temp_free_i32(t1
);
3629 /* lfd lfdu lfdux lfdx */
3630 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3631 /* lfs lfsu lfsux lfsx */
3632 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3635 static void gen_lfdp(DisasContext
*ctx
)
3638 if (unlikely(!ctx
->fpu_enabled
)) {
3639 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3642 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3643 EA
= tcg_temp_new();
3644 gen_addr_imm_index(ctx
, EA
, 0);
3645 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3646 64-bit byteswap already. */
3647 if (unlikely(ctx
->le_mode
)) {
3648 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3649 tcg_gen_addi_tl(EA
, EA
, 8);
3650 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3652 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3653 tcg_gen_addi_tl(EA
, EA
, 8);
3654 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3660 static void gen_lfdpx(DisasContext
*ctx
)
3663 if (unlikely(!ctx
->fpu_enabled
)) {
3664 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3667 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3668 EA
= tcg_temp_new();
3669 gen_addr_reg_index(ctx
, EA
);
3670 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3671 64-bit byteswap already. */
3672 if (unlikely(ctx
->le_mode
)) {
3673 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3674 tcg_gen_addi_tl(EA
, EA
, 8);
3675 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3677 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3678 tcg_gen_addi_tl(EA
, EA
, 8);
3679 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3685 static void gen_lfiwax(DisasContext
*ctx
)
3689 if (unlikely(!ctx
->fpu_enabled
)) {
3690 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3693 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3694 EA
= tcg_temp_new();
3695 t0
= tcg_temp_new();
3696 gen_addr_reg_index(ctx
, EA
);
3697 gen_qemu_ld32s(ctx
, t0
, EA
);
3698 tcg_gen_ext_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], t0
);
3704 static void gen_lfiwzx(DisasContext
*ctx
)
3707 if (unlikely(!ctx
->fpu_enabled
)) {
3708 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3711 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3712 EA
= tcg_temp_new();
3713 gen_addr_reg_index(ctx
, EA
);
3714 gen_qemu_ld32u_i64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3717 /*** Floating-point store ***/
3718 #define GEN_STF(name, stop, opc, type) \
3719 static void glue(gen_, name)(DisasContext *ctx) \
3722 if (unlikely(!ctx->fpu_enabled)) { \
3723 gen_exception(ctx, POWERPC_EXCP_FPU); \
3726 gen_set_access_type(ctx, ACCESS_FLOAT); \
3727 EA = tcg_temp_new(); \
3728 gen_addr_imm_index(ctx, EA, 0); \
3729 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3730 tcg_temp_free(EA); \
3733 #define GEN_STUF(name, stop, opc, type) \
3734 static void glue(gen_, name##u)(DisasContext *ctx) \
3737 if (unlikely(!ctx->fpu_enabled)) { \
3738 gen_exception(ctx, POWERPC_EXCP_FPU); \
3741 if (unlikely(rA(ctx->opcode) == 0)) { \
3742 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3745 gen_set_access_type(ctx, ACCESS_FLOAT); \
3746 EA = tcg_temp_new(); \
3747 gen_addr_imm_index(ctx, EA, 0); \
3748 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3749 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3750 tcg_temp_free(EA); \
3753 #define GEN_STUXF(name, stop, opc, type) \
3754 static void glue(gen_, name##ux)(DisasContext *ctx) \
3757 if (unlikely(!ctx->fpu_enabled)) { \
3758 gen_exception(ctx, POWERPC_EXCP_FPU); \
3761 if (unlikely(rA(ctx->opcode) == 0)) { \
3762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3765 gen_set_access_type(ctx, ACCESS_FLOAT); \
3766 EA = tcg_temp_new(); \
3767 gen_addr_reg_index(ctx, EA); \
3768 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3770 tcg_temp_free(EA); \
3773 #define GEN_STXF(name, stop, opc2, opc3, type) \
3774 static void glue(gen_, name##x)(DisasContext *ctx) \
3777 if (unlikely(!ctx->fpu_enabled)) { \
3778 gen_exception(ctx, POWERPC_EXCP_FPU); \
3781 gen_set_access_type(ctx, ACCESS_FLOAT); \
3782 EA = tcg_temp_new(); \
3783 gen_addr_reg_index(ctx, EA); \
3784 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3785 tcg_temp_free(EA); \
3788 #define GEN_STFS(name, stop, op, type) \
3789 GEN_STF(name, stop, op | 0x20, type); \
3790 GEN_STUF(name, stop, op | 0x21, type); \
3791 GEN_STUXF(name, stop, op | 0x01, type); \
3792 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3794 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3796 TCGv_i32 t0
= tcg_temp_new_i32();
3797 TCGv t1
= tcg_temp_new();
3798 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3799 tcg_gen_extu_i32_tl(t1
, t0
);
3800 tcg_temp_free_i32(t0
);
3801 gen_qemu_st32(ctx
, t1
, arg2
);
3805 /* stfd stfdu stfdux stfdx */
3806 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3807 /* stfs stfsu stfsux stfsx */
3808 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3811 static void gen_stfdp(DisasContext
*ctx
)
3814 if (unlikely(!ctx
->fpu_enabled
)) {
3815 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3818 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3819 EA
= tcg_temp_new();
3820 gen_addr_imm_index(ctx
, EA
, 0);
3821 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3822 64-bit byteswap already. */
3823 if (unlikely(ctx
->le_mode
)) {
3824 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3825 tcg_gen_addi_tl(EA
, EA
, 8);
3826 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3828 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3829 tcg_gen_addi_tl(EA
, EA
, 8);
3830 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3836 static void gen_stfdpx(DisasContext
*ctx
)
3839 if (unlikely(!ctx
->fpu_enabled
)) {
3840 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3843 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3844 EA
= tcg_temp_new();
3845 gen_addr_reg_index(ctx
, EA
);
3846 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3847 64-bit byteswap already. */
3848 if (unlikely(ctx
->le_mode
)) {
3849 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3850 tcg_gen_addi_tl(EA
, EA
, 8);
3851 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3853 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3854 tcg_gen_addi_tl(EA
, EA
, 8);
3855 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3861 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3863 TCGv t0
= tcg_temp_new();
3864 tcg_gen_trunc_i64_tl(t0
, arg1
),
3865 gen_qemu_st32(ctx
, t0
, arg2
);
3869 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3871 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3873 #if defined(TARGET_PPC64)
3875 tcg_gen_movi_tl(cpu_cfar
, nip
);
3879 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3881 if (unlikely(ctx
->singlestep_enabled
)) {
3885 #ifndef CONFIG_USER_ONLY
3886 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3893 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3895 if (NARROW_MODE(ctx
)) {
3896 dest
= (uint32_t) dest
;
3898 if (use_goto_tb(ctx
, dest
)) {
3900 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3901 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3903 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3904 if (unlikely(ctx
->singlestep_enabled
)) {
3905 if ((ctx
->singlestep_enabled
&
3906 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3907 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3908 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3909 target_ulong tmp
= ctx
->nip
;
3911 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3914 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3915 gen_debug_exception(ctx
);
3922 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3924 if (NARROW_MODE(ctx
)) {
3925 nip
= (uint32_t)nip
;
3927 tcg_gen_movi_tl(cpu_lr
, nip
);
3931 static void gen_b(DisasContext
*ctx
)
3933 target_ulong li
, target
;
3935 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3936 /* sign extend LI */
3937 li
= LI(ctx
->opcode
);
3938 li
= (li
^ 0x02000000) - 0x02000000;
3939 if (likely(AA(ctx
->opcode
) == 0)) {
3940 target
= ctx
->nip
+ li
- 4;
3944 if (LK(ctx
->opcode
)) {
3945 gen_setlr(ctx
, ctx
->nip
);
3947 gen_update_cfar(ctx
, ctx
->nip
);
3948 gen_goto_tb(ctx
, 0, target
);
3956 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3958 uint32_t bo
= BO(ctx
->opcode
);
3962 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3963 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3964 target
= tcg_temp_local_new();
3965 if (type
== BCOND_CTR
)
3966 tcg_gen_mov_tl(target
, cpu_ctr
);
3967 else if (type
== BCOND_TAR
)
3968 gen_load_spr(target
, SPR_TAR
);
3970 tcg_gen_mov_tl(target
, cpu_lr
);
3972 TCGV_UNUSED(target
);
3974 if (LK(ctx
->opcode
))
3975 gen_setlr(ctx
, ctx
->nip
);
3976 l1
= gen_new_label();
3977 if ((bo
& 0x4) == 0) {
3978 /* Decrement and test CTR */
3979 TCGv temp
= tcg_temp_new();
3980 if (unlikely(type
== BCOND_CTR
)) {
3981 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3984 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3985 if (NARROW_MODE(ctx
)) {
3986 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3988 tcg_gen_mov_tl(temp
, cpu_ctr
);
3991 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3993 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3995 tcg_temp_free(temp
);
3997 if ((bo
& 0x10) == 0) {
3999 uint32_t bi
= BI(ctx
->opcode
);
4000 uint32_t mask
= 0x08 >> (bi
& 0x03);
4001 TCGv_i32 temp
= tcg_temp_new_i32();
4004 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
4005 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
4007 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
4008 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
4010 tcg_temp_free_i32(temp
);
4012 gen_update_cfar(ctx
, ctx
->nip
);
4013 if (type
== BCOND_IM
) {
4014 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
4015 if (likely(AA(ctx
->opcode
) == 0)) {
4016 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
4018 gen_goto_tb(ctx
, 0, li
);
4021 gen_goto_tb(ctx
, 1, ctx
->nip
);
4023 if (NARROW_MODE(ctx
)) {
4024 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
4026 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
4030 gen_update_nip(ctx
, ctx
->nip
);
4033 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
4034 tcg_temp_free(target
);
4038 static void gen_bc(DisasContext
*ctx
)
4040 gen_bcond(ctx
, BCOND_IM
);
4043 static void gen_bcctr(DisasContext
*ctx
)
4045 gen_bcond(ctx
, BCOND_CTR
);
4048 static void gen_bclr(DisasContext
*ctx
)
4050 gen_bcond(ctx
, BCOND_LR
);
4053 static void gen_bctar(DisasContext
*ctx
)
4055 gen_bcond(ctx
, BCOND_TAR
);
4058 /*** Condition register logical ***/
4059 #define GEN_CRLOGIC(name, tcg_op, opc) \
4060 static void glue(gen_, name)(DisasContext *ctx) \
4065 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4066 t0 = tcg_temp_new_i32(); \
4068 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4070 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4072 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4073 t1 = tcg_temp_new_i32(); \
4074 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4076 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4078 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4080 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4081 tcg_op(t0, t0, t1); \
4082 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4083 tcg_gen_andi_i32(t0, t0, bitmask); \
4084 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4085 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4086 tcg_temp_free_i32(t0); \
4087 tcg_temp_free_i32(t1); \
4091 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
4093 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
4095 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
4097 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
4099 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
4101 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
4103 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
4105 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
4108 static void gen_mcrf(DisasContext
*ctx
)
4110 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
4113 /*** System linkage ***/
4115 /* rfi (supervisor only) */
4116 static void gen_rfi(DisasContext
*ctx
)
4118 #if defined(CONFIG_USER_ONLY)
4119 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4121 /* Restore CPU state */
4122 if (unlikely(ctx
->pr
)) {
4123 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4126 gen_update_cfar(ctx
, ctx
->nip
);
4127 gen_helper_rfi(cpu_env
);
4128 gen_sync_exception(ctx
);
4132 #if defined(TARGET_PPC64)
4133 static void gen_rfid(DisasContext
*ctx
)
4135 #if defined(CONFIG_USER_ONLY)
4136 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4138 /* Restore CPU state */
4139 if (unlikely(ctx
->pr
)) {
4140 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4143 gen_update_cfar(ctx
, ctx
->nip
);
4144 gen_helper_rfid(cpu_env
);
4145 gen_sync_exception(ctx
);
4149 static void gen_hrfid(DisasContext
*ctx
)
4151 #if defined(CONFIG_USER_ONLY)
4152 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4154 /* Restore CPU state */
4155 if (unlikely(ctx
->pr
|| !ctx
->hv
)) {
4156 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4159 gen_helper_hrfid(cpu_env
);
4160 gen_sync_exception(ctx
);
4166 #if defined(CONFIG_USER_ONLY)
4167 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4169 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4171 static void gen_sc(DisasContext
*ctx
)
4175 lev
= (ctx
->opcode
>> 5) & 0x7F;
4176 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4182 static void gen_tw(DisasContext
*ctx
)
4184 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4185 /* Update the nip since this might generate a trap exception */
4186 gen_update_nip(ctx
, ctx
->nip
);
4187 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4189 tcg_temp_free_i32(t0
);
4193 static void gen_twi(DisasContext
*ctx
)
4195 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4196 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4197 /* Update the nip since this might generate a trap exception */
4198 gen_update_nip(ctx
, ctx
->nip
);
4199 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4201 tcg_temp_free_i32(t1
);
4204 #if defined(TARGET_PPC64)
4206 static void gen_td(DisasContext
*ctx
)
4208 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4209 /* Update the nip since this might generate a trap exception */
4210 gen_update_nip(ctx
, ctx
->nip
);
4211 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4213 tcg_temp_free_i32(t0
);
4217 static void gen_tdi(DisasContext
*ctx
)
4219 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4220 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4221 /* Update the nip since this might generate a trap exception */
4222 gen_update_nip(ctx
, ctx
->nip
);
4223 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4225 tcg_temp_free_i32(t1
);
4229 /*** Processor control ***/
4231 static void gen_read_xer(TCGv dst
)
4233 TCGv t0
= tcg_temp_new();
4234 TCGv t1
= tcg_temp_new();
4235 TCGv t2
= tcg_temp_new();
4236 tcg_gen_mov_tl(dst
, cpu_xer
);
4237 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4238 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4239 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4240 tcg_gen_or_tl(t0
, t0
, t1
);
4241 tcg_gen_or_tl(dst
, dst
, t2
);
4242 tcg_gen_or_tl(dst
, dst
, t0
);
4248 static void gen_write_xer(TCGv src
)
4250 tcg_gen_andi_tl(cpu_xer
, src
,
4251 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
4252 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
4253 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
4254 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
4255 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
4256 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
4257 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
4261 static void gen_mcrxr(DisasContext
*ctx
)
4263 TCGv_i32 t0
= tcg_temp_new_i32();
4264 TCGv_i32 t1
= tcg_temp_new_i32();
4265 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4267 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4268 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4269 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4270 tcg_gen_shli_i32(t0
, t0
, 3);
4271 tcg_gen_shli_i32(t1
, t1
, 2);
4272 tcg_gen_shli_i32(dst
, dst
, 1);
4273 tcg_gen_or_i32(dst
, dst
, t0
);
4274 tcg_gen_or_i32(dst
, dst
, t1
);
4275 tcg_temp_free_i32(t0
);
4276 tcg_temp_free_i32(t1
);
4278 tcg_gen_movi_tl(cpu_so
, 0);
4279 tcg_gen_movi_tl(cpu_ov
, 0);
4280 tcg_gen_movi_tl(cpu_ca
, 0);
4284 static void gen_mfcr(DisasContext
*ctx
)
4288 if (likely(ctx
->opcode
& 0x00100000)) {
4289 crm
= CRM(ctx
->opcode
);
4290 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4292 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4293 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4294 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4297 TCGv_i32 t0
= tcg_temp_new_i32();
4298 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4299 tcg_gen_shli_i32(t0
, t0
, 4);
4300 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4301 tcg_gen_shli_i32(t0
, t0
, 4);
4302 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4303 tcg_gen_shli_i32(t0
, t0
, 4);
4304 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4305 tcg_gen_shli_i32(t0
, t0
, 4);
4306 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4307 tcg_gen_shli_i32(t0
, t0
, 4);
4308 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4309 tcg_gen_shli_i32(t0
, t0
, 4);
4310 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4311 tcg_gen_shli_i32(t0
, t0
, 4);
4312 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4313 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4314 tcg_temp_free_i32(t0
);
4319 static void gen_mfmsr(DisasContext
*ctx
)
4321 #if defined(CONFIG_USER_ONLY)
4322 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4324 if (unlikely(ctx
->pr
)) {
4325 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4328 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4332 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4335 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4336 printf("ERROR: try to access SPR %d !\n", sprn
);
4339 #define SPR_NOACCESS (&spr_noaccess)
4342 static inline void gen_op_mfspr(DisasContext
*ctx
)
4344 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4345 uint32_t sprn
= SPR(ctx
->opcode
);
4347 #if defined(CONFIG_USER_ONLY)
4348 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4351 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4352 } else if (ctx
->hv
) {
4353 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4355 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4358 if (likely(read_cb
!= NULL
)) {
4359 if (likely(read_cb
!= SPR_NOACCESS
)) {
4360 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4362 /* Privilege exception */
4363 /* This is a hack to avoid warnings when running Linux:
4364 * this OS breaks the PowerPC virtualisation model,
4365 * allowing userland application to read the PVR
4367 if (sprn
!= SPR_PVR
) {
4368 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
4369 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4370 if (qemu_log_separate()) {
4371 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4372 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4375 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4379 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
4380 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4381 if (qemu_log_separate()) {
4382 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4383 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4385 /* Only generate an exception in user space, otherwise this is a nop */
4387 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4392 static void gen_mfspr(DisasContext
*ctx
)
4398 static void gen_mftb(DisasContext
*ctx
)
4404 static void gen_mtcrf(DisasContext
*ctx
)
4408 crm
= CRM(ctx
->opcode
);
4409 if (likely((ctx
->opcode
& 0x00100000))) {
4410 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4411 TCGv_i32 temp
= tcg_temp_new_i32();
4413 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4414 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4415 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4416 tcg_temp_free_i32(temp
);
4419 TCGv_i32 temp
= tcg_temp_new_i32();
4420 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4421 for (crn
= 0 ; crn
< 8 ; crn
++) {
4422 if (crm
& (1 << crn
)) {
4423 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4424 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4427 tcg_temp_free_i32(temp
);
4432 #if defined(TARGET_PPC64)
4433 static void gen_mtmsrd(DisasContext
*ctx
)
4435 #if defined(CONFIG_USER_ONLY)
4436 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4438 if (unlikely(ctx
->pr
)) {
4439 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4442 if (ctx
->opcode
& 0x00010000) {
4443 /* Special form that does not need any synchronisation */
4444 TCGv t0
= tcg_temp_new();
4445 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4446 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4447 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4450 /* XXX: we need to update nip before the store
4451 * if we enter power saving mode, we will exit the loop
4452 * directly from ppc_store_msr
4454 gen_update_nip(ctx
, ctx
->nip
);
4455 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4456 /* Must stop the translation as machine state (may have) changed */
4457 /* Note that mtmsr is not always defined as context-synchronizing */
4458 gen_stop_exception(ctx
);
4464 static void gen_mtmsr(DisasContext
*ctx
)
4466 #if defined(CONFIG_USER_ONLY)
4467 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4469 if (unlikely(ctx
->pr
)) {
4470 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4473 if (ctx
->opcode
& 0x00010000) {
4474 /* Special form that does not need any synchronisation */
4475 TCGv t0
= tcg_temp_new();
4476 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4477 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4478 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4481 TCGv msr
= tcg_temp_new();
4483 /* XXX: we need to update nip before the store
4484 * if we enter power saving mode, we will exit the loop
4485 * directly from ppc_store_msr
4487 gen_update_nip(ctx
, ctx
->nip
);
4488 #if defined(TARGET_PPC64)
4489 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4491 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4493 gen_helper_store_msr(cpu_env
, msr
);
4495 /* Must stop the translation as machine state (may have) changed */
4496 /* Note that mtmsr is not always defined as context-synchronizing */
4497 gen_stop_exception(ctx
);
4503 static void gen_mtspr(DisasContext
*ctx
)
4505 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4506 uint32_t sprn
= SPR(ctx
->opcode
);
4508 #if defined(CONFIG_USER_ONLY)
4509 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4512 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4513 } else if (ctx
->hv
) {
4514 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4516 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4519 if (likely(write_cb
!= NULL
)) {
4520 if (likely(write_cb
!= SPR_NOACCESS
)) {
4521 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4523 /* Privilege exception */
4524 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
4525 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4526 if (qemu_log_separate()) {
4527 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4528 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4530 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4534 if (qemu_log_separate()) {
4535 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4536 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4538 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
4539 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4541 /* Only generate an exception in user space, otherwise this is a nop */
4543 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4548 /*** Cache management ***/
4551 static void gen_dcbf(DisasContext
*ctx
)
4553 /* XXX: specification says this is treated as a load by the MMU */
4555 gen_set_access_type(ctx
, ACCESS_CACHE
);
4556 t0
= tcg_temp_new();
4557 gen_addr_reg_index(ctx
, t0
);
4558 gen_qemu_ld8u(ctx
, t0
, t0
);
4562 /* dcbi (Supervisor only) */
4563 static void gen_dcbi(DisasContext
*ctx
)
4565 #if defined(CONFIG_USER_ONLY)
4566 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4569 if (unlikely(ctx
->pr
)) {
4570 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4573 EA
= tcg_temp_new();
4574 gen_set_access_type(ctx
, ACCESS_CACHE
);
4575 gen_addr_reg_index(ctx
, EA
);
4576 val
= tcg_temp_new();
4577 /* XXX: specification says this should be treated as a store by the MMU */
4578 gen_qemu_ld8u(ctx
, val
, EA
);
4579 gen_qemu_st8(ctx
, val
, EA
);
4586 static void gen_dcbst(DisasContext
*ctx
)
4588 /* XXX: specification say this is treated as a load by the MMU */
4590 gen_set_access_type(ctx
, ACCESS_CACHE
);
4591 t0
= tcg_temp_new();
4592 gen_addr_reg_index(ctx
, t0
);
4593 gen_qemu_ld8u(ctx
, t0
, t0
);
4598 static void gen_dcbt(DisasContext
*ctx
)
4600 /* interpreted as no-op */
4601 /* XXX: specification say this is treated as a load by the MMU
4602 * but does not generate any exception
4607 static void gen_dcbtst(DisasContext
*ctx
)
4609 /* interpreted as no-op */
4610 /* XXX: specification say this is treated as a load by the MMU
4611 * but does not generate any exception
4616 static void gen_dcbtls(DisasContext
*ctx
)
4618 /* Always fails locking the cache */
4619 TCGv t0
= tcg_temp_new();
4620 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4621 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4622 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4627 static void gen_dcbz(DisasContext
*ctx
)
4630 TCGv_i32 tcgv_is_dcbzl
;
4631 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4633 gen_set_access_type(ctx
, ACCESS_CACHE
);
4634 /* NIP cannot be restored if the memory exception comes from an helper */
4635 gen_update_nip(ctx
, ctx
->nip
- 4);
4636 tcgv_addr
= tcg_temp_new();
4637 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4639 gen_addr_reg_index(ctx
, tcgv_addr
);
4640 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4642 tcg_temp_free(tcgv_addr
);
4643 tcg_temp_free_i32(tcgv_is_dcbzl
);
4647 static void gen_dst(DisasContext
*ctx
)
4649 if (rA(ctx
->opcode
) == 0) {
4650 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4652 /* interpreted as no-op */
4657 static void gen_dstst(DisasContext
*ctx
)
4659 if (rA(ctx
->opcode
) == 0) {
4660 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4662 /* interpreted as no-op */
4668 static void gen_dss(DisasContext
*ctx
)
4670 /* interpreted as no-op */
4674 static void gen_icbi(DisasContext
*ctx
)
4677 gen_set_access_type(ctx
, ACCESS_CACHE
);
4678 /* NIP cannot be restored if the memory exception comes from an helper */
4679 gen_update_nip(ctx
, ctx
->nip
- 4);
4680 t0
= tcg_temp_new();
4681 gen_addr_reg_index(ctx
, t0
);
4682 gen_helper_icbi(cpu_env
, t0
);
4688 static void gen_dcba(DisasContext
*ctx
)
4690 /* interpreted as no-op */
4691 /* XXX: specification say this is treated as a store by the MMU
4692 * but does not generate any exception
4696 /*** Segment register manipulation ***/
4697 /* Supervisor only: */
4700 static void gen_mfsr(DisasContext
*ctx
)
4702 #if defined(CONFIG_USER_ONLY)
4703 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4706 if (unlikely(ctx
->pr
)) {
4707 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4710 t0
= tcg_const_tl(SR(ctx
->opcode
));
4711 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4717 static void gen_mfsrin(DisasContext
*ctx
)
4719 #if defined(CONFIG_USER_ONLY)
4720 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4723 if (unlikely(ctx
->pr
)) {
4724 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4727 t0
= tcg_temp_new();
4728 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4729 tcg_gen_andi_tl(t0
, t0
, 0xF);
4730 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4736 static void gen_mtsr(DisasContext
*ctx
)
4738 #if defined(CONFIG_USER_ONLY)
4739 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4742 if (unlikely(ctx
->pr
)) {
4743 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4746 t0
= tcg_const_tl(SR(ctx
->opcode
));
4747 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4753 static void gen_mtsrin(DisasContext
*ctx
)
4755 #if defined(CONFIG_USER_ONLY)
4756 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4759 if (unlikely(ctx
->pr
)) {
4760 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4763 t0
= tcg_temp_new();
4764 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4765 tcg_gen_andi_tl(t0
, t0
, 0xF);
4766 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4771 #if defined(TARGET_PPC64)
4772 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4775 static void gen_mfsr_64b(DisasContext
*ctx
)
4777 #if defined(CONFIG_USER_ONLY)
4778 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4781 if (unlikely(ctx
->pr
)) {
4782 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4785 t0
= tcg_const_tl(SR(ctx
->opcode
));
4786 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4792 static void gen_mfsrin_64b(DisasContext
*ctx
)
4794 #if defined(CONFIG_USER_ONLY)
4795 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4798 if (unlikely(ctx
->pr
)) {
4799 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4802 t0
= tcg_temp_new();
4803 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4804 tcg_gen_andi_tl(t0
, t0
, 0xF);
4805 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4811 static void gen_mtsr_64b(DisasContext
*ctx
)
4813 #if defined(CONFIG_USER_ONLY)
4814 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4817 if (unlikely(ctx
->pr
)) {
4818 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4821 t0
= tcg_const_tl(SR(ctx
->opcode
));
4822 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4828 static void gen_mtsrin_64b(DisasContext
*ctx
)
4830 #if defined(CONFIG_USER_ONLY)
4831 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4834 if (unlikely(ctx
->pr
)) {
4835 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4838 t0
= tcg_temp_new();
4839 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4840 tcg_gen_andi_tl(t0
, t0
, 0xF);
4841 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4847 static void gen_slbmte(DisasContext
*ctx
)
4849 #if defined(CONFIG_USER_ONLY)
4850 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4852 if (unlikely(ctx
->pr
)) {
4853 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4856 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4857 cpu_gpr
[rS(ctx
->opcode
)]);
4861 static void gen_slbmfee(DisasContext
*ctx
)
4863 #if defined(CONFIG_USER_ONLY)
4864 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4866 if (unlikely(ctx
->pr
)) {
4867 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4870 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4871 cpu_gpr
[rB(ctx
->opcode
)]);
4875 static void gen_slbmfev(DisasContext
*ctx
)
4877 #if defined(CONFIG_USER_ONLY)
4878 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4880 if (unlikely(ctx
->pr
)) {
4881 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4884 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4885 cpu_gpr
[rB(ctx
->opcode
)]);
4889 static void gen_slbfee_(DisasContext
*ctx
)
4891 #if defined(CONFIG_USER_ONLY)
4892 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4896 if (unlikely(ctx
->pr
)) {
4897 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4900 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4901 cpu_gpr
[rB(ctx
->opcode
)]);
4902 l1
= gen_new_label();
4903 l2
= gen_new_label();
4904 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4905 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4906 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
4909 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4913 #endif /* defined(TARGET_PPC64) */
4915 /*** Lookaside buffer management ***/
4916 /* Optional & supervisor only: */
4919 static void gen_tlbia(DisasContext
*ctx
)
4921 #if defined(CONFIG_USER_ONLY)
4922 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4924 if (unlikely(ctx
->pr
|| !ctx
->hv
)) {
4925 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4928 gen_helper_tlbia(cpu_env
);
4933 static void gen_tlbiel(DisasContext
*ctx
)
4935 #if defined(CONFIG_USER_ONLY)
4936 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4938 if (unlikely(ctx
->pr
)) {
4939 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4942 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4947 static void gen_tlbie(DisasContext
*ctx
)
4949 #if defined(CONFIG_USER_ONLY)
4950 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4952 if (unlikely(ctx
->pr
|| !ctx
->hv
)) {
4953 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4956 if (NARROW_MODE(ctx
)) {
4957 TCGv t0
= tcg_temp_new();
4958 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4959 gen_helper_tlbie(cpu_env
, t0
);
4962 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4968 static void gen_tlbsync(DisasContext
*ctx
)
4970 #if defined(CONFIG_USER_ONLY)
4971 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4973 if (unlikely(ctx
->pr
|| !ctx
->hv
)) {
4974 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4977 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4978 * embedded however needs to deal with tlbsync. We don't try to be
4979 * fancy and swallow the overhead of checking for both.
4981 gen_check_tlb_flush(ctx
);
4985 #if defined(TARGET_PPC64)
4987 static void gen_slbia(DisasContext
*ctx
)
4989 #if defined(CONFIG_USER_ONLY)
4990 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4992 if (unlikely(ctx
->pr
)) {
4993 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
4996 gen_helper_slbia(cpu_env
);
5001 static void gen_slbie(DisasContext
*ctx
)
5003 #if defined(CONFIG_USER_ONLY)
5004 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5006 if (unlikely(ctx
->pr
)) {
5007 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5010 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5015 /*** External control ***/
5019 static void gen_eciwx(DisasContext
*ctx
)
5022 /* Should check EAR[E] ! */
5023 gen_set_access_type(ctx
, ACCESS_EXT
);
5024 t0
= tcg_temp_new();
5025 gen_addr_reg_index(ctx
, t0
);
5026 gen_check_align(ctx
, t0
, 0x03);
5027 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
5032 static void gen_ecowx(DisasContext
*ctx
)
5035 /* Should check EAR[E] ! */
5036 gen_set_access_type(ctx
, ACCESS_EXT
);
5037 t0
= tcg_temp_new();
5038 gen_addr_reg_index(ctx
, t0
);
5039 gen_check_align(ctx
, t0
, 0x03);
5040 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
5044 /* PowerPC 601 specific instructions */
5047 static void gen_abs(DisasContext
*ctx
)
5049 TCGLabel
*l1
= gen_new_label();
5050 TCGLabel
*l2
= gen_new_label();
5051 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5052 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5055 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5057 if (unlikely(Rc(ctx
->opcode
) != 0))
5058 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5062 static void gen_abso(DisasContext
*ctx
)
5064 TCGLabel
*l1
= gen_new_label();
5065 TCGLabel
*l2
= gen_new_label();
5066 TCGLabel
*l3
= gen_new_label();
5067 /* Start with XER OV disabled, the most likely case */
5068 tcg_gen_movi_tl(cpu_ov
, 0);
5069 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
5070 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
5071 tcg_gen_movi_tl(cpu_ov
, 1);
5072 tcg_gen_movi_tl(cpu_so
, 1);
5075 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5078 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5080 if (unlikely(Rc(ctx
->opcode
) != 0))
5081 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5085 static void gen_clcs(DisasContext
*ctx
)
5087 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
5088 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5089 tcg_temp_free_i32(t0
);
5090 /* Rc=1 sets CR0 to an undefined state */
5094 static void gen_div(DisasContext
*ctx
)
5096 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5097 cpu_gpr
[rB(ctx
->opcode
)]);
5098 if (unlikely(Rc(ctx
->opcode
) != 0))
5099 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5103 static void gen_divo(DisasContext
*ctx
)
5105 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5106 cpu_gpr
[rB(ctx
->opcode
)]);
5107 if (unlikely(Rc(ctx
->opcode
) != 0))
5108 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5112 static void gen_divs(DisasContext
*ctx
)
5114 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5115 cpu_gpr
[rB(ctx
->opcode
)]);
5116 if (unlikely(Rc(ctx
->opcode
) != 0))
5117 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5120 /* divso - divso. */
5121 static void gen_divso(DisasContext
*ctx
)
5123 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5124 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5125 if (unlikely(Rc(ctx
->opcode
) != 0))
5126 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5130 static void gen_doz(DisasContext
*ctx
)
5132 TCGLabel
*l1
= gen_new_label();
5133 TCGLabel
*l2
= gen_new_label();
5134 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5135 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5138 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5140 if (unlikely(Rc(ctx
->opcode
) != 0))
5141 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5145 static void gen_dozo(DisasContext
*ctx
)
5147 TCGLabel
*l1
= gen_new_label();
5148 TCGLabel
*l2
= gen_new_label();
5149 TCGv t0
= tcg_temp_new();
5150 TCGv t1
= tcg_temp_new();
5151 TCGv t2
= tcg_temp_new();
5152 /* Start with XER OV disabled, the most likely case */
5153 tcg_gen_movi_tl(cpu_ov
, 0);
5154 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5155 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5156 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5157 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5158 tcg_gen_andc_tl(t1
, t1
, t2
);
5159 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5160 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5161 tcg_gen_movi_tl(cpu_ov
, 1);
5162 tcg_gen_movi_tl(cpu_so
, 1);
5165 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5170 if (unlikely(Rc(ctx
->opcode
) != 0))
5171 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5175 static void gen_dozi(DisasContext
*ctx
)
5177 target_long simm
= SIMM(ctx
->opcode
);
5178 TCGLabel
*l1
= gen_new_label();
5179 TCGLabel
*l2
= gen_new_label();
5180 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5181 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5184 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5186 if (unlikely(Rc(ctx
->opcode
) != 0))
5187 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5190 /* lscbx - lscbx. */
5191 static void gen_lscbx(DisasContext
*ctx
)
5193 TCGv t0
= tcg_temp_new();
5194 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5195 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5196 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5198 gen_addr_reg_index(ctx
, t0
);
5199 /* NIP cannot be restored if the memory exception comes from an helper */
5200 gen_update_nip(ctx
, ctx
->nip
- 4);
5201 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5202 tcg_temp_free_i32(t1
);
5203 tcg_temp_free_i32(t2
);
5204 tcg_temp_free_i32(t3
);
5205 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5206 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5207 if (unlikely(Rc(ctx
->opcode
) != 0))
5208 gen_set_Rc0(ctx
, t0
);
5212 /* maskg - maskg. */
5213 static void gen_maskg(DisasContext
*ctx
)
5215 TCGLabel
*l1
= gen_new_label();
5216 TCGv t0
= tcg_temp_new();
5217 TCGv t1
= tcg_temp_new();
5218 TCGv t2
= tcg_temp_new();
5219 TCGv t3
= tcg_temp_new();
5220 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5221 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5222 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5223 tcg_gen_addi_tl(t2
, t0
, 1);
5224 tcg_gen_shr_tl(t2
, t3
, t2
);
5225 tcg_gen_shr_tl(t3
, t3
, t1
);
5226 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5227 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5228 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5234 if (unlikely(Rc(ctx
->opcode
) != 0))
5235 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5238 /* maskir - maskir. */
5239 static void gen_maskir(DisasContext
*ctx
)
5241 TCGv t0
= tcg_temp_new();
5242 TCGv t1
= tcg_temp_new();
5243 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5244 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5245 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5248 if (unlikely(Rc(ctx
->opcode
) != 0))
5249 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5253 static void gen_mul(DisasContext
*ctx
)
5255 TCGv_i64 t0
= tcg_temp_new_i64();
5256 TCGv_i64 t1
= tcg_temp_new_i64();
5257 TCGv t2
= tcg_temp_new();
5258 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5259 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5260 tcg_gen_mul_i64(t0
, t0
, t1
);
5261 tcg_gen_trunc_i64_tl(t2
, t0
);
5262 gen_store_spr(SPR_MQ
, t2
);
5263 tcg_gen_shri_i64(t1
, t0
, 32);
5264 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5265 tcg_temp_free_i64(t0
);
5266 tcg_temp_free_i64(t1
);
5268 if (unlikely(Rc(ctx
->opcode
) != 0))
5269 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5273 static void gen_mulo(DisasContext
*ctx
)
5275 TCGLabel
*l1
= gen_new_label();
5276 TCGv_i64 t0
= tcg_temp_new_i64();
5277 TCGv_i64 t1
= tcg_temp_new_i64();
5278 TCGv t2
= tcg_temp_new();
5279 /* Start with XER OV disabled, the most likely case */
5280 tcg_gen_movi_tl(cpu_ov
, 0);
5281 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5282 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5283 tcg_gen_mul_i64(t0
, t0
, t1
);
5284 tcg_gen_trunc_i64_tl(t2
, t0
);
5285 gen_store_spr(SPR_MQ
, t2
);
5286 tcg_gen_shri_i64(t1
, t0
, 32);
5287 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5288 tcg_gen_ext32s_i64(t1
, t0
);
5289 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5290 tcg_gen_movi_tl(cpu_ov
, 1);
5291 tcg_gen_movi_tl(cpu_so
, 1);
5293 tcg_temp_free_i64(t0
);
5294 tcg_temp_free_i64(t1
);
5296 if (unlikely(Rc(ctx
->opcode
) != 0))
5297 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5301 static void gen_nabs(DisasContext
*ctx
)
5303 TCGLabel
*l1
= gen_new_label();
5304 TCGLabel
*l2
= gen_new_label();
5305 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5306 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5309 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5311 if (unlikely(Rc(ctx
->opcode
) != 0))
5312 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5315 /* nabso - nabso. */
5316 static void gen_nabso(DisasContext
*ctx
)
5318 TCGLabel
*l1
= gen_new_label();
5319 TCGLabel
*l2
= gen_new_label();
5320 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5321 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5324 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5326 /* nabs never overflows */
5327 tcg_gen_movi_tl(cpu_ov
, 0);
5328 if (unlikely(Rc(ctx
->opcode
) != 0))
5329 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5333 static void gen_rlmi(DisasContext
*ctx
)
5335 uint32_t mb
= MB(ctx
->opcode
);
5336 uint32_t me
= ME(ctx
->opcode
);
5337 TCGv t0
= tcg_temp_new();
5338 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5339 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5340 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5341 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
5342 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5344 if (unlikely(Rc(ctx
->opcode
) != 0))
5345 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5349 static void gen_rrib(DisasContext
*ctx
)
5351 TCGv t0
= tcg_temp_new();
5352 TCGv t1
= tcg_temp_new();
5353 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5354 tcg_gen_movi_tl(t1
, 0x80000000);
5355 tcg_gen_shr_tl(t1
, t1
, t0
);
5356 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5357 tcg_gen_and_tl(t0
, t0
, t1
);
5358 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5359 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5362 if (unlikely(Rc(ctx
->opcode
) != 0))
5363 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5367 static void gen_sle(DisasContext
*ctx
)
5369 TCGv t0
= tcg_temp_new();
5370 TCGv t1
= tcg_temp_new();
5371 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5372 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5373 tcg_gen_subfi_tl(t1
, 32, t1
);
5374 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5375 tcg_gen_or_tl(t1
, t0
, t1
);
5376 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5377 gen_store_spr(SPR_MQ
, t1
);
5380 if (unlikely(Rc(ctx
->opcode
) != 0))
5381 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5385 static void gen_sleq(DisasContext
*ctx
)
5387 TCGv t0
= tcg_temp_new();
5388 TCGv t1
= tcg_temp_new();
5389 TCGv t2
= tcg_temp_new();
5390 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5391 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5392 tcg_gen_shl_tl(t2
, t2
, t0
);
5393 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5394 gen_load_spr(t1
, SPR_MQ
);
5395 gen_store_spr(SPR_MQ
, t0
);
5396 tcg_gen_and_tl(t0
, t0
, t2
);
5397 tcg_gen_andc_tl(t1
, t1
, t2
);
5398 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5402 if (unlikely(Rc(ctx
->opcode
) != 0))
5403 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5407 static void gen_sliq(DisasContext
*ctx
)
5409 int sh
= SH(ctx
->opcode
);
5410 TCGv t0
= tcg_temp_new();
5411 TCGv t1
= tcg_temp_new();
5412 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5413 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5414 tcg_gen_or_tl(t1
, t0
, t1
);
5415 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5416 gen_store_spr(SPR_MQ
, t1
);
5419 if (unlikely(Rc(ctx
->opcode
) != 0))
5420 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5423 /* slliq - slliq. */
5424 static void gen_slliq(DisasContext
*ctx
)
5426 int sh
= SH(ctx
->opcode
);
5427 TCGv t0
= tcg_temp_new();
5428 TCGv t1
= tcg_temp_new();
5429 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5430 gen_load_spr(t1
, SPR_MQ
);
5431 gen_store_spr(SPR_MQ
, t0
);
5432 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5433 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5434 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5437 if (unlikely(Rc(ctx
->opcode
) != 0))
5438 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5442 static void gen_sllq(DisasContext
*ctx
)
5444 TCGLabel
*l1
= gen_new_label();
5445 TCGLabel
*l2
= gen_new_label();
5446 TCGv t0
= tcg_temp_local_new();
5447 TCGv t1
= tcg_temp_local_new();
5448 TCGv t2
= tcg_temp_local_new();
5449 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5450 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5451 tcg_gen_shl_tl(t1
, t1
, t2
);
5452 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5453 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5454 gen_load_spr(t0
, SPR_MQ
);
5455 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5458 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5459 gen_load_spr(t2
, SPR_MQ
);
5460 tcg_gen_andc_tl(t1
, t2
, t1
);
5461 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5466 if (unlikely(Rc(ctx
->opcode
) != 0))
5467 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5471 static void gen_slq(DisasContext
*ctx
)
5473 TCGLabel
*l1
= gen_new_label();
5474 TCGv t0
= tcg_temp_new();
5475 TCGv t1
= tcg_temp_new();
5476 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5477 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5478 tcg_gen_subfi_tl(t1
, 32, t1
);
5479 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5480 tcg_gen_or_tl(t1
, t0
, t1
);
5481 gen_store_spr(SPR_MQ
, t1
);
5482 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5483 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5484 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5485 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5489 if (unlikely(Rc(ctx
->opcode
) != 0))
5490 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5493 /* sraiq - sraiq. */
5494 static void gen_sraiq(DisasContext
*ctx
)
5496 int sh
= SH(ctx
->opcode
);
5497 TCGLabel
*l1
= gen_new_label();
5498 TCGv t0
= tcg_temp_new();
5499 TCGv t1
= tcg_temp_new();
5500 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5501 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5502 tcg_gen_or_tl(t0
, t0
, t1
);
5503 gen_store_spr(SPR_MQ
, t0
);
5504 tcg_gen_movi_tl(cpu_ca
, 0);
5505 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5506 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5507 tcg_gen_movi_tl(cpu_ca
, 1);
5509 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5512 if (unlikely(Rc(ctx
->opcode
) != 0))
5513 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5517 static void gen_sraq(DisasContext
*ctx
)
5519 TCGLabel
*l1
= gen_new_label();
5520 TCGLabel
*l2
= gen_new_label();
5521 TCGv t0
= tcg_temp_new();
5522 TCGv t1
= tcg_temp_local_new();
5523 TCGv t2
= tcg_temp_local_new();
5524 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5525 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5526 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5527 tcg_gen_subfi_tl(t2
, 32, t2
);
5528 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5529 tcg_gen_or_tl(t0
, t0
, t2
);
5530 gen_store_spr(SPR_MQ
, t0
);
5531 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5532 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5533 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5534 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5537 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5538 tcg_gen_movi_tl(cpu_ca
, 0);
5539 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5540 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5541 tcg_gen_movi_tl(cpu_ca
, 1);
5545 if (unlikely(Rc(ctx
->opcode
) != 0))
5546 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5550 static void gen_sre(DisasContext
*ctx
)
5552 TCGv t0
= tcg_temp_new();
5553 TCGv t1
= tcg_temp_new();
5554 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5555 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5556 tcg_gen_subfi_tl(t1
, 32, t1
);
5557 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5558 tcg_gen_or_tl(t1
, t0
, t1
);
5559 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5560 gen_store_spr(SPR_MQ
, t1
);
5563 if (unlikely(Rc(ctx
->opcode
) != 0))
5564 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5568 static void gen_srea(DisasContext
*ctx
)
5570 TCGv t0
= tcg_temp_new();
5571 TCGv t1
= tcg_temp_new();
5572 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5573 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5574 gen_store_spr(SPR_MQ
, t0
);
5575 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5578 if (unlikely(Rc(ctx
->opcode
) != 0))
5579 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5583 static void gen_sreq(DisasContext
*ctx
)
5585 TCGv t0
= tcg_temp_new();
5586 TCGv t1
= tcg_temp_new();
5587 TCGv t2
= tcg_temp_new();
5588 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5589 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5590 tcg_gen_shr_tl(t1
, t1
, t0
);
5591 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5592 gen_load_spr(t2
, SPR_MQ
);
5593 gen_store_spr(SPR_MQ
, t0
);
5594 tcg_gen_and_tl(t0
, t0
, t1
);
5595 tcg_gen_andc_tl(t2
, t2
, t1
);
5596 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5600 if (unlikely(Rc(ctx
->opcode
) != 0))
5601 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5605 static void gen_sriq(DisasContext
*ctx
)
5607 int sh
= SH(ctx
->opcode
);
5608 TCGv t0
= tcg_temp_new();
5609 TCGv t1
= tcg_temp_new();
5610 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5611 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5612 tcg_gen_or_tl(t1
, t0
, t1
);
5613 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5614 gen_store_spr(SPR_MQ
, t1
);
5617 if (unlikely(Rc(ctx
->opcode
) != 0))
5618 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5622 static void gen_srliq(DisasContext
*ctx
)
5624 int sh
= SH(ctx
->opcode
);
5625 TCGv t0
= tcg_temp_new();
5626 TCGv t1
= tcg_temp_new();
5627 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5628 gen_load_spr(t1
, SPR_MQ
);
5629 gen_store_spr(SPR_MQ
, t0
);
5630 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5631 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5632 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5635 if (unlikely(Rc(ctx
->opcode
) != 0))
5636 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5640 static void gen_srlq(DisasContext
*ctx
)
5642 TCGLabel
*l1
= gen_new_label();
5643 TCGLabel
*l2
= gen_new_label();
5644 TCGv t0
= tcg_temp_local_new();
5645 TCGv t1
= tcg_temp_local_new();
5646 TCGv t2
= tcg_temp_local_new();
5647 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5648 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5649 tcg_gen_shr_tl(t2
, t1
, t2
);
5650 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5651 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5652 gen_load_spr(t0
, SPR_MQ
);
5653 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5656 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5657 tcg_gen_and_tl(t0
, t0
, t2
);
5658 gen_load_spr(t1
, SPR_MQ
);
5659 tcg_gen_andc_tl(t1
, t1
, t2
);
5660 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5665 if (unlikely(Rc(ctx
->opcode
) != 0))
5666 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5670 static void gen_srq(DisasContext
*ctx
)
5672 TCGLabel
*l1
= gen_new_label();
5673 TCGv t0
= tcg_temp_new();
5674 TCGv t1
= tcg_temp_new();
5675 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5676 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5677 tcg_gen_subfi_tl(t1
, 32, t1
);
5678 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5679 tcg_gen_or_tl(t1
, t0
, t1
);
5680 gen_store_spr(SPR_MQ
, t1
);
5681 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5682 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5683 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5684 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5688 if (unlikely(Rc(ctx
->opcode
) != 0))
5689 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5692 /* PowerPC 602 specific instructions */
5695 static void gen_dsa(DisasContext
*ctx
)
5698 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5702 static void gen_esa(DisasContext
*ctx
)
5705 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5709 static void gen_mfrom(DisasContext
*ctx
)
5711 #if defined(CONFIG_USER_ONLY)
5712 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5714 if (unlikely(ctx
->pr
)) {
5715 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5718 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5722 /* 602 - 603 - G2 TLB management */
5725 static void gen_tlbld_6xx(DisasContext
*ctx
)
5727 #if defined(CONFIG_USER_ONLY)
5728 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5730 if (unlikely(ctx
->pr
)) {
5731 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5734 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5739 static void gen_tlbli_6xx(DisasContext
*ctx
)
5741 #if defined(CONFIG_USER_ONLY)
5742 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5744 if (unlikely(ctx
->pr
)) {
5745 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5748 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5752 /* 74xx TLB management */
5755 static void gen_tlbld_74xx(DisasContext
*ctx
)
5757 #if defined(CONFIG_USER_ONLY)
5758 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5760 if (unlikely(ctx
->pr
)) {
5761 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5764 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5769 static void gen_tlbli_74xx(DisasContext
*ctx
)
5771 #if defined(CONFIG_USER_ONLY)
5772 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5774 if (unlikely(ctx
->pr
)) {
5775 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5778 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5782 /* POWER instructions not in PowerPC 601 */
5785 static void gen_clf(DisasContext
*ctx
)
5787 /* Cache line flush: implemented as no-op */
5791 static void gen_cli(DisasContext
*ctx
)
5793 /* Cache line invalidate: privileged and treated as no-op */
5794 #if defined(CONFIG_USER_ONLY)
5795 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5797 if (unlikely(ctx
->pr
)) {
5798 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5805 static void gen_dclst(DisasContext
*ctx
)
5807 /* Data cache line store: treated as no-op */
5810 static void gen_mfsri(DisasContext
*ctx
)
5812 #if defined(CONFIG_USER_ONLY)
5813 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5815 int ra
= rA(ctx
->opcode
);
5816 int rd
= rD(ctx
->opcode
);
5818 if (unlikely(ctx
->pr
)) {
5819 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5822 t0
= tcg_temp_new();
5823 gen_addr_reg_index(ctx
, t0
);
5824 tcg_gen_shri_tl(t0
, t0
, 28);
5825 tcg_gen_andi_tl(t0
, t0
, 0xF);
5826 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5828 if (ra
!= 0 && ra
!= rd
)
5829 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5833 static void gen_rac(DisasContext
*ctx
)
5835 #if defined(CONFIG_USER_ONLY)
5836 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5839 if (unlikely(ctx
->pr
)) {
5840 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5843 t0
= tcg_temp_new();
5844 gen_addr_reg_index(ctx
, t0
);
5845 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5850 static void gen_rfsvc(DisasContext
*ctx
)
5852 #if defined(CONFIG_USER_ONLY)
5853 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5855 if (unlikely(ctx
->pr
)) {
5856 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
5859 gen_helper_rfsvc(cpu_env
);
5860 gen_sync_exception(ctx
);
5864 /* svc is not implemented for now */
5866 /* POWER2 specific instructions */
5867 /* Quad manipulation (load/store two floats at a time) */
5870 static void gen_lfq(DisasContext
*ctx
)
5872 int rd
= rD(ctx
->opcode
);
5874 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5875 t0
= tcg_temp_new();
5876 gen_addr_imm_index(ctx
, t0
, 0);
5877 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5878 gen_addr_add(ctx
, t0
, t0
, 8);
5879 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5884 static void gen_lfqu(DisasContext
*ctx
)
5886 int ra
= rA(ctx
->opcode
);
5887 int rd
= rD(ctx
->opcode
);
5889 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5890 t0
= tcg_temp_new();
5891 t1
= tcg_temp_new();
5892 gen_addr_imm_index(ctx
, t0
, 0);
5893 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5894 gen_addr_add(ctx
, t1
, t0
, 8);
5895 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5897 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5903 static void gen_lfqux(DisasContext
*ctx
)
5905 int ra
= rA(ctx
->opcode
);
5906 int rd
= rD(ctx
->opcode
);
5907 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5909 t0
= tcg_temp_new();
5910 gen_addr_reg_index(ctx
, t0
);
5911 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5912 t1
= tcg_temp_new();
5913 gen_addr_add(ctx
, t1
, t0
, 8);
5914 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5917 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5922 static void gen_lfqx(DisasContext
*ctx
)
5924 int rd
= rD(ctx
->opcode
);
5926 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5927 t0
= tcg_temp_new();
5928 gen_addr_reg_index(ctx
, t0
);
5929 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5930 gen_addr_add(ctx
, t0
, t0
, 8);
5931 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5936 static void gen_stfq(DisasContext
*ctx
)
5938 int rd
= rD(ctx
->opcode
);
5940 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5941 t0
= tcg_temp_new();
5942 gen_addr_imm_index(ctx
, t0
, 0);
5943 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5944 gen_addr_add(ctx
, t0
, t0
, 8);
5945 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5950 static void gen_stfqu(DisasContext
*ctx
)
5952 int ra
= rA(ctx
->opcode
);
5953 int rd
= rD(ctx
->opcode
);
5955 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5956 t0
= tcg_temp_new();
5957 gen_addr_imm_index(ctx
, t0
, 0);
5958 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5959 t1
= tcg_temp_new();
5960 gen_addr_add(ctx
, t1
, t0
, 8);
5961 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5964 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5969 static void gen_stfqux(DisasContext
*ctx
)
5971 int ra
= rA(ctx
->opcode
);
5972 int rd
= rD(ctx
->opcode
);
5974 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5975 t0
= tcg_temp_new();
5976 gen_addr_reg_index(ctx
, t0
);
5977 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5978 t1
= tcg_temp_new();
5979 gen_addr_add(ctx
, t1
, t0
, 8);
5980 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5983 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5988 static void gen_stfqx(DisasContext
*ctx
)
5990 int rd
= rD(ctx
->opcode
);
5992 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5993 t0
= tcg_temp_new();
5994 gen_addr_reg_index(ctx
, t0
);
5995 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5996 gen_addr_add(ctx
, t0
, t0
, 8);
5997 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
6001 /* BookE specific instructions */
6003 /* XXX: not implemented on 440 ? */
6004 static void gen_mfapidi(DisasContext
*ctx
)
6007 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6010 /* XXX: not implemented on 440 ? */
6011 static void gen_tlbiva(DisasContext
*ctx
)
6013 #if defined(CONFIG_USER_ONLY)
6014 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6017 if (unlikely(ctx
->pr
)) {
6018 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6021 t0
= tcg_temp_new();
6022 gen_addr_reg_index(ctx
, t0
);
6023 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6028 /* All 405 MAC instructions are translated here */
6029 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
6030 int ra
, int rb
, int rt
, int Rc
)
6034 t0
= tcg_temp_local_new();
6035 t1
= tcg_temp_local_new();
6037 switch (opc3
& 0x0D) {
6039 /* macchw - macchw. - macchwo - macchwo. */
6040 /* macchws - macchws. - macchwso - macchwso. */
6041 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6042 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6043 /* mulchw - mulchw. */
6044 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6045 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6046 tcg_gen_ext16s_tl(t1
, t1
);
6049 /* macchwu - macchwu. - macchwuo - macchwuo. */
6050 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6051 /* mulchwu - mulchwu. */
6052 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6053 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6054 tcg_gen_ext16u_tl(t1
, t1
);
6057 /* machhw - machhw. - machhwo - machhwo. */
6058 /* machhws - machhws. - machhwso - machhwso. */
6059 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6060 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6061 /* mulhhw - mulhhw. */
6062 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
6063 tcg_gen_ext16s_tl(t0
, t0
);
6064 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6065 tcg_gen_ext16s_tl(t1
, t1
);
6068 /* machhwu - machhwu. - machhwuo - machhwuo. */
6069 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6070 /* mulhhwu - mulhhwu. */
6071 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
6072 tcg_gen_ext16u_tl(t0
, t0
);
6073 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6074 tcg_gen_ext16u_tl(t1
, t1
);
6077 /* maclhw - maclhw. - maclhwo - maclhwo. */
6078 /* maclhws - maclhws. - maclhwso - maclhwso. */
6079 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6080 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6081 /* mullhw - mullhw. */
6082 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6083 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
6086 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6087 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6088 /* mullhwu - mullhwu. */
6089 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6090 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
6094 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6095 tcg_gen_mul_tl(t1
, t0
, t1
);
6097 /* nmultiply-and-accumulate (0x0E) */
6098 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
6100 /* multiply-and-accumulate (0x0C) */
6101 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
6105 /* Check overflow and/or saturate */
6106 TCGLabel
*l1
= gen_new_label();
6109 /* Start with XER OV disabled, the most likely case */
6110 tcg_gen_movi_tl(cpu_ov
, 0);
6114 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
6115 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
6116 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
6117 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
6120 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
6121 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6125 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6128 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6132 /* Check overflow */
6133 tcg_gen_movi_tl(cpu_ov
, 1);
6134 tcg_gen_movi_tl(cpu_so
, 1);
6137 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6140 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6144 if (unlikely(Rc
) != 0) {
6146 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6150 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6151 static void glue(gen_, name)(DisasContext *ctx) \
6153 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6154 rD(ctx->opcode), Rc(ctx->opcode)); \
6157 /* macchw - macchw. */
6158 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6159 /* macchwo - macchwo. */
6160 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6161 /* macchws - macchws. */
6162 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6163 /* macchwso - macchwso. */
6164 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6165 /* macchwsu - macchwsu. */
6166 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6167 /* macchwsuo - macchwsuo. */
6168 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6169 /* macchwu - macchwu. */
6170 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6171 /* macchwuo - macchwuo. */
6172 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6173 /* machhw - machhw. */
6174 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6175 /* machhwo - machhwo. */
6176 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6177 /* machhws - machhws. */
6178 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6179 /* machhwso - machhwso. */
6180 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6181 /* machhwsu - machhwsu. */
6182 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6183 /* machhwsuo - machhwsuo. */
6184 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6185 /* machhwu - machhwu. */
6186 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6187 /* machhwuo - machhwuo. */
6188 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6189 /* maclhw - maclhw. */
6190 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6191 /* maclhwo - maclhwo. */
6192 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6193 /* maclhws - maclhws. */
6194 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6195 /* maclhwso - maclhwso. */
6196 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6197 /* maclhwu - maclhwu. */
6198 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6199 /* maclhwuo - maclhwuo. */
6200 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6201 /* maclhwsu - maclhwsu. */
6202 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6203 /* maclhwsuo - maclhwsuo. */
6204 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6205 /* nmacchw - nmacchw. */
6206 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6207 /* nmacchwo - nmacchwo. */
6208 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6209 /* nmacchws - nmacchws. */
6210 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6211 /* nmacchwso - nmacchwso. */
6212 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6213 /* nmachhw - nmachhw. */
6214 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6215 /* nmachhwo - nmachhwo. */
6216 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6217 /* nmachhws - nmachhws. */
6218 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6219 /* nmachhwso - nmachhwso. */
6220 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6221 /* nmaclhw - nmaclhw. */
6222 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6223 /* nmaclhwo - nmaclhwo. */
6224 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6225 /* nmaclhws - nmaclhws. */
6226 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6227 /* nmaclhwso - nmaclhwso. */
6228 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6230 /* mulchw - mulchw. */
6231 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6232 /* mulchwu - mulchwu. */
6233 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6234 /* mulhhw - mulhhw. */
6235 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6236 /* mulhhwu - mulhhwu. */
6237 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6238 /* mullhw - mullhw. */
6239 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6240 /* mullhwu - mullhwu. */
6241 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6244 static void gen_mfdcr(DisasContext
*ctx
)
6246 #if defined(CONFIG_USER_ONLY)
6247 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6250 if (unlikely(ctx
->pr
)) {
6251 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6254 /* NIP cannot be restored if the memory exception comes from an helper */
6255 gen_update_nip(ctx
, ctx
->nip
- 4);
6256 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6257 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6258 tcg_temp_free(dcrn
);
6263 static void gen_mtdcr(DisasContext
*ctx
)
6265 #if defined(CONFIG_USER_ONLY)
6266 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6269 if (unlikely(ctx
->pr
)) {
6270 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6273 /* NIP cannot be restored if the memory exception comes from an helper */
6274 gen_update_nip(ctx
, ctx
->nip
- 4);
6275 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6276 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6277 tcg_temp_free(dcrn
);
6282 /* XXX: not implemented on 440 ? */
6283 static void gen_mfdcrx(DisasContext
*ctx
)
6285 #if defined(CONFIG_USER_ONLY)
6286 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6288 if (unlikely(ctx
->pr
)) {
6289 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6292 /* NIP cannot be restored if the memory exception comes from an helper */
6293 gen_update_nip(ctx
, ctx
->nip
- 4);
6294 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6295 cpu_gpr
[rA(ctx
->opcode
)]);
6296 /* Note: Rc update flag set leads to undefined state of Rc0 */
6301 /* XXX: not implemented on 440 ? */
6302 static void gen_mtdcrx(DisasContext
*ctx
)
6304 #if defined(CONFIG_USER_ONLY)
6305 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6307 if (unlikely(ctx
->pr
)) {
6308 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
6311 /* NIP cannot be restored if the memory exception comes from an helper */
6312 gen_update_nip(ctx
, ctx
->nip
- 4);
6313 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6314 cpu_gpr
[rS(ctx
->opcode
)]);
6315 /* Note: Rc update flag set leads to undefined state of Rc0 */
6319 /* mfdcrux (PPC 460) : user-mode access to DCR */
6320 static void gen_mfdcrux(DisasContext
*ctx
)
6322 /* NIP cannot be restored if the memory exception comes from an helper */
6323 gen_update_nip(ctx
, ctx
->nip
- 4);
6324 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6325 cpu_gpr
[rA(ctx
->opcode
)]);
6326 /* Note: Rc update flag set leads to undefined state of Rc0 */
6329 /* mtdcrux (PPC 460) : user-mode access to DCR */
6330 static void gen_mtdcrux(DisasContext
*ctx
)
6332 /* NIP cannot be restored if the memory exception comes from an helper */
6333 gen_update_nip(ctx
, ctx
->nip
- 4);
6334 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6335 cpu_gpr
[rS(ctx
->opcode
)]);
6336 /* Note: Rc update flag set leads to undefined state of Rc0 */
6340 static void gen_dccci(DisasContext
*ctx
)
6342 #if defined(CONFIG_USER_ONLY)
6343 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6345 if (unlikely(ctx
->pr
)) {
6346 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6349 /* interpreted as no-op */
6354 static void gen_dcread(DisasContext
*ctx
)
6356 #if defined(CONFIG_USER_ONLY)
6357 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6360 if (unlikely(ctx
->pr
)) {
6361 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6364 gen_set_access_type(ctx
, ACCESS_CACHE
);
6365 EA
= tcg_temp_new();
6366 gen_addr_reg_index(ctx
, EA
);
6367 val
= tcg_temp_new();
6368 gen_qemu_ld32u(ctx
, val
, EA
);
6370 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6376 static void gen_icbt_40x(DisasContext
*ctx
)
6378 /* interpreted as no-op */
6379 /* XXX: specification say this is treated as a load by the MMU
6380 * but does not generate any exception
6385 static void gen_iccci(DisasContext
*ctx
)
6387 #if defined(CONFIG_USER_ONLY)
6388 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6390 if (unlikely(ctx
->pr
)) {
6391 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6394 /* interpreted as no-op */
6399 static void gen_icread(DisasContext
*ctx
)
6401 #if defined(CONFIG_USER_ONLY)
6402 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6404 if (unlikely(ctx
->pr
)) {
6405 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6408 /* interpreted as no-op */
6412 /* rfci (supervisor only) */
6413 static void gen_rfci_40x(DisasContext
*ctx
)
6415 #if defined(CONFIG_USER_ONLY)
6416 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6418 if (unlikely(ctx
->pr
)) {
6419 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6422 /* Restore CPU state */
6423 gen_helper_40x_rfci(cpu_env
);
6424 gen_sync_exception(ctx
);
6428 static void gen_rfci(DisasContext
*ctx
)
6430 #if defined(CONFIG_USER_ONLY)
6431 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6433 if (unlikely(ctx
->pr
)) {
6434 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6437 /* Restore CPU state */
6438 gen_helper_rfci(cpu_env
);
6439 gen_sync_exception(ctx
);
6443 /* BookE specific */
6445 /* XXX: not implemented on 440 ? */
6446 static void gen_rfdi(DisasContext
*ctx
)
6448 #if defined(CONFIG_USER_ONLY)
6449 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6451 if (unlikely(ctx
->pr
)) {
6452 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6455 /* Restore CPU state */
6456 gen_helper_rfdi(cpu_env
);
6457 gen_sync_exception(ctx
);
6461 /* XXX: not implemented on 440 ? */
6462 static void gen_rfmci(DisasContext
*ctx
)
6464 #if defined(CONFIG_USER_ONLY)
6465 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6467 if (unlikely(ctx
->pr
)) {
6468 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6471 /* Restore CPU state */
6472 gen_helper_rfmci(cpu_env
);
6473 gen_sync_exception(ctx
);
6477 /* TLB management - PowerPC 405 implementation */
6480 static void gen_tlbre_40x(DisasContext
*ctx
)
6482 #if defined(CONFIG_USER_ONLY)
6483 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6485 if (unlikely(ctx
->pr
)) {
6486 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6489 switch (rB(ctx
->opcode
)) {
6491 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6492 cpu_gpr
[rA(ctx
->opcode
)]);
6495 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6496 cpu_gpr
[rA(ctx
->opcode
)]);
6499 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6505 /* tlbsx - tlbsx. */
6506 static void gen_tlbsx_40x(DisasContext
*ctx
)
6508 #if defined(CONFIG_USER_ONLY)
6509 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6512 if (unlikely(ctx
->pr
)) {
6513 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6516 t0
= tcg_temp_new();
6517 gen_addr_reg_index(ctx
, t0
);
6518 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6520 if (Rc(ctx
->opcode
)) {
6521 TCGLabel
*l1
= gen_new_label();
6522 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6523 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6524 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6531 static void gen_tlbwe_40x(DisasContext
*ctx
)
6533 #if defined(CONFIG_USER_ONLY)
6534 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6536 if (unlikely(ctx
->pr
)) {
6537 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6540 switch (rB(ctx
->opcode
)) {
6542 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6543 cpu_gpr
[rS(ctx
->opcode
)]);
6546 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6547 cpu_gpr
[rS(ctx
->opcode
)]);
6550 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6556 /* TLB management - PowerPC 440 implementation */
6559 static void gen_tlbre_440(DisasContext
*ctx
)
6561 #if defined(CONFIG_USER_ONLY)
6562 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6564 if (unlikely(ctx
->pr
)) {
6565 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6568 switch (rB(ctx
->opcode
)) {
6573 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6574 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6575 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6576 tcg_temp_free_i32(t0
);
6580 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6586 /* tlbsx - tlbsx. */
6587 static void gen_tlbsx_440(DisasContext
*ctx
)
6589 #if defined(CONFIG_USER_ONLY)
6590 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6593 if (unlikely(ctx
->pr
)) {
6594 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6597 t0
= tcg_temp_new();
6598 gen_addr_reg_index(ctx
, t0
);
6599 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6601 if (Rc(ctx
->opcode
)) {
6602 TCGLabel
*l1
= gen_new_label();
6603 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6604 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6605 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6612 static void gen_tlbwe_440(DisasContext
*ctx
)
6614 #if defined(CONFIG_USER_ONLY)
6615 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6617 if (unlikely(ctx
->pr
)) {
6618 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6621 switch (rB(ctx
->opcode
)) {
6626 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6627 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6628 cpu_gpr
[rS(ctx
->opcode
)]);
6629 tcg_temp_free_i32(t0
);
6633 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6639 /* TLB management - PowerPC BookE 2.06 implementation */
6642 static void gen_tlbre_booke206(DisasContext
*ctx
)
6644 #if defined(CONFIG_USER_ONLY)
6645 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6647 if (unlikely(ctx
->pr
)) {
6648 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6652 gen_helper_booke206_tlbre(cpu_env
);
6656 /* tlbsx - tlbsx. */
6657 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6659 #if defined(CONFIG_USER_ONLY)
6660 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6663 if (unlikely(ctx
->pr
)) {
6664 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6668 if (rA(ctx
->opcode
)) {
6669 t0
= tcg_temp_new();
6670 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6672 t0
= tcg_const_tl(0);
6675 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6676 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6682 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6684 #if defined(CONFIG_USER_ONLY)
6685 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6687 if (unlikely(ctx
->pr
)) {
6688 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6691 gen_update_nip(ctx
, ctx
->nip
- 4);
6692 gen_helper_booke206_tlbwe(cpu_env
);
6696 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6698 #if defined(CONFIG_USER_ONLY)
6699 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6702 if (unlikely(ctx
->pr
)) {
6703 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6707 t0
= tcg_temp_new();
6708 gen_addr_reg_index(ctx
, t0
);
6710 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6715 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6717 #if defined(CONFIG_USER_ONLY)
6718 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6721 if (unlikely(ctx
->pr
)) {
6722 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6726 t0
= tcg_temp_new();
6727 gen_addr_reg_index(ctx
, t0
);
6729 switch((ctx
->opcode
>> 21) & 0x3) {
6731 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6734 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6737 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6740 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6750 static void gen_wrtee(DisasContext
*ctx
)
6752 #if defined(CONFIG_USER_ONLY)
6753 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6756 if (unlikely(ctx
->pr
)) {
6757 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6760 t0
= tcg_temp_new();
6761 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6762 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6763 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6765 /* Stop translation to have a chance to raise an exception
6766 * if we just set msr_ee to 1
6768 gen_stop_exception(ctx
);
6773 static void gen_wrteei(DisasContext
*ctx
)
6775 #if defined(CONFIG_USER_ONLY)
6776 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6778 if (unlikely(ctx
->pr
)) {
6779 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6782 if (ctx
->opcode
& 0x00008000) {
6783 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6784 /* Stop translation to have a chance to raise an exception */
6785 gen_stop_exception(ctx
);
6787 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6792 /* PowerPC 440 specific instructions */
6795 static void gen_dlmzb(DisasContext
*ctx
)
6797 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6798 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6799 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6800 tcg_temp_free_i32(t0
);
6803 /* mbar replaces eieio on 440 */
6804 static void gen_mbar(DisasContext
*ctx
)
6806 /* interpreted as no-op */
6809 /* msync replaces sync on 440 */
6810 static void gen_msync_4xx(DisasContext
*ctx
)
6812 /* interpreted as no-op */
6816 static void gen_icbt_440(DisasContext
*ctx
)
6818 /* interpreted as no-op */
6819 /* XXX: specification say this is treated as a load by the MMU
6820 * but does not generate any exception
6824 /* Embedded.Processor Control */
6826 static void gen_msgclr(DisasContext
*ctx
)
6828 #if defined(CONFIG_USER_ONLY)
6829 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6831 if (unlikely(ctx
->pr
)) {
6832 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6836 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6840 static void gen_msgsnd(DisasContext
*ctx
)
6842 #if defined(CONFIG_USER_ONLY)
6843 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6845 if (unlikely(ctx
->pr
)) {
6846 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
6850 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6854 /*** Altivec vector extension ***/
6855 /* Altivec registers moves */
6857 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6859 TCGv_ptr r
= tcg_temp_new_ptr();
6860 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6864 #define GEN_VR_LDX(name, opc2, opc3) \
6865 static void glue(gen_, name)(DisasContext *ctx) \
6868 if (unlikely(!ctx->altivec_enabled)) { \
6869 gen_exception(ctx, POWERPC_EXCP_VPU); \
6872 gen_set_access_type(ctx, ACCESS_INT); \
6873 EA = tcg_temp_new(); \
6874 gen_addr_reg_index(ctx, EA); \
6875 tcg_gen_andi_tl(EA, EA, ~0xf); \
6876 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6877 64-bit byteswap already. */ \
6878 if (ctx->le_mode) { \
6879 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6880 tcg_gen_addi_tl(EA, EA, 8); \
6881 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6883 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6884 tcg_gen_addi_tl(EA, EA, 8); \
6885 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6887 tcg_temp_free(EA); \
6890 #define GEN_VR_STX(name, opc2, opc3) \
6891 static void gen_st##name(DisasContext *ctx) \
6894 if (unlikely(!ctx->altivec_enabled)) { \
6895 gen_exception(ctx, POWERPC_EXCP_VPU); \
6898 gen_set_access_type(ctx, ACCESS_INT); \
6899 EA = tcg_temp_new(); \
6900 gen_addr_reg_index(ctx, EA); \
6901 tcg_gen_andi_tl(EA, EA, ~0xf); \
6902 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6903 64-bit byteswap already. */ \
6904 if (ctx->le_mode) { \
6905 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6906 tcg_gen_addi_tl(EA, EA, 8); \
6907 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6909 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6910 tcg_gen_addi_tl(EA, EA, 8); \
6911 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6913 tcg_temp_free(EA); \
6916 #define GEN_VR_LVE(name, opc2, opc3, size) \
6917 static void gen_lve##name(DisasContext *ctx) \
6921 if (unlikely(!ctx->altivec_enabled)) { \
6922 gen_exception(ctx, POWERPC_EXCP_VPU); \
6925 gen_set_access_type(ctx, ACCESS_INT); \
6926 EA = tcg_temp_new(); \
6927 gen_addr_reg_index(ctx, EA); \
6929 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6931 rs = gen_avr_ptr(rS(ctx->opcode)); \
6932 gen_helper_lve##name(cpu_env, rs, EA); \
6933 tcg_temp_free(EA); \
6934 tcg_temp_free_ptr(rs); \
6937 #define GEN_VR_STVE(name, opc2, opc3, size) \
6938 static void gen_stve##name(DisasContext *ctx) \
6942 if (unlikely(!ctx->altivec_enabled)) { \
6943 gen_exception(ctx, POWERPC_EXCP_VPU); \
6946 gen_set_access_type(ctx, ACCESS_INT); \
6947 EA = tcg_temp_new(); \
6948 gen_addr_reg_index(ctx, EA); \
6950 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6952 rs = gen_avr_ptr(rS(ctx->opcode)); \
6953 gen_helper_stve##name(cpu_env, rs, EA); \
6954 tcg_temp_free(EA); \
6955 tcg_temp_free_ptr(rs); \
6958 GEN_VR_LDX(lvx
, 0x07, 0x03);
6959 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6960 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6962 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
6963 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
6964 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
6966 GEN_VR_STX(svx
, 0x07, 0x07);
6967 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6968 GEN_VR_STX(svxl
, 0x07, 0x0F);
6970 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
6971 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
6972 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
6974 static void gen_lvsl(DisasContext
*ctx
)
6978 if (unlikely(!ctx
->altivec_enabled
)) {
6979 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6982 EA
= tcg_temp_new();
6983 gen_addr_reg_index(ctx
, EA
);
6984 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6985 gen_helper_lvsl(rd
, EA
);
6987 tcg_temp_free_ptr(rd
);
6990 static void gen_lvsr(DisasContext
*ctx
)
6994 if (unlikely(!ctx
->altivec_enabled
)) {
6995 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6998 EA
= tcg_temp_new();
6999 gen_addr_reg_index(ctx
, EA
);
7000 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7001 gen_helper_lvsr(rd
, EA
);
7003 tcg_temp_free_ptr(rd
);
7006 static void gen_mfvscr(DisasContext
*ctx
)
7009 if (unlikely(!ctx
->altivec_enabled
)) {
7010 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7013 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
7014 t
= tcg_temp_new_i32();
7015 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
7016 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
7017 tcg_temp_free_i32(t
);
7020 static void gen_mtvscr(DisasContext
*ctx
)
7023 if (unlikely(!ctx
->altivec_enabled
)) {
7024 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7027 p
= gen_avr_ptr(rB(ctx
->opcode
));
7028 gen_helper_mtvscr(cpu_env
, p
);
7029 tcg_temp_free_ptr(p
);
7032 /* Logical operations */
7033 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7034 static void glue(gen_, name)(DisasContext *ctx) \
7036 if (unlikely(!ctx->altivec_enabled)) { \
7037 gen_exception(ctx, POWERPC_EXCP_VPU); \
7040 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7041 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7044 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
7045 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
7046 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
7047 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
7048 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
7049 GEN_VX_LOGICAL(veqv
, tcg_gen_eqv_i64
, 2, 26);
7050 GEN_VX_LOGICAL(vnand
, tcg_gen_nand_i64
, 2, 22);
7051 GEN_VX_LOGICAL(vorc
, tcg_gen_orc_i64
, 2, 21);
7053 #define GEN_VXFORM(name, opc2, opc3) \
7054 static void glue(gen_, name)(DisasContext *ctx) \
7056 TCGv_ptr ra, rb, rd; \
7057 if (unlikely(!ctx->altivec_enabled)) { \
7058 gen_exception(ctx, POWERPC_EXCP_VPU); \
7061 ra = gen_avr_ptr(rA(ctx->opcode)); \
7062 rb = gen_avr_ptr(rB(ctx->opcode)); \
7063 rd = gen_avr_ptr(rD(ctx->opcode)); \
7064 gen_helper_##name (rd, ra, rb); \
7065 tcg_temp_free_ptr(ra); \
7066 tcg_temp_free_ptr(rb); \
7067 tcg_temp_free_ptr(rd); \
7070 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7071 static void glue(gen_, name)(DisasContext *ctx) \
7073 TCGv_ptr ra, rb, rd; \
7074 if (unlikely(!ctx->altivec_enabled)) { \
7075 gen_exception(ctx, POWERPC_EXCP_VPU); \
7078 ra = gen_avr_ptr(rA(ctx->opcode)); \
7079 rb = gen_avr_ptr(rB(ctx->opcode)); \
7080 rd = gen_avr_ptr(rD(ctx->opcode)); \
7081 gen_helper_##name(cpu_env, rd, ra, rb); \
7082 tcg_temp_free_ptr(ra); \
7083 tcg_temp_free_ptr(rb); \
7084 tcg_temp_free_ptr(rd); \
7087 #define GEN_VXFORM3(name, opc2, opc3) \
7088 static void glue(gen_, name)(DisasContext *ctx) \
7090 TCGv_ptr ra, rb, rc, rd; \
7091 if (unlikely(!ctx->altivec_enabled)) { \
7092 gen_exception(ctx, POWERPC_EXCP_VPU); \
7095 ra = gen_avr_ptr(rA(ctx->opcode)); \
7096 rb = gen_avr_ptr(rB(ctx->opcode)); \
7097 rc = gen_avr_ptr(rC(ctx->opcode)); \
7098 rd = gen_avr_ptr(rD(ctx->opcode)); \
7099 gen_helper_##name(rd, ra, rb, rc); \
7100 tcg_temp_free_ptr(ra); \
7101 tcg_temp_free_ptr(rb); \
7102 tcg_temp_free_ptr(rc); \
7103 tcg_temp_free_ptr(rd); \
7107 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7108 * an opcode bit. In general, these pairs come from different
7109 * versions of the ISA, so we must also support a pair of flags for
7112 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7113 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7115 if ((Rc(ctx->opcode) == 0) && \
7116 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7118 } else if ((Rc(ctx->opcode) == 1) && \
7119 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7122 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7126 GEN_VXFORM(vaddubm
, 0, 0);
7127 GEN_VXFORM(vadduhm
, 0, 1);
7128 GEN_VXFORM(vadduwm
, 0, 2);
7129 GEN_VXFORM(vaddudm
, 0, 3);
7130 GEN_VXFORM(vsububm
, 0, 16);
7131 GEN_VXFORM(vsubuhm
, 0, 17);
7132 GEN_VXFORM(vsubuwm
, 0, 18);
7133 GEN_VXFORM(vsubudm
, 0, 19);
7134 GEN_VXFORM(vmaxub
, 1, 0);
7135 GEN_VXFORM(vmaxuh
, 1, 1);
7136 GEN_VXFORM(vmaxuw
, 1, 2);
7137 GEN_VXFORM(vmaxud
, 1, 3);
7138 GEN_VXFORM(vmaxsb
, 1, 4);
7139 GEN_VXFORM(vmaxsh
, 1, 5);
7140 GEN_VXFORM(vmaxsw
, 1, 6);
7141 GEN_VXFORM(vmaxsd
, 1, 7);
7142 GEN_VXFORM(vminub
, 1, 8);
7143 GEN_VXFORM(vminuh
, 1, 9);
7144 GEN_VXFORM(vminuw
, 1, 10);
7145 GEN_VXFORM(vminud
, 1, 11);
7146 GEN_VXFORM(vminsb
, 1, 12);
7147 GEN_VXFORM(vminsh
, 1, 13);
7148 GEN_VXFORM(vminsw
, 1, 14);
7149 GEN_VXFORM(vminsd
, 1, 15);
7150 GEN_VXFORM(vavgub
, 1, 16);
7151 GEN_VXFORM(vavguh
, 1, 17);
7152 GEN_VXFORM(vavguw
, 1, 18);
7153 GEN_VXFORM(vavgsb
, 1, 20);
7154 GEN_VXFORM(vavgsh
, 1, 21);
7155 GEN_VXFORM(vavgsw
, 1, 22);
7156 GEN_VXFORM(vmrghb
, 6, 0);
7157 GEN_VXFORM(vmrghh
, 6, 1);
7158 GEN_VXFORM(vmrghw
, 6, 2);
7159 GEN_VXFORM(vmrglb
, 6, 4);
7160 GEN_VXFORM(vmrglh
, 6, 5);
7161 GEN_VXFORM(vmrglw
, 6, 6);
7163 static void gen_vmrgew(DisasContext
*ctx
)
7167 if (unlikely(!ctx
->altivec_enabled
)) {
7168 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7171 VT
= rD(ctx
->opcode
);
7172 VA
= rA(ctx
->opcode
);
7173 VB
= rB(ctx
->opcode
);
7174 tmp
= tcg_temp_new_i64();
7175 tcg_gen_shri_i64(tmp
, cpu_avrh
[VB
], 32);
7176 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VA
], tmp
, 0, 32);
7177 tcg_gen_shri_i64(tmp
, cpu_avrl
[VB
], 32);
7178 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VA
], tmp
, 0, 32);
7179 tcg_temp_free_i64(tmp
);
7182 static void gen_vmrgow(DisasContext
*ctx
)
7185 if (unlikely(!ctx
->altivec_enabled
)) {
7186 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7189 VT
= rD(ctx
->opcode
);
7190 VA
= rA(ctx
->opcode
);
7191 VB
= rB(ctx
->opcode
);
7193 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VB
], cpu_avrh
[VA
], 32, 32);
7194 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VB
], cpu_avrl
[VA
], 32, 32);
7197 GEN_VXFORM(vmuloub
, 4, 0);
7198 GEN_VXFORM(vmulouh
, 4, 1);
7199 GEN_VXFORM(vmulouw
, 4, 2);
7200 GEN_VXFORM(vmuluwm
, 4, 2);
7201 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
7202 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
7203 GEN_VXFORM(vmulosb
, 4, 4);
7204 GEN_VXFORM(vmulosh
, 4, 5);
7205 GEN_VXFORM(vmulosw
, 4, 6);
7206 GEN_VXFORM(vmuleub
, 4, 8);
7207 GEN_VXFORM(vmuleuh
, 4, 9);
7208 GEN_VXFORM(vmuleuw
, 4, 10);
7209 GEN_VXFORM(vmulesb
, 4, 12);
7210 GEN_VXFORM(vmulesh
, 4, 13);
7211 GEN_VXFORM(vmulesw
, 4, 14);
7212 GEN_VXFORM(vslb
, 2, 4);
7213 GEN_VXFORM(vslh
, 2, 5);
7214 GEN_VXFORM(vslw
, 2, 6);
7215 GEN_VXFORM(vsld
, 2, 23);
7216 GEN_VXFORM(vsrb
, 2, 8);
7217 GEN_VXFORM(vsrh
, 2, 9);
7218 GEN_VXFORM(vsrw
, 2, 10);
7219 GEN_VXFORM(vsrd
, 2, 27);
7220 GEN_VXFORM(vsrab
, 2, 12);
7221 GEN_VXFORM(vsrah
, 2, 13);
7222 GEN_VXFORM(vsraw
, 2, 14);
7223 GEN_VXFORM(vsrad
, 2, 15);
7224 GEN_VXFORM(vslo
, 6, 16);
7225 GEN_VXFORM(vsro
, 6, 17);
7226 GEN_VXFORM(vaddcuw
, 0, 6);
7227 GEN_VXFORM(vsubcuw
, 0, 22);
7228 GEN_VXFORM_ENV(vaddubs
, 0, 8);
7229 GEN_VXFORM_ENV(vadduhs
, 0, 9);
7230 GEN_VXFORM_ENV(vadduws
, 0, 10);
7231 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
7232 GEN_VXFORM_ENV(vaddshs
, 0, 13);
7233 GEN_VXFORM_ENV(vaddsws
, 0, 14);
7234 GEN_VXFORM_ENV(vsububs
, 0, 24);
7235 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
7236 GEN_VXFORM_ENV(vsubuws
, 0, 26);
7237 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
7238 GEN_VXFORM_ENV(vsubshs
, 0, 29);
7239 GEN_VXFORM_ENV(vsubsws
, 0, 30);
7240 GEN_VXFORM(vadduqm
, 0, 4);
7241 GEN_VXFORM(vaddcuq
, 0, 5);
7242 GEN_VXFORM3(vaddeuqm
, 30, 0);
7243 GEN_VXFORM3(vaddecuq
, 30, 0);
7244 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7245 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7246 GEN_VXFORM(vsubuqm
, 0, 20);
7247 GEN_VXFORM(vsubcuq
, 0, 21);
7248 GEN_VXFORM3(vsubeuqm
, 31, 0);
7249 GEN_VXFORM3(vsubecuq
, 31, 0);
7250 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7251 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7252 GEN_VXFORM(vrlb
, 2, 0);
7253 GEN_VXFORM(vrlh
, 2, 1);
7254 GEN_VXFORM(vrlw
, 2, 2);
7255 GEN_VXFORM(vrld
, 2, 3);
7256 GEN_VXFORM(vsl
, 2, 7);
7257 GEN_VXFORM(vsr
, 2, 11);
7258 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
7259 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
7260 GEN_VXFORM_ENV(vpkudum
, 7, 17);
7261 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
7262 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
7263 GEN_VXFORM_ENV(vpkudus
, 7, 19);
7264 GEN_VXFORM_ENV(vpkshus
, 7, 4);
7265 GEN_VXFORM_ENV(vpkswus
, 7, 5);
7266 GEN_VXFORM_ENV(vpksdus
, 7, 21);
7267 GEN_VXFORM_ENV(vpkshss
, 7, 6);
7268 GEN_VXFORM_ENV(vpkswss
, 7, 7);
7269 GEN_VXFORM_ENV(vpksdss
, 7, 23);
7270 GEN_VXFORM(vpkpx
, 7, 12);
7271 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
7272 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
7273 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
7274 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
7275 GEN_VXFORM_ENV(vsumsws
, 4, 30);
7276 GEN_VXFORM_ENV(vaddfp
, 5, 0);
7277 GEN_VXFORM_ENV(vsubfp
, 5, 1);
7278 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
7279 GEN_VXFORM_ENV(vminfp
, 5, 17);
7281 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7282 static void glue(gen_, name)(DisasContext *ctx) \
7284 TCGv_ptr ra, rb, rd; \
7285 if (unlikely(!ctx->altivec_enabled)) { \
7286 gen_exception(ctx, POWERPC_EXCP_VPU); \
7289 ra = gen_avr_ptr(rA(ctx->opcode)); \
7290 rb = gen_avr_ptr(rB(ctx->opcode)); \
7291 rd = gen_avr_ptr(rD(ctx->opcode)); \
7292 gen_helper_##opname(cpu_env, rd, ra, rb); \
7293 tcg_temp_free_ptr(ra); \
7294 tcg_temp_free_ptr(rb); \
7295 tcg_temp_free_ptr(rd); \
7298 #define GEN_VXRFORM(name, opc2, opc3) \
7299 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7300 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7303 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7304 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7305 * come from different versions of the ISA, so we must also support a
7306 * pair of flags for each instruction.
7308 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7309 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7311 if ((Rc(ctx->opcode) == 0) && \
7312 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7313 if (Rc21(ctx->opcode) == 0) { \
7316 gen_##name0##_(ctx); \
7318 } else if ((Rc(ctx->opcode) == 1) && \
7319 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7320 if (Rc21(ctx->opcode) == 0) { \
7323 gen_##name1##_(ctx); \
7326 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7330 GEN_VXRFORM(vcmpequb
, 3, 0)
7331 GEN_VXRFORM(vcmpequh
, 3, 1)
7332 GEN_VXRFORM(vcmpequw
, 3, 2)
7333 GEN_VXRFORM(vcmpequd
, 3, 3)
7334 GEN_VXRFORM(vcmpgtsb
, 3, 12)
7335 GEN_VXRFORM(vcmpgtsh
, 3, 13)
7336 GEN_VXRFORM(vcmpgtsw
, 3, 14)
7337 GEN_VXRFORM(vcmpgtsd
, 3, 15)
7338 GEN_VXRFORM(vcmpgtub
, 3, 8)
7339 GEN_VXRFORM(vcmpgtuh
, 3, 9)
7340 GEN_VXRFORM(vcmpgtuw
, 3, 10)
7341 GEN_VXRFORM(vcmpgtud
, 3, 11)
7342 GEN_VXRFORM(vcmpeqfp
, 3, 3)
7343 GEN_VXRFORM(vcmpgefp
, 3, 7)
7344 GEN_VXRFORM(vcmpgtfp
, 3, 11)
7345 GEN_VXRFORM(vcmpbfp
, 3, 15)
7347 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
7348 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7349 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
7350 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7351 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
7352 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
7354 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7355 static void glue(gen_, name)(DisasContext *ctx) \
7359 if (unlikely(!ctx->altivec_enabled)) { \
7360 gen_exception(ctx, POWERPC_EXCP_VPU); \
7363 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7364 rd = gen_avr_ptr(rD(ctx->opcode)); \
7365 gen_helper_##name (rd, simm); \
7366 tcg_temp_free_i32(simm); \
7367 tcg_temp_free_ptr(rd); \
7370 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
7371 GEN_VXFORM_SIMM(vspltish
, 6, 13);
7372 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
7374 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7375 static void glue(gen_, name)(DisasContext *ctx) \
7378 if (unlikely(!ctx->altivec_enabled)) { \
7379 gen_exception(ctx, POWERPC_EXCP_VPU); \
7382 rb = gen_avr_ptr(rB(ctx->opcode)); \
7383 rd = gen_avr_ptr(rD(ctx->opcode)); \
7384 gen_helper_##name (rd, rb); \
7385 tcg_temp_free_ptr(rb); \
7386 tcg_temp_free_ptr(rd); \
7389 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7390 static void glue(gen_, name)(DisasContext *ctx) \
7394 if (unlikely(!ctx->altivec_enabled)) { \
7395 gen_exception(ctx, POWERPC_EXCP_VPU); \
7398 rb = gen_avr_ptr(rB(ctx->opcode)); \
7399 rd = gen_avr_ptr(rD(ctx->opcode)); \
7400 gen_helper_##name(cpu_env, rd, rb); \
7401 tcg_temp_free_ptr(rb); \
7402 tcg_temp_free_ptr(rd); \
7405 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
7406 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
7407 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
7408 GEN_VXFORM_NOA(vupklsb
, 7, 10);
7409 GEN_VXFORM_NOA(vupklsh
, 7, 11);
7410 GEN_VXFORM_NOA(vupklsw
, 7, 27);
7411 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
7412 GEN_VXFORM_NOA(vupklpx
, 7, 15);
7413 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
7414 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
7415 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
7416 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
7417 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
7418 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
7419 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
7420 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
7422 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7423 static void glue(gen_, name)(DisasContext *ctx) \
7427 if (unlikely(!ctx->altivec_enabled)) { \
7428 gen_exception(ctx, POWERPC_EXCP_VPU); \
7431 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7432 rd = gen_avr_ptr(rD(ctx->opcode)); \
7433 gen_helper_##name (rd, simm); \
7434 tcg_temp_free_i32(simm); \
7435 tcg_temp_free_ptr(rd); \
7438 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7439 static void glue(gen_, name)(DisasContext *ctx) \
7443 if (unlikely(!ctx->altivec_enabled)) { \
7444 gen_exception(ctx, POWERPC_EXCP_VPU); \
7447 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7448 rb = gen_avr_ptr(rB(ctx->opcode)); \
7449 rd = gen_avr_ptr(rD(ctx->opcode)); \
7450 gen_helper_##name (rd, rb, uimm); \
7451 tcg_temp_free_i32(uimm); \
7452 tcg_temp_free_ptr(rb); \
7453 tcg_temp_free_ptr(rd); \
7456 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7457 static void glue(gen_, name)(DisasContext *ctx) \
7462 if (unlikely(!ctx->altivec_enabled)) { \
7463 gen_exception(ctx, POWERPC_EXCP_VPU); \
7466 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7467 rb = gen_avr_ptr(rB(ctx->opcode)); \
7468 rd = gen_avr_ptr(rD(ctx->opcode)); \
7469 gen_helper_##name(cpu_env, rd, rb, uimm); \
7470 tcg_temp_free_i32(uimm); \
7471 tcg_temp_free_ptr(rb); \
7472 tcg_temp_free_ptr(rd); \
7475 GEN_VXFORM_UIMM(vspltb
, 6, 8);
7476 GEN_VXFORM_UIMM(vsplth
, 6, 9);
7477 GEN_VXFORM_UIMM(vspltw
, 6, 10);
7478 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
7479 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
7480 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
7481 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
7483 static void gen_vsldoi(DisasContext
*ctx
)
7485 TCGv_ptr ra
, rb
, rd
;
7487 if (unlikely(!ctx
->altivec_enabled
)) {
7488 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7491 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7492 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7493 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7494 sh
= tcg_const_i32(VSH(ctx
->opcode
));
7495 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
7496 tcg_temp_free_ptr(ra
);
7497 tcg_temp_free_ptr(rb
);
7498 tcg_temp_free_ptr(rd
);
7499 tcg_temp_free_i32(sh
);
7502 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7503 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7505 TCGv_ptr ra, rb, rc, rd; \
7506 if (unlikely(!ctx->altivec_enabled)) { \
7507 gen_exception(ctx, POWERPC_EXCP_VPU); \
7510 ra = gen_avr_ptr(rA(ctx->opcode)); \
7511 rb = gen_avr_ptr(rB(ctx->opcode)); \
7512 rc = gen_avr_ptr(rC(ctx->opcode)); \
7513 rd = gen_avr_ptr(rD(ctx->opcode)); \
7514 if (Rc(ctx->opcode)) { \
7515 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7517 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7519 tcg_temp_free_ptr(ra); \
7520 tcg_temp_free_ptr(rb); \
7521 tcg_temp_free_ptr(rc); \
7522 tcg_temp_free_ptr(rd); \
7525 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
7527 static void gen_vmladduhm(DisasContext
*ctx
)
7529 TCGv_ptr ra
, rb
, rc
, rd
;
7530 if (unlikely(!ctx
->altivec_enabled
)) {
7531 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7534 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7535 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7536 rc
= gen_avr_ptr(rC(ctx
->opcode
));
7537 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7538 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
7539 tcg_temp_free_ptr(ra
);
7540 tcg_temp_free_ptr(rb
);
7541 tcg_temp_free_ptr(rc
);
7542 tcg_temp_free_ptr(rd
);
7545 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
7546 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
7547 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
7548 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
7549 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
7551 GEN_VXFORM_NOA(vclzb
, 1, 28)
7552 GEN_VXFORM_NOA(vclzh
, 1, 29)
7553 GEN_VXFORM_NOA(vclzw
, 1, 30)
7554 GEN_VXFORM_NOA(vclzd
, 1, 31)
7555 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
7556 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
7557 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
7558 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
7559 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7560 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
7561 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7562 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
7563 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7564 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
7565 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7566 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7567 GEN_VXFORM(vbpermq
, 6, 21);
7568 GEN_VXFORM_NOA(vgbbd
, 6, 20);
7569 GEN_VXFORM(vpmsumb
, 4, 16)
7570 GEN_VXFORM(vpmsumh
, 4, 17)
7571 GEN_VXFORM(vpmsumw
, 4, 18)
7572 GEN_VXFORM(vpmsumd
, 4, 19)
7574 #define GEN_BCD(op) \
7575 static void gen_##op(DisasContext *ctx) \
7577 TCGv_ptr ra, rb, rd; \
7580 if (unlikely(!ctx->altivec_enabled)) { \
7581 gen_exception(ctx, POWERPC_EXCP_VPU); \
7585 ra = gen_avr_ptr(rA(ctx->opcode)); \
7586 rb = gen_avr_ptr(rB(ctx->opcode)); \
7587 rd = gen_avr_ptr(rD(ctx->opcode)); \
7589 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7591 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7593 tcg_temp_free_ptr(ra); \
7594 tcg_temp_free_ptr(rb); \
7595 tcg_temp_free_ptr(rd); \
7596 tcg_temp_free_i32(ps); \
7602 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
7603 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7604 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
7605 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7606 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
7607 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7608 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
7609 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7611 static void gen_vsbox(DisasContext
*ctx
)
7614 if (unlikely(!ctx
->altivec_enabled
)) {
7615 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7618 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7619 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7620 gen_helper_vsbox(rd
, ra
);
7621 tcg_temp_free_ptr(ra
);
7622 tcg_temp_free_ptr(rd
);
7625 GEN_VXFORM(vcipher
, 4, 20)
7626 GEN_VXFORM(vcipherlast
, 4, 20)
7627 GEN_VXFORM(vncipher
, 4, 21)
7628 GEN_VXFORM(vncipherlast
, 4, 21)
7630 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7631 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7632 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7633 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7635 #define VSHASIGMA(op) \
7636 static void gen_##op(DisasContext *ctx) \
7640 if (unlikely(!ctx->altivec_enabled)) { \
7641 gen_exception(ctx, POWERPC_EXCP_VPU); \
7644 ra = gen_avr_ptr(rA(ctx->opcode)); \
7645 rd = gen_avr_ptr(rD(ctx->opcode)); \
7646 st_six = tcg_const_i32(rB(ctx->opcode)); \
7647 gen_helper_##op(rd, ra, st_six); \
7648 tcg_temp_free_ptr(ra); \
7649 tcg_temp_free_ptr(rd); \
7650 tcg_temp_free_i32(st_six); \
7653 VSHASIGMA(vshasigmaw
)
7654 VSHASIGMA(vshasigmad
)
7656 GEN_VXFORM3(vpermxor
, 22, 0xFF)
7657 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
7658 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
7660 /*** VSX extension ***/
7662 static inline TCGv_i64
cpu_vsrh(int n
)
7667 return cpu_avrh
[n
-32];
7671 static inline TCGv_i64
cpu_vsrl(int n
)
7676 return cpu_avrl
[n
-32];
7680 #define VSX_LOAD_SCALAR(name, operation) \
7681 static void gen_##name(DisasContext *ctx) \
7684 if (unlikely(!ctx->vsx_enabled)) { \
7685 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7688 gen_set_access_type(ctx, ACCESS_INT); \
7689 EA = tcg_temp_new(); \
7690 gen_addr_reg_index(ctx, EA); \
7691 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7692 /* NOTE: cpu_vsrl is undefined */ \
7693 tcg_temp_free(EA); \
7696 VSX_LOAD_SCALAR(lxsdx
, ld64
)
7697 VSX_LOAD_SCALAR(lxsiwax
, ld32s_i64
)
7698 VSX_LOAD_SCALAR(lxsiwzx
, ld32u_i64
)
7699 VSX_LOAD_SCALAR(lxsspx
, ld32fs
)
7701 static void gen_lxvd2x(DisasContext
*ctx
)
7704 if (unlikely(!ctx
->vsx_enabled
)) {
7705 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7708 gen_set_access_type(ctx
, ACCESS_INT
);
7709 EA
= tcg_temp_new();
7710 gen_addr_reg_index(ctx
, EA
);
7711 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7712 tcg_gen_addi_tl(EA
, EA
, 8);
7713 gen_qemu_ld64(ctx
, cpu_vsrl(xT(ctx
->opcode
)), EA
);
7717 static void gen_lxvdsx(DisasContext
*ctx
)
7720 if (unlikely(!ctx
->vsx_enabled
)) {
7721 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7724 gen_set_access_type(ctx
, ACCESS_INT
);
7725 EA
= tcg_temp_new();
7726 gen_addr_reg_index(ctx
, EA
);
7727 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7728 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
7732 static void gen_lxvw4x(DisasContext
*ctx
)
7736 TCGv_i64 xth
= cpu_vsrh(xT(ctx
->opcode
));
7737 TCGv_i64 xtl
= cpu_vsrl(xT(ctx
->opcode
));
7738 if (unlikely(!ctx
->vsx_enabled
)) {
7739 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7742 gen_set_access_type(ctx
, ACCESS_INT
);
7743 EA
= tcg_temp_new();
7744 tmp
= tcg_temp_new_i64();
7746 gen_addr_reg_index(ctx
, EA
);
7747 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7748 tcg_gen_addi_tl(EA
, EA
, 4);
7749 gen_qemu_ld32u_i64(ctx
, xth
, EA
);
7750 tcg_gen_deposit_i64(xth
, xth
, tmp
, 32, 32);
7752 tcg_gen_addi_tl(EA
, EA
, 4);
7753 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7754 tcg_gen_addi_tl(EA
, EA
, 4);
7755 gen_qemu_ld32u_i64(ctx
, xtl
, EA
);
7756 tcg_gen_deposit_i64(xtl
, xtl
, tmp
, 32, 32);
7759 tcg_temp_free_i64(tmp
);
7762 #define VSX_STORE_SCALAR(name, operation) \
7763 static void gen_##name(DisasContext *ctx) \
7766 if (unlikely(!ctx->vsx_enabled)) { \
7767 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7770 gen_set_access_type(ctx, ACCESS_INT); \
7771 EA = tcg_temp_new(); \
7772 gen_addr_reg_index(ctx, EA); \
7773 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7774 tcg_temp_free(EA); \
7777 VSX_STORE_SCALAR(stxsdx
, st64
)
7778 VSX_STORE_SCALAR(stxsiwx
, st32_i64
)
7779 VSX_STORE_SCALAR(stxsspx
, st32fs
)
7781 static void gen_stxvd2x(DisasContext
*ctx
)
7784 if (unlikely(!ctx
->vsx_enabled
)) {
7785 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7788 gen_set_access_type(ctx
, ACCESS_INT
);
7789 EA
= tcg_temp_new();
7790 gen_addr_reg_index(ctx
, EA
);
7791 gen_qemu_st64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7792 tcg_gen_addi_tl(EA
, EA
, 8);
7793 gen_qemu_st64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7797 static void gen_stxvw4x(DisasContext
*ctx
)
7801 if (unlikely(!ctx
->vsx_enabled
)) {
7802 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7805 gen_set_access_type(ctx
, ACCESS_INT
);
7806 EA
= tcg_temp_new();
7807 gen_addr_reg_index(ctx
, EA
);
7808 tmp
= tcg_temp_new_i64();
7810 tcg_gen_shri_i64(tmp
, cpu_vsrh(xS(ctx
->opcode
)), 32);
7811 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7812 tcg_gen_addi_tl(EA
, EA
, 4);
7813 gen_qemu_st32_i64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7815 tcg_gen_shri_i64(tmp
, cpu_vsrl(xS(ctx
->opcode
)), 32);
7816 tcg_gen_addi_tl(EA
, EA
, 4);
7817 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7818 tcg_gen_addi_tl(EA
, EA
, 4);
7819 gen_qemu_st32_i64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7822 tcg_temp_free_i64(tmp
);
7825 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7826 static void gen_##name(DisasContext *ctx) \
7828 if (xS(ctx->opcode) < 32) { \
7829 if (unlikely(!ctx->fpu_enabled)) { \
7830 gen_exception(ctx, POWERPC_EXCP_FPU); \
7834 if (unlikely(!ctx->altivec_enabled)) { \
7835 gen_exception(ctx, POWERPC_EXCP_VPU); \
7839 TCGv_i64 tmp = tcg_temp_new_i64(); \
7840 tcg_gen_##tcgop1(tmp, source); \
7841 tcg_gen_##tcgop2(target, tmp); \
7842 tcg_temp_free_i64(tmp); \
7846 MV_VSRW(mfvsrwz
, ext32u_i64
, trunc_i64_tl
, cpu_gpr
[rA(ctx
->opcode
)], \
7847 cpu_vsrh(xS(ctx
->opcode
)))
7848 MV_VSRW(mtvsrwa
, extu_tl_i64
, ext32s_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7849 cpu_gpr
[rA(ctx
->opcode
)])
7850 MV_VSRW(mtvsrwz
, extu_tl_i64
, ext32u_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7851 cpu_gpr
[rA(ctx
->opcode
)])
7853 #if defined(TARGET_PPC64)
7854 #define MV_VSRD(name, target, source) \
7855 static void gen_##name(DisasContext *ctx) \
7857 if (xS(ctx->opcode) < 32) { \
7858 if (unlikely(!ctx->fpu_enabled)) { \
7859 gen_exception(ctx, POWERPC_EXCP_FPU); \
7863 if (unlikely(!ctx->altivec_enabled)) { \
7864 gen_exception(ctx, POWERPC_EXCP_VPU); \
7868 tcg_gen_mov_i64(target, source); \
7871 MV_VSRD(mfvsrd
, cpu_gpr
[rA(ctx
->opcode
)], cpu_vsrh(xS(ctx
->opcode
)))
7872 MV_VSRD(mtvsrd
, cpu_vsrh(xT(ctx
->opcode
)), cpu_gpr
[rA(ctx
->opcode
)])
7876 static void gen_xxpermdi(DisasContext
*ctx
)
7878 if (unlikely(!ctx
->vsx_enabled
)) {
7879 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7883 if (unlikely((xT(ctx
->opcode
) == xA(ctx
->opcode
)) ||
7884 (xT(ctx
->opcode
) == xB(ctx
->opcode
)))) {
7887 xh
= tcg_temp_new_i64();
7888 xl
= tcg_temp_new_i64();
7890 if ((DM(ctx
->opcode
) & 2) == 0) {
7891 tcg_gen_mov_i64(xh
, cpu_vsrh(xA(ctx
->opcode
)));
7893 tcg_gen_mov_i64(xh
, cpu_vsrl(xA(ctx
->opcode
)));
7895 if ((DM(ctx
->opcode
) & 1) == 0) {
7896 tcg_gen_mov_i64(xl
, cpu_vsrh(xB(ctx
->opcode
)));
7898 tcg_gen_mov_i64(xl
, cpu_vsrl(xB(ctx
->opcode
)));
7901 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xh
);
7902 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xl
);
7904 tcg_temp_free_i64(xh
);
7905 tcg_temp_free_i64(xl
);
7907 if ((DM(ctx
->opcode
) & 2) == 0) {
7908 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrh(xA(ctx
->opcode
)));
7910 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrl(xA(ctx
->opcode
)));
7912 if ((DM(ctx
->opcode
) & 1) == 0) {
7913 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xB(ctx
->opcode
)));
7915 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrl(xB(ctx
->opcode
)));
7924 #define SGN_MASK_DP 0x8000000000000000ull
7925 #define SGN_MASK_SP 0x8000000080000000ull
7927 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7928 static void glue(gen_, name)(DisasContext * ctx) \
7931 if (unlikely(!ctx->vsx_enabled)) { \
7932 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7935 xb = tcg_temp_new_i64(); \
7936 sgm = tcg_temp_new_i64(); \
7937 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7938 tcg_gen_movi_i64(sgm, sgn_mask); \
7941 tcg_gen_andc_i64(xb, xb, sgm); \
7945 tcg_gen_or_i64(xb, xb, sgm); \
7949 tcg_gen_xor_i64(xb, xb, sgm); \
7953 TCGv_i64 xa = tcg_temp_new_i64(); \
7954 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7955 tcg_gen_and_i64(xa, xa, sgm); \
7956 tcg_gen_andc_i64(xb, xb, sgm); \
7957 tcg_gen_or_i64(xb, xb, xa); \
7958 tcg_temp_free_i64(xa); \
7962 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7963 tcg_temp_free_i64(xb); \
7964 tcg_temp_free_i64(sgm); \
7967 VSX_SCALAR_MOVE(xsabsdp
, OP_ABS
, SGN_MASK_DP
)
7968 VSX_SCALAR_MOVE(xsnabsdp
, OP_NABS
, SGN_MASK_DP
)
7969 VSX_SCALAR_MOVE(xsnegdp
, OP_NEG
, SGN_MASK_DP
)
7970 VSX_SCALAR_MOVE(xscpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7972 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7973 static void glue(gen_, name)(DisasContext * ctx) \
7975 TCGv_i64 xbh, xbl, sgm; \
7976 if (unlikely(!ctx->vsx_enabled)) { \
7977 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7980 xbh = tcg_temp_new_i64(); \
7981 xbl = tcg_temp_new_i64(); \
7982 sgm = tcg_temp_new_i64(); \
7983 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7984 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7985 tcg_gen_movi_i64(sgm, sgn_mask); \
7988 tcg_gen_andc_i64(xbh, xbh, sgm); \
7989 tcg_gen_andc_i64(xbl, xbl, sgm); \
7993 tcg_gen_or_i64(xbh, xbh, sgm); \
7994 tcg_gen_or_i64(xbl, xbl, sgm); \
7998 tcg_gen_xor_i64(xbh, xbh, sgm); \
7999 tcg_gen_xor_i64(xbl, xbl, sgm); \
8003 TCGv_i64 xah = tcg_temp_new_i64(); \
8004 TCGv_i64 xal = tcg_temp_new_i64(); \
8005 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
8006 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
8007 tcg_gen_and_i64(xah, xah, sgm); \
8008 tcg_gen_and_i64(xal, xal, sgm); \
8009 tcg_gen_andc_i64(xbh, xbh, sgm); \
8010 tcg_gen_andc_i64(xbl, xbl, sgm); \
8011 tcg_gen_or_i64(xbh, xbh, xah); \
8012 tcg_gen_or_i64(xbl, xbl, xal); \
8013 tcg_temp_free_i64(xah); \
8014 tcg_temp_free_i64(xal); \
8018 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
8019 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
8020 tcg_temp_free_i64(xbh); \
8021 tcg_temp_free_i64(xbl); \
8022 tcg_temp_free_i64(sgm); \
8025 VSX_VECTOR_MOVE(xvabsdp
, OP_ABS
, SGN_MASK_DP
)
8026 VSX_VECTOR_MOVE(xvnabsdp
, OP_NABS
, SGN_MASK_DP
)
8027 VSX_VECTOR_MOVE(xvnegdp
, OP_NEG
, SGN_MASK_DP
)
8028 VSX_VECTOR_MOVE(xvcpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
8029 VSX_VECTOR_MOVE(xvabssp
, OP_ABS
, SGN_MASK_SP
)
8030 VSX_VECTOR_MOVE(xvnabssp
, OP_NABS
, SGN_MASK_SP
)
8031 VSX_VECTOR_MOVE(xvnegsp
, OP_NEG
, SGN_MASK_SP
)
8032 VSX_VECTOR_MOVE(xvcpsgnsp
, OP_CPSGN
, SGN_MASK_SP
)
8034 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8035 static void gen_##name(DisasContext * ctx) \
8038 if (unlikely(!ctx->vsx_enabled)) { \
8039 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8042 /* NIP cannot be restored if the memory exception comes from an helper */ \
8043 gen_update_nip(ctx, ctx->nip - 4); \
8044 opc = tcg_const_i32(ctx->opcode); \
8045 gen_helper_##name(cpu_env, opc); \
8046 tcg_temp_free_i32(opc); \
8049 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8050 static void gen_##name(DisasContext * ctx) \
8052 if (unlikely(!ctx->vsx_enabled)) { \
8053 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8056 /* NIP cannot be restored if the exception comes */ \
8057 /* from a helper. */ \
8058 gen_update_nip(ctx, ctx->nip - 4); \
8060 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8061 cpu_vsrh(xB(ctx->opcode))); \
8064 GEN_VSX_HELPER_2(xsadddp
, 0x00, 0x04, 0, PPC2_VSX
)
8065 GEN_VSX_HELPER_2(xssubdp
, 0x00, 0x05, 0, PPC2_VSX
)
8066 GEN_VSX_HELPER_2(xsmuldp
, 0x00, 0x06, 0, PPC2_VSX
)
8067 GEN_VSX_HELPER_2(xsdivdp
, 0x00, 0x07, 0, PPC2_VSX
)
8068 GEN_VSX_HELPER_2(xsredp
, 0x14, 0x05, 0, PPC2_VSX
)
8069 GEN_VSX_HELPER_2(xssqrtdp
, 0x16, 0x04, 0, PPC2_VSX
)
8070 GEN_VSX_HELPER_2(xsrsqrtedp
, 0x14, 0x04, 0, PPC2_VSX
)
8071 GEN_VSX_HELPER_2(xstdivdp
, 0x14, 0x07, 0, PPC2_VSX
)
8072 GEN_VSX_HELPER_2(xstsqrtdp
, 0x14, 0x06, 0, PPC2_VSX
)
8073 GEN_VSX_HELPER_2(xsmaddadp
, 0x04, 0x04, 0, PPC2_VSX
)
8074 GEN_VSX_HELPER_2(xsmaddmdp
, 0x04, 0x05, 0, PPC2_VSX
)
8075 GEN_VSX_HELPER_2(xsmsubadp
, 0x04, 0x06, 0, PPC2_VSX
)
8076 GEN_VSX_HELPER_2(xsmsubmdp
, 0x04, 0x07, 0, PPC2_VSX
)
8077 GEN_VSX_HELPER_2(xsnmaddadp
, 0x04, 0x14, 0, PPC2_VSX
)
8078 GEN_VSX_HELPER_2(xsnmaddmdp
, 0x04, 0x15, 0, PPC2_VSX
)
8079 GEN_VSX_HELPER_2(xsnmsubadp
, 0x04, 0x16, 0, PPC2_VSX
)
8080 GEN_VSX_HELPER_2(xsnmsubmdp
, 0x04, 0x17, 0, PPC2_VSX
)
8081 GEN_VSX_HELPER_2(xscmpodp
, 0x0C, 0x05, 0, PPC2_VSX
)
8082 GEN_VSX_HELPER_2(xscmpudp
, 0x0C, 0x04, 0, PPC2_VSX
)
8083 GEN_VSX_HELPER_2(xsmaxdp
, 0x00, 0x14, 0, PPC2_VSX
)
8084 GEN_VSX_HELPER_2(xsmindp
, 0x00, 0x15, 0, PPC2_VSX
)
8085 GEN_VSX_HELPER_2(xscvdpsp
, 0x12, 0x10, 0, PPC2_VSX
)
8086 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn
, 0x16, 0x10, 0, PPC2_VSX207
)
8087 GEN_VSX_HELPER_2(xscvspdp
, 0x12, 0x14, 0, PPC2_VSX
)
8088 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn
, 0x16, 0x14, 0, PPC2_VSX207
)
8089 GEN_VSX_HELPER_2(xscvdpsxds
, 0x10, 0x15, 0, PPC2_VSX
)
8090 GEN_VSX_HELPER_2(xscvdpsxws
, 0x10, 0x05, 0, PPC2_VSX
)
8091 GEN_VSX_HELPER_2(xscvdpuxds
, 0x10, 0x14, 0, PPC2_VSX
)
8092 GEN_VSX_HELPER_2(xscvdpuxws
, 0x10, 0x04, 0, PPC2_VSX
)
8093 GEN_VSX_HELPER_2(xscvsxddp
, 0x10, 0x17, 0, PPC2_VSX
)
8094 GEN_VSX_HELPER_2(xscvuxddp
, 0x10, 0x16, 0, PPC2_VSX
)
8095 GEN_VSX_HELPER_2(xsrdpi
, 0x12, 0x04, 0, PPC2_VSX
)
8096 GEN_VSX_HELPER_2(xsrdpic
, 0x16, 0x06, 0, PPC2_VSX
)
8097 GEN_VSX_HELPER_2(xsrdpim
, 0x12, 0x07, 0, PPC2_VSX
)
8098 GEN_VSX_HELPER_2(xsrdpip
, 0x12, 0x06, 0, PPC2_VSX
)
8099 GEN_VSX_HELPER_2(xsrdpiz
, 0x12, 0x05, 0, PPC2_VSX
)
8100 GEN_VSX_HELPER_XT_XB_ENV(xsrsp
, 0x12, 0x11, 0, PPC2_VSX207
)
8102 GEN_VSX_HELPER_2(xsaddsp
, 0x00, 0x00, 0, PPC2_VSX207
)
8103 GEN_VSX_HELPER_2(xssubsp
, 0x00, 0x01, 0, PPC2_VSX207
)
8104 GEN_VSX_HELPER_2(xsmulsp
, 0x00, 0x02, 0, PPC2_VSX207
)
8105 GEN_VSX_HELPER_2(xsdivsp
, 0x00, 0x03, 0, PPC2_VSX207
)
8106 GEN_VSX_HELPER_2(xsresp
, 0x14, 0x01, 0, PPC2_VSX207
)
8107 GEN_VSX_HELPER_2(xssqrtsp
, 0x16, 0x00, 0, PPC2_VSX207
)
8108 GEN_VSX_HELPER_2(xsrsqrtesp
, 0x14, 0x00, 0, PPC2_VSX207
)
8109 GEN_VSX_HELPER_2(xsmaddasp
, 0x04, 0x00, 0, PPC2_VSX207
)
8110 GEN_VSX_HELPER_2(xsmaddmsp
, 0x04, 0x01, 0, PPC2_VSX207
)
8111 GEN_VSX_HELPER_2(xsmsubasp
, 0x04, 0x02, 0, PPC2_VSX207
)
8112 GEN_VSX_HELPER_2(xsmsubmsp
, 0x04, 0x03, 0, PPC2_VSX207
)
8113 GEN_VSX_HELPER_2(xsnmaddasp
, 0x04, 0x10, 0, PPC2_VSX207
)
8114 GEN_VSX_HELPER_2(xsnmaddmsp
, 0x04, 0x11, 0, PPC2_VSX207
)
8115 GEN_VSX_HELPER_2(xsnmsubasp
, 0x04, 0x12, 0, PPC2_VSX207
)
8116 GEN_VSX_HELPER_2(xsnmsubmsp
, 0x04, 0x13, 0, PPC2_VSX207
)
8117 GEN_VSX_HELPER_2(xscvsxdsp
, 0x10, 0x13, 0, PPC2_VSX207
)
8118 GEN_VSX_HELPER_2(xscvuxdsp
, 0x10, 0x12, 0, PPC2_VSX207
)
8120 GEN_VSX_HELPER_2(xvadddp
, 0x00, 0x0C, 0, PPC2_VSX
)
8121 GEN_VSX_HELPER_2(xvsubdp
, 0x00, 0x0D, 0, PPC2_VSX
)
8122 GEN_VSX_HELPER_2(xvmuldp
, 0x00, 0x0E, 0, PPC2_VSX
)
8123 GEN_VSX_HELPER_2(xvdivdp
, 0x00, 0x0F, 0, PPC2_VSX
)
8124 GEN_VSX_HELPER_2(xvredp
, 0x14, 0x0D, 0, PPC2_VSX
)
8125 GEN_VSX_HELPER_2(xvsqrtdp
, 0x16, 0x0C, 0, PPC2_VSX
)
8126 GEN_VSX_HELPER_2(xvrsqrtedp
, 0x14, 0x0C, 0, PPC2_VSX
)
8127 GEN_VSX_HELPER_2(xvtdivdp
, 0x14, 0x0F, 0, PPC2_VSX
)
8128 GEN_VSX_HELPER_2(xvtsqrtdp
, 0x14, 0x0E, 0, PPC2_VSX
)
8129 GEN_VSX_HELPER_2(xvmaddadp
, 0x04, 0x0C, 0, PPC2_VSX
)
8130 GEN_VSX_HELPER_2(xvmaddmdp
, 0x04, 0x0D, 0, PPC2_VSX
)
8131 GEN_VSX_HELPER_2(xvmsubadp
, 0x04, 0x0E, 0, PPC2_VSX
)
8132 GEN_VSX_HELPER_2(xvmsubmdp
, 0x04, 0x0F, 0, PPC2_VSX
)
8133 GEN_VSX_HELPER_2(xvnmaddadp
, 0x04, 0x1C, 0, PPC2_VSX
)
8134 GEN_VSX_HELPER_2(xvnmaddmdp
, 0x04, 0x1D, 0, PPC2_VSX
)
8135 GEN_VSX_HELPER_2(xvnmsubadp
, 0x04, 0x1E, 0, PPC2_VSX
)
8136 GEN_VSX_HELPER_2(xvnmsubmdp
, 0x04, 0x1F, 0, PPC2_VSX
)
8137 GEN_VSX_HELPER_2(xvmaxdp
, 0x00, 0x1C, 0, PPC2_VSX
)
8138 GEN_VSX_HELPER_2(xvmindp
, 0x00, 0x1D, 0, PPC2_VSX
)
8139 GEN_VSX_HELPER_2(xvcmpeqdp
, 0x0C, 0x0C, 0, PPC2_VSX
)
8140 GEN_VSX_HELPER_2(xvcmpgtdp
, 0x0C, 0x0D, 0, PPC2_VSX
)
8141 GEN_VSX_HELPER_2(xvcmpgedp
, 0x0C, 0x0E, 0, PPC2_VSX
)
8142 GEN_VSX_HELPER_2(xvcvdpsp
, 0x12, 0x18, 0, PPC2_VSX
)
8143 GEN_VSX_HELPER_2(xvcvdpsxds
, 0x10, 0x1D, 0, PPC2_VSX
)
8144 GEN_VSX_HELPER_2(xvcvdpsxws
, 0x10, 0x0D, 0, PPC2_VSX
)
8145 GEN_VSX_HELPER_2(xvcvdpuxds
, 0x10, 0x1C, 0, PPC2_VSX
)
8146 GEN_VSX_HELPER_2(xvcvdpuxws
, 0x10, 0x0C, 0, PPC2_VSX
)
8147 GEN_VSX_HELPER_2(xvcvsxddp
, 0x10, 0x1F, 0, PPC2_VSX
)
8148 GEN_VSX_HELPER_2(xvcvuxddp
, 0x10, 0x1E, 0, PPC2_VSX
)
8149 GEN_VSX_HELPER_2(xvcvsxwdp
, 0x10, 0x0F, 0, PPC2_VSX
)
8150 GEN_VSX_HELPER_2(xvcvuxwdp
, 0x10, 0x0E, 0, PPC2_VSX
)
8151 GEN_VSX_HELPER_2(xvrdpi
, 0x12, 0x0C, 0, PPC2_VSX
)
8152 GEN_VSX_HELPER_2(xvrdpic
, 0x16, 0x0E, 0, PPC2_VSX
)
8153 GEN_VSX_HELPER_2(xvrdpim
, 0x12, 0x0F, 0, PPC2_VSX
)
8154 GEN_VSX_HELPER_2(xvrdpip
, 0x12, 0x0E, 0, PPC2_VSX
)
8155 GEN_VSX_HELPER_2(xvrdpiz
, 0x12, 0x0D, 0, PPC2_VSX
)
8157 GEN_VSX_HELPER_2(xvaddsp
, 0x00, 0x08, 0, PPC2_VSX
)
8158 GEN_VSX_HELPER_2(xvsubsp
, 0x00, 0x09, 0, PPC2_VSX
)
8159 GEN_VSX_HELPER_2(xvmulsp
, 0x00, 0x0A, 0, PPC2_VSX
)
8160 GEN_VSX_HELPER_2(xvdivsp
, 0x00, 0x0B, 0, PPC2_VSX
)
8161 GEN_VSX_HELPER_2(xvresp
, 0x14, 0x09, 0, PPC2_VSX
)
8162 GEN_VSX_HELPER_2(xvsqrtsp
, 0x16, 0x08, 0, PPC2_VSX
)
8163 GEN_VSX_HELPER_2(xvrsqrtesp
, 0x14, 0x08, 0, PPC2_VSX
)
8164 GEN_VSX_HELPER_2(xvtdivsp
, 0x14, 0x0B, 0, PPC2_VSX
)
8165 GEN_VSX_HELPER_2(xvtsqrtsp
, 0x14, 0x0A, 0, PPC2_VSX
)
8166 GEN_VSX_HELPER_2(xvmaddasp
, 0x04, 0x08, 0, PPC2_VSX
)
8167 GEN_VSX_HELPER_2(xvmaddmsp
, 0x04, 0x09, 0, PPC2_VSX
)
8168 GEN_VSX_HELPER_2(xvmsubasp
, 0x04, 0x0A, 0, PPC2_VSX
)
8169 GEN_VSX_HELPER_2(xvmsubmsp
, 0x04, 0x0B, 0, PPC2_VSX
)
8170 GEN_VSX_HELPER_2(xvnmaddasp
, 0x04, 0x18, 0, PPC2_VSX
)
8171 GEN_VSX_HELPER_2(xvnmaddmsp
, 0x04, 0x19, 0, PPC2_VSX
)
8172 GEN_VSX_HELPER_2(xvnmsubasp
, 0x04, 0x1A, 0, PPC2_VSX
)
8173 GEN_VSX_HELPER_2(xvnmsubmsp
, 0x04, 0x1B, 0, PPC2_VSX
)
8174 GEN_VSX_HELPER_2(xvmaxsp
, 0x00, 0x18, 0, PPC2_VSX
)
8175 GEN_VSX_HELPER_2(xvminsp
, 0x00, 0x19, 0, PPC2_VSX
)
8176 GEN_VSX_HELPER_2(xvcmpeqsp
, 0x0C, 0x08, 0, PPC2_VSX
)
8177 GEN_VSX_HELPER_2(xvcmpgtsp
, 0x0C, 0x09, 0, PPC2_VSX
)
8178 GEN_VSX_HELPER_2(xvcmpgesp
, 0x0C, 0x0A, 0, PPC2_VSX
)
8179 GEN_VSX_HELPER_2(xvcvspdp
, 0x12, 0x1C, 0, PPC2_VSX
)
8180 GEN_VSX_HELPER_2(xvcvspsxds
, 0x10, 0x19, 0, PPC2_VSX
)
8181 GEN_VSX_HELPER_2(xvcvspsxws
, 0x10, 0x09, 0, PPC2_VSX
)
8182 GEN_VSX_HELPER_2(xvcvspuxds
, 0x10, 0x18, 0, PPC2_VSX
)
8183 GEN_VSX_HELPER_2(xvcvspuxws
, 0x10, 0x08, 0, PPC2_VSX
)
8184 GEN_VSX_HELPER_2(xvcvsxdsp
, 0x10, 0x1B, 0, PPC2_VSX
)
8185 GEN_VSX_HELPER_2(xvcvuxdsp
, 0x10, 0x1A, 0, PPC2_VSX
)
8186 GEN_VSX_HELPER_2(xvcvsxwsp
, 0x10, 0x0B, 0, PPC2_VSX
)
8187 GEN_VSX_HELPER_2(xvcvuxwsp
, 0x10, 0x0A, 0, PPC2_VSX
)
8188 GEN_VSX_HELPER_2(xvrspi
, 0x12, 0x08, 0, PPC2_VSX
)
8189 GEN_VSX_HELPER_2(xvrspic
, 0x16, 0x0A, 0, PPC2_VSX
)
8190 GEN_VSX_HELPER_2(xvrspim
, 0x12, 0x0B, 0, PPC2_VSX
)
8191 GEN_VSX_HELPER_2(xvrspip
, 0x12, 0x0A, 0, PPC2_VSX
)
8192 GEN_VSX_HELPER_2(xvrspiz
, 0x12, 0x09, 0, PPC2_VSX
)
8194 #define VSX_LOGICAL(name, tcg_op) \
8195 static void glue(gen_, name)(DisasContext * ctx) \
8197 if (unlikely(!ctx->vsx_enabled)) { \
8198 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8201 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8202 cpu_vsrh(xB(ctx->opcode))); \
8203 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8204 cpu_vsrl(xB(ctx->opcode))); \
8207 VSX_LOGICAL(xxland
, tcg_gen_and_i64
)
8208 VSX_LOGICAL(xxlandc
, tcg_gen_andc_i64
)
8209 VSX_LOGICAL(xxlor
, tcg_gen_or_i64
)
8210 VSX_LOGICAL(xxlxor
, tcg_gen_xor_i64
)
8211 VSX_LOGICAL(xxlnor
, tcg_gen_nor_i64
)
8212 VSX_LOGICAL(xxleqv
, tcg_gen_eqv_i64
)
8213 VSX_LOGICAL(xxlnand
, tcg_gen_nand_i64
)
8214 VSX_LOGICAL(xxlorc
, tcg_gen_orc_i64
)
8216 #define VSX_XXMRG(name, high) \
8217 static void glue(gen_, name)(DisasContext * ctx) \
8219 TCGv_i64 a0, a1, b0, b1; \
8220 if (unlikely(!ctx->vsx_enabled)) { \
8221 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8224 a0 = tcg_temp_new_i64(); \
8225 a1 = tcg_temp_new_i64(); \
8226 b0 = tcg_temp_new_i64(); \
8227 b1 = tcg_temp_new_i64(); \
8229 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8230 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8231 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8232 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8234 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8235 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8236 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8237 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8239 tcg_gen_shri_i64(a0, a0, 32); \
8240 tcg_gen_shri_i64(b0, b0, 32); \
8241 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8243 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8245 tcg_temp_free_i64(a0); \
8246 tcg_temp_free_i64(a1); \
8247 tcg_temp_free_i64(b0); \
8248 tcg_temp_free_i64(b1); \
8251 VSX_XXMRG(xxmrghw
, 1)
8252 VSX_XXMRG(xxmrglw
, 0)
8254 static void gen_xxsel(DisasContext
* ctx
)
8257 if (unlikely(!ctx
->vsx_enabled
)) {
8258 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8261 a
= tcg_temp_new_i64();
8262 b
= tcg_temp_new_i64();
8263 c
= tcg_temp_new_i64();
8265 tcg_gen_mov_i64(a
, cpu_vsrh(xA(ctx
->opcode
)));
8266 tcg_gen_mov_i64(b
, cpu_vsrh(xB(ctx
->opcode
)));
8267 tcg_gen_mov_i64(c
, cpu_vsrh(xC(ctx
->opcode
)));
8269 tcg_gen_and_i64(b
, b
, c
);
8270 tcg_gen_andc_i64(a
, a
, c
);
8271 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), a
, b
);
8273 tcg_gen_mov_i64(a
, cpu_vsrl(xA(ctx
->opcode
)));
8274 tcg_gen_mov_i64(b
, cpu_vsrl(xB(ctx
->opcode
)));
8275 tcg_gen_mov_i64(c
, cpu_vsrl(xC(ctx
->opcode
)));
8277 tcg_gen_and_i64(b
, b
, c
);
8278 tcg_gen_andc_i64(a
, a
, c
);
8279 tcg_gen_or_i64(cpu_vsrl(xT(ctx
->opcode
)), a
, b
);
8281 tcg_temp_free_i64(a
);
8282 tcg_temp_free_i64(b
);
8283 tcg_temp_free_i64(c
);
8286 static void gen_xxspltw(DisasContext
*ctx
)
8289 TCGv_i64 vsr
= (UIM(ctx
->opcode
) & 2) ?
8290 cpu_vsrl(xB(ctx
->opcode
)) :
8291 cpu_vsrh(xB(ctx
->opcode
));
8293 if (unlikely(!ctx
->vsx_enabled
)) {
8294 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8298 b
= tcg_temp_new_i64();
8299 b2
= tcg_temp_new_i64();
8301 if (UIM(ctx
->opcode
) & 1) {
8302 tcg_gen_ext32u_i64(b
, vsr
);
8304 tcg_gen_shri_i64(b
, vsr
, 32);
8307 tcg_gen_shli_i64(b2
, b
, 32);
8308 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), b
, b2
);
8309 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
8311 tcg_temp_free_i64(b
);
8312 tcg_temp_free_i64(b2
);
8315 static void gen_xxsldwi(DisasContext
*ctx
)
8318 if (unlikely(!ctx
->vsx_enabled
)) {
8319 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8322 xth
= tcg_temp_new_i64();
8323 xtl
= tcg_temp_new_i64();
8325 switch (SHW(ctx
->opcode
)) {
8327 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8328 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8332 TCGv_i64 t0
= tcg_temp_new_i64();
8333 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8334 tcg_gen_shli_i64(xth
, xth
, 32);
8335 tcg_gen_mov_i64(t0
, cpu_vsrl(xA(ctx
->opcode
)));
8336 tcg_gen_shri_i64(t0
, t0
, 32);
8337 tcg_gen_or_i64(xth
, xth
, t0
);
8338 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8339 tcg_gen_shli_i64(xtl
, xtl
, 32);
8340 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8341 tcg_gen_shri_i64(t0
, t0
, 32);
8342 tcg_gen_or_i64(xtl
, xtl
, t0
);
8343 tcg_temp_free_i64(t0
);
8347 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8348 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8352 TCGv_i64 t0
= tcg_temp_new_i64();
8353 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8354 tcg_gen_shli_i64(xth
, xth
, 32);
8355 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8356 tcg_gen_shri_i64(t0
, t0
, 32);
8357 tcg_gen_or_i64(xth
, xth
, t0
);
8358 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8359 tcg_gen_shli_i64(xtl
, xtl
, 32);
8360 tcg_gen_mov_i64(t0
, cpu_vsrl(xB(ctx
->opcode
)));
8361 tcg_gen_shri_i64(t0
, t0
, 32);
8362 tcg_gen_or_i64(xtl
, xtl
, t0
);
8363 tcg_temp_free_i64(t0
);
8368 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xth
);
8369 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xtl
);
8371 tcg_temp_free_i64(xth
);
8372 tcg_temp_free_i64(xtl
);
8375 /*** Decimal Floating Point ***/
8377 static inline TCGv_ptr
gen_fprp_ptr(int reg
)
8379 TCGv_ptr r
= tcg_temp_new_ptr();
8380 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, fpr
[reg
]));
8384 #define GEN_DFP_T_A_B_Rc(name) \
8385 static void gen_##name(DisasContext *ctx) \
8387 TCGv_ptr rd, ra, rb; \
8388 if (unlikely(!ctx->fpu_enabled)) { \
8389 gen_exception(ctx, POWERPC_EXCP_FPU); \
8392 gen_update_nip(ctx, ctx->nip - 4); \
8393 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8394 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8395 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8396 gen_helper_##name(cpu_env, rd, ra, rb); \
8397 if (unlikely(Rc(ctx->opcode) != 0)) { \
8398 gen_set_cr1_from_fpscr(ctx); \
8400 tcg_temp_free_ptr(rd); \
8401 tcg_temp_free_ptr(ra); \
8402 tcg_temp_free_ptr(rb); \
8405 #define GEN_DFP_BF_A_B(name) \
8406 static void gen_##name(DisasContext *ctx) \
8409 if (unlikely(!ctx->fpu_enabled)) { \
8410 gen_exception(ctx, POWERPC_EXCP_FPU); \
8413 gen_update_nip(ctx, ctx->nip - 4); \
8414 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8415 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8416 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8418 tcg_temp_free_ptr(ra); \
8419 tcg_temp_free_ptr(rb); \
8422 #define GEN_DFP_BF_A_DCM(name) \
8423 static void gen_##name(DisasContext *ctx) \
8427 if (unlikely(!ctx->fpu_enabled)) { \
8428 gen_exception(ctx, POWERPC_EXCP_FPU); \
8431 gen_update_nip(ctx, ctx->nip - 4); \
8432 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8433 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8434 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8435 cpu_env, ra, dcm); \
8436 tcg_temp_free_ptr(ra); \
8437 tcg_temp_free_i32(dcm); \
8440 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8441 static void gen_##name(DisasContext *ctx) \
8444 TCGv_i32 u32_1, u32_2; \
8445 if (unlikely(!ctx->fpu_enabled)) { \
8446 gen_exception(ctx, POWERPC_EXCP_FPU); \
8449 gen_update_nip(ctx, ctx->nip - 4); \
8450 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8451 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8452 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8453 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8454 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8455 if (unlikely(Rc(ctx->opcode) != 0)) { \
8456 gen_set_cr1_from_fpscr(ctx); \
8458 tcg_temp_free_ptr(rt); \
8459 tcg_temp_free_ptr(rb); \
8460 tcg_temp_free_i32(u32_1); \
8461 tcg_temp_free_i32(u32_2); \
8464 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8465 static void gen_##name(DisasContext *ctx) \
8467 TCGv_ptr rt, ra, rb; \
8469 if (unlikely(!ctx->fpu_enabled)) { \
8470 gen_exception(ctx, POWERPC_EXCP_FPU); \
8473 gen_update_nip(ctx, ctx->nip - 4); \
8474 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8475 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8476 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8477 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8478 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8479 if (unlikely(Rc(ctx->opcode) != 0)) { \
8480 gen_set_cr1_from_fpscr(ctx); \
8482 tcg_temp_free_ptr(rt); \
8483 tcg_temp_free_ptr(rb); \
8484 tcg_temp_free_ptr(ra); \
8485 tcg_temp_free_i32(i32); \
8488 #define GEN_DFP_T_B_Rc(name) \
8489 static void gen_##name(DisasContext *ctx) \
8492 if (unlikely(!ctx->fpu_enabled)) { \
8493 gen_exception(ctx, POWERPC_EXCP_FPU); \
8496 gen_update_nip(ctx, ctx->nip - 4); \
8497 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8498 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8499 gen_helper_##name(cpu_env, rt, rb); \
8500 if (unlikely(Rc(ctx->opcode) != 0)) { \
8501 gen_set_cr1_from_fpscr(ctx); \
8503 tcg_temp_free_ptr(rt); \
8504 tcg_temp_free_ptr(rb); \
8507 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8508 static void gen_##name(DisasContext *ctx) \
8512 if (unlikely(!ctx->fpu_enabled)) { \
8513 gen_exception(ctx, POWERPC_EXCP_FPU); \
8516 gen_update_nip(ctx, ctx->nip - 4); \
8517 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8518 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8519 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8520 gen_helper_##name(cpu_env, rt, rs, i32); \
8521 if (unlikely(Rc(ctx->opcode) != 0)) { \
8522 gen_set_cr1_from_fpscr(ctx); \
8524 tcg_temp_free_ptr(rt); \
8525 tcg_temp_free_ptr(rs); \
8526 tcg_temp_free_i32(i32); \
8529 GEN_DFP_T_A_B_Rc(dadd
)
8530 GEN_DFP_T_A_B_Rc(daddq
)
8531 GEN_DFP_T_A_B_Rc(dsub
)
8532 GEN_DFP_T_A_B_Rc(dsubq
)
8533 GEN_DFP_T_A_B_Rc(dmul
)
8534 GEN_DFP_T_A_B_Rc(dmulq
)
8535 GEN_DFP_T_A_B_Rc(ddiv
)
8536 GEN_DFP_T_A_B_Rc(ddivq
)
8537 GEN_DFP_BF_A_B(dcmpu
)
8538 GEN_DFP_BF_A_B(dcmpuq
)
8539 GEN_DFP_BF_A_B(dcmpo
)
8540 GEN_DFP_BF_A_B(dcmpoq
)
8541 GEN_DFP_BF_A_DCM(dtstdc
)
8542 GEN_DFP_BF_A_DCM(dtstdcq
)
8543 GEN_DFP_BF_A_DCM(dtstdg
)
8544 GEN_DFP_BF_A_DCM(dtstdgq
)
8545 GEN_DFP_BF_A_B(dtstex
)
8546 GEN_DFP_BF_A_B(dtstexq
)
8547 GEN_DFP_BF_A_B(dtstsf
)
8548 GEN_DFP_BF_A_B(dtstsfq
)
8549 GEN_DFP_T_B_U32_U32_Rc(dquai
, SIMM5
, RMC
)
8550 GEN_DFP_T_B_U32_U32_Rc(dquaiq
, SIMM5
, RMC
)
8551 GEN_DFP_T_A_B_I32_Rc(dqua
, RMC
)
8552 GEN_DFP_T_A_B_I32_Rc(dquaq
, RMC
)
8553 GEN_DFP_T_A_B_I32_Rc(drrnd
, RMC
)
8554 GEN_DFP_T_A_B_I32_Rc(drrndq
, RMC
)
8555 GEN_DFP_T_B_U32_U32_Rc(drintx
, FPW
, RMC
)
8556 GEN_DFP_T_B_U32_U32_Rc(drintxq
, FPW
, RMC
)
8557 GEN_DFP_T_B_U32_U32_Rc(drintn
, FPW
, RMC
)
8558 GEN_DFP_T_B_U32_U32_Rc(drintnq
, FPW
, RMC
)
8559 GEN_DFP_T_B_Rc(dctdp
)
8560 GEN_DFP_T_B_Rc(dctqpq
)
8561 GEN_DFP_T_B_Rc(drsp
)
8562 GEN_DFP_T_B_Rc(drdpq
)
8563 GEN_DFP_T_B_Rc(dcffix
)
8564 GEN_DFP_T_B_Rc(dcffixq
)
8565 GEN_DFP_T_B_Rc(dctfix
)
8566 GEN_DFP_T_B_Rc(dctfixq
)
8567 GEN_DFP_T_FPR_I32_Rc(ddedpd
, rB
, SP
)
8568 GEN_DFP_T_FPR_I32_Rc(ddedpdq
, rB
, SP
)
8569 GEN_DFP_T_FPR_I32_Rc(denbcd
, rB
, SP
)
8570 GEN_DFP_T_FPR_I32_Rc(denbcdq
, rB
, SP
)
8571 GEN_DFP_T_B_Rc(dxex
)
8572 GEN_DFP_T_B_Rc(dxexq
)
8573 GEN_DFP_T_A_B_Rc(diex
)
8574 GEN_DFP_T_A_B_Rc(diexq
)
8575 GEN_DFP_T_FPR_I32_Rc(dscli
, rA
, DCM
)
8576 GEN_DFP_T_FPR_I32_Rc(dscliq
, rA
, DCM
)
8577 GEN_DFP_T_FPR_I32_Rc(dscri
, rA
, DCM
)
8578 GEN_DFP_T_FPR_I32_Rc(dscriq
, rA
, DCM
)
8580 /*** SPE extension ***/
8581 /* Register moves */
8583 static inline void gen_evmra(DisasContext
*ctx
)
8586 if (unlikely(!ctx
->spe_enabled
)) {
8587 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8591 TCGv_i64 tmp
= tcg_temp_new_i64();
8593 /* tmp := rA_lo + rA_hi << 32 */
8594 tcg_gen_concat_tl_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8596 /* spe_acc := tmp */
8597 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8598 tcg_temp_free_i64(tmp
);
8601 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8602 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8605 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
8607 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
8610 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
8612 tcg_gen_extr_i64_tl(cpu_gpr
[reg
], cpu_gprh
[reg
], t
);
8615 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8616 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8618 if (Rc(ctx->opcode)) \
8624 /* Handler for undefined SPE opcodes */
8625 static inline void gen_speundef(DisasContext
*ctx
)
8627 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
8631 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8632 static inline void gen_##name(DisasContext *ctx) \
8634 if (unlikely(!ctx->spe_enabled)) { \
8635 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8638 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8639 cpu_gpr[rB(ctx->opcode)]); \
8640 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8641 cpu_gprh[rB(ctx->opcode)]); \
8644 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
8645 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
8646 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
8647 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
8648 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
8649 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
8650 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
8651 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
8653 /* SPE logic immediate */
8654 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8655 static inline void gen_##name(DisasContext *ctx) \
8658 if (unlikely(!ctx->spe_enabled)) { \
8659 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8662 t0 = tcg_temp_new_i32(); \
8664 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8665 tcg_opi(t0, t0, rB(ctx->opcode)); \
8666 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8668 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8669 tcg_opi(t0, t0, rB(ctx->opcode)); \
8670 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8672 tcg_temp_free_i32(t0); \
8674 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
8675 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
8676 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
8677 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
8679 /* SPE arithmetic */
8680 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8681 static inline void gen_##name(DisasContext *ctx) \
8684 if (unlikely(!ctx->spe_enabled)) { \
8685 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8688 t0 = tcg_temp_new_i32(); \
8690 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8692 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8694 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8696 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8698 tcg_temp_free_i32(t0); \
8701 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
8703 TCGLabel
*l1
= gen_new_label();
8704 TCGLabel
*l2
= gen_new_label();
8706 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
8707 tcg_gen_neg_i32(ret
, arg1
);
8710 tcg_gen_mov_i32(ret
, arg1
);
8713 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
8714 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
8715 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
8716 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
8717 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
8719 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
8720 tcg_gen_ext16u_i32(ret
, ret
);
8722 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
8723 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
8724 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
8726 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8727 static inline void gen_##name(DisasContext *ctx) \
8730 if (unlikely(!ctx->spe_enabled)) { \
8731 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8734 t0 = tcg_temp_new_i32(); \
8735 t1 = tcg_temp_new_i32(); \
8737 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8738 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8739 tcg_op(t0, t0, t1); \
8740 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8742 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8743 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8744 tcg_op(t0, t0, t1); \
8745 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8747 tcg_temp_free_i32(t0); \
8748 tcg_temp_free_i32(t1); \
8751 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8753 TCGLabel
*l1
= gen_new_label();
8754 TCGLabel
*l2
= gen_new_label();
8755 TCGv_i32 t0
= tcg_temp_local_new_i32();
8757 /* No error here: 6 bits are used */
8758 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8759 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8760 tcg_gen_shr_i32(ret
, arg1
, t0
);
8763 tcg_gen_movi_i32(ret
, 0);
8765 tcg_temp_free_i32(t0
);
8767 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
8768 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8770 TCGLabel
*l1
= gen_new_label();
8771 TCGLabel
*l2
= gen_new_label();
8772 TCGv_i32 t0
= tcg_temp_local_new_i32();
8774 /* No error here: 6 bits are used */
8775 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8776 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8777 tcg_gen_sar_i32(ret
, arg1
, t0
);
8780 tcg_gen_movi_i32(ret
, 0);
8782 tcg_temp_free_i32(t0
);
8784 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
8785 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8787 TCGLabel
*l1
= gen_new_label();
8788 TCGLabel
*l2
= gen_new_label();
8789 TCGv_i32 t0
= tcg_temp_local_new_i32();
8791 /* No error here: 6 bits are used */
8792 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8793 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8794 tcg_gen_shl_i32(ret
, arg1
, t0
);
8797 tcg_gen_movi_i32(ret
, 0);
8799 tcg_temp_free_i32(t0
);
8801 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
8802 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8804 TCGv_i32 t0
= tcg_temp_new_i32();
8805 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
8806 tcg_gen_rotl_i32(ret
, arg1
, t0
);
8807 tcg_temp_free_i32(t0
);
8809 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
8810 static inline void gen_evmergehi(DisasContext
*ctx
)
8812 if (unlikely(!ctx
->spe_enabled
)) {
8813 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8816 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8817 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8819 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
8820 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8822 tcg_gen_sub_i32(ret
, arg2
, arg1
);
8824 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
8826 /* SPE arithmetic immediate */
8827 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8828 static inline void gen_##name(DisasContext *ctx) \
8831 if (unlikely(!ctx->spe_enabled)) { \
8832 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8835 t0 = tcg_temp_new_i32(); \
8837 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8838 tcg_op(t0, t0, rA(ctx->opcode)); \
8839 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8841 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8842 tcg_op(t0, t0, rA(ctx->opcode)); \
8843 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8845 tcg_temp_free_i32(t0); \
8847 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
8848 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
8850 /* SPE comparison */
8851 #define GEN_SPEOP_COMP(name, tcg_cond) \
8852 static inline void gen_##name(DisasContext *ctx) \
8854 if (unlikely(!ctx->spe_enabled)) { \
8855 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8858 TCGLabel *l1 = gen_new_label(); \
8859 TCGLabel *l2 = gen_new_label(); \
8860 TCGLabel *l3 = gen_new_label(); \
8861 TCGLabel *l4 = gen_new_label(); \
8863 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8864 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8865 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8866 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8868 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8869 cpu_gpr[rB(ctx->opcode)], l1); \
8870 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8872 gen_set_label(l1); \
8873 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8874 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8875 gen_set_label(l2); \
8876 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8877 cpu_gprh[rB(ctx->opcode)], l3); \
8878 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8879 ~(CRF_CH | CRF_CH_AND_CL)); \
8881 gen_set_label(l3); \
8882 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8883 CRF_CH | CRF_CH_OR_CL); \
8884 gen_set_label(l4); \
8886 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
8887 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
8888 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
8889 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
8890 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
8893 static inline void gen_brinc(DisasContext
*ctx
)
8895 /* Note: brinc is usable even if SPE is disabled */
8896 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
8897 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8899 static inline void gen_evmergelo(DisasContext
*ctx
)
8901 if (unlikely(!ctx
->spe_enabled
)) {
8902 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8905 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8906 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8908 static inline void gen_evmergehilo(DisasContext
*ctx
)
8910 if (unlikely(!ctx
->spe_enabled
)) {
8911 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8914 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8915 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8917 static inline void gen_evmergelohi(DisasContext
*ctx
)
8919 if (unlikely(!ctx
->spe_enabled
)) {
8920 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8923 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
8924 TCGv tmp
= tcg_temp_new();
8925 tcg_gen_mov_tl(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
8926 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8927 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
8930 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8931 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8934 static inline void gen_evsplati(DisasContext
*ctx
)
8936 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
8938 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8939 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8941 static inline void gen_evsplatfi(DisasContext
*ctx
)
8943 uint64_t imm
= rA(ctx
->opcode
) << 27;
8945 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8946 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8949 static inline void gen_evsel(DisasContext
*ctx
)
8951 TCGLabel
*l1
= gen_new_label();
8952 TCGLabel
*l2
= gen_new_label();
8953 TCGLabel
*l3
= gen_new_label();
8954 TCGLabel
*l4
= gen_new_label();
8955 TCGv_i32 t0
= tcg_temp_local_new_i32();
8957 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
8958 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
8959 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8962 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8964 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
8965 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
8966 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8969 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8971 tcg_temp_free_i32(t0
);
8974 static void gen_evsel0(DisasContext
*ctx
)
8979 static void gen_evsel1(DisasContext
*ctx
)
8984 static void gen_evsel2(DisasContext
*ctx
)
8989 static void gen_evsel3(DisasContext
*ctx
)
8996 static inline void gen_evmwumi(DisasContext
*ctx
)
9000 if (unlikely(!ctx
->spe_enabled
)) {
9001 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9005 t0
= tcg_temp_new_i64();
9006 t1
= tcg_temp_new_i64();
9008 /* t0 := rA; t1 := rB */
9009 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
9010 tcg_gen_ext32u_i64(t0
, t0
);
9011 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
9012 tcg_gen_ext32u_i64(t1
, t1
);
9014 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
9016 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
9018 tcg_temp_free_i64(t0
);
9019 tcg_temp_free_i64(t1
);
9022 static inline void gen_evmwumia(DisasContext
*ctx
)
9026 if (unlikely(!ctx
->spe_enabled
)) {
9027 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9031 gen_evmwumi(ctx
); /* rD := rA * rB */
9033 tmp
= tcg_temp_new_i64();
9036 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9037 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9038 tcg_temp_free_i64(tmp
);
9041 static inline void gen_evmwumiaa(DisasContext
*ctx
)
9046 if (unlikely(!ctx
->spe_enabled
)) {
9047 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9051 gen_evmwumi(ctx
); /* rD := rA * rB */
9053 acc
= tcg_temp_new_i64();
9054 tmp
= tcg_temp_new_i64();
9057 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9060 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9062 /* acc := tmp + acc */
9063 tcg_gen_add_i64(acc
, acc
, tmp
);
9066 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9069 gen_store_gpr64(rD(ctx
->opcode
), acc
);
9071 tcg_temp_free_i64(acc
);
9072 tcg_temp_free_i64(tmp
);
9075 static inline void gen_evmwsmi(DisasContext
*ctx
)
9079 if (unlikely(!ctx
->spe_enabled
)) {
9080 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9084 t0
= tcg_temp_new_i64();
9085 t1
= tcg_temp_new_i64();
9087 /* t0 := rA; t1 := rB */
9088 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
9089 tcg_gen_ext32s_i64(t0
, t0
);
9090 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
9091 tcg_gen_ext32s_i64(t1
, t1
);
9093 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
9095 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
9097 tcg_temp_free_i64(t0
);
9098 tcg_temp_free_i64(t1
);
9101 static inline void gen_evmwsmia(DisasContext
*ctx
)
9105 gen_evmwsmi(ctx
); /* rD := rA * rB */
9107 tmp
= tcg_temp_new_i64();
9110 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9111 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9113 tcg_temp_free_i64(tmp
);
9116 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
9118 TCGv_i64 acc
= tcg_temp_new_i64();
9119 TCGv_i64 tmp
= tcg_temp_new_i64();
9121 gen_evmwsmi(ctx
); /* rD := rA * rB */
9123 acc
= tcg_temp_new_i64();
9124 tmp
= tcg_temp_new_i64();
9127 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9130 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9132 /* acc := tmp + acc */
9133 tcg_gen_add_i64(acc
, acc
, tmp
);
9136 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9139 gen_store_gpr64(rD(ctx
->opcode
), acc
);
9141 tcg_temp_free_i64(acc
);
9142 tcg_temp_free_i64(tmp
);
9145 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9146 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9147 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9148 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9149 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9150 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9151 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9152 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
9153 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
9154 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9155 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9156 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9157 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9158 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9159 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9160 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9161 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9162 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9163 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9164 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
9165 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9166 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9167 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
9168 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
9169 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9170 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9171 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9172 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9173 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
9175 /* SPE load and stores */
9176 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
9178 target_ulong uimm
= rB(ctx
->opcode
);
9180 if (rA(ctx
->opcode
) == 0) {
9181 tcg_gen_movi_tl(EA
, uimm
<< sh
);
9183 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
9184 if (NARROW_MODE(ctx
)) {
9185 tcg_gen_ext32u_tl(EA
, EA
);
9190 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
9192 TCGv_i64 t0
= tcg_temp_new_i64();
9193 gen_qemu_ld64(ctx
, t0
, addr
);
9194 gen_store_gpr64(rD(ctx
->opcode
), t0
);
9195 tcg_temp_free_i64(t0
);
9198 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
9200 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9201 gen_addr_add(ctx
, addr
, addr
, 4);
9202 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9205 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
9207 TCGv t0
= tcg_temp_new();
9208 gen_qemu_ld16u(ctx
, t0
, addr
);
9209 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9210 gen_addr_add(ctx
, addr
, addr
, 2);
9211 gen_qemu_ld16u(ctx
, t0
, addr
);
9212 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9213 gen_addr_add(ctx
, addr
, addr
, 2);
9214 gen_qemu_ld16u(ctx
, t0
, addr
);
9215 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9216 gen_addr_add(ctx
, addr
, addr
, 2);
9217 gen_qemu_ld16u(ctx
, t0
, addr
);
9218 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
9222 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
9224 TCGv t0
= tcg_temp_new();
9225 gen_qemu_ld16u(ctx
, t0
, addr
);
9226 tcg_gen_shli_tl(t0
, t0
, 16);
9227 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9228 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9232 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
9234 TCGv t0
= tcg_temp_new();
9235 gen_qemu_ld16u(ctx
, t0
, addr
);
9236 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9237 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9241 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
9243 TCGv t0
= tcg_temp_new();
9244 gen_qemu_ld16s(ctx
, t0
, addr
);
9245 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9246 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9250 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
9252 TCGv t0
= tcg_temp_new();
9253 gen_qemu_ld16u(ctx
, t0
, addr
);
9254 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9255 gen_addr_add(ctx
, addr
, addr
, 2);
9256 gen_qemu_ld16u(ctx
, t0
, addr
);
9257 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9261 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
9263 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9264 gen_addr_add(ctx
, addr
, addr
, 2);
9265 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9268 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
9270 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9271 gen_addr_add(ctx
, addr
, addr
, 2);
9272 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9275 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
9277 TCGv t0
= tcg_temp_new();
9278 gen_qemu_ld32u(ctx
, t0
, addr
);
9279 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9280 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9284 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
9286 TCGv t0
= tcg_temp_new();
9287 gen_qemu_ld16u(ctx
, t0
, addr
);
9288 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9289 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9290 gen_addr_add(ctx
, addr
, addr
, 2);
9291 gen_qemu_ld16u(ctx
, t0
, addr
);
9292 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9293 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9297 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
9299 TCGv_i64 t0
= tcg_temp_new_i64();
9300 gen_load_gpr64(t0
, rS(ctx
->opcode
));
9301 gen_qemu_st64(ctx
, t0
, addr
);
9302 tcg_temp_free_i64(t0
);
9305 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
9307 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9308 gen_addr_add(ctx
, addr
, addr
, 4);
9309 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9312 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
9314 TCGv t0
= tcg_temp_new();
9315 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9316 gen_qemu_st16(ctx
, t0
, addr
);
9317 gen_addr_add(ctx
, addr
, addr
, 2);
9318 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9319 gen_addr_add(ctx
, addr
, addr
, 2);
9320 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9321 gen_qemu_st16(ctx
, t0
, addr
);
9323 gen_addr_add(ctx
, addr
, addr
, 2);
9324 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9327 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
9329 TCGv t0
= tcg_temp_new();
9330 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9331 gen_qemu_st16(ctx
, t0
, addr
);
9332 gen_addr_add(ctx
, addr
, addr
, 2);
9333 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9334 gen_qemu_st16(ctx
, t0
, addr
);
9338 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
9340 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9341 gen_addr_add(ctx
, addr
, addr
, 2);
9342 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9345 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
9347 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9350 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
9352 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9355 #define GEN_SPEOP_LDST(name, opc2, sh) \
9356 static void glue(gen_, name)(DisasContext *ctx) \
9359 if (unlikely(!ctx->spe_enabled)) { \
9360 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9363 gen_set_access_type(ctx, ACCESS_INT); \
9364 t0 = tcg_temp_new(); \
9365 if (Rc(ctx->opcode)) { \
9366 gen_addr_spe_imm_index(ctx, t0, sh); \
9368 gen_addr_reg_index(ctx, t0); \
9370 gen_op_##name(ctx, t0); \
9371 tcg_temp_free(t0); \
9374 GEN_SPEOP_LDST(evldd
, 0x00, 3);
9375 GEN_SPEOP_LDST(evldw
, 0x01, 3);
9376 GEN_SPEOP_LDST(evldh
, 0x02, 3);
9377 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
9378 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
9379 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
9380 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
9381 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
9382 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
9383 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
9384 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
9386 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
9387 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
9388 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
9389 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
9390 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
9391 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
9392 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
9394 /* Multiply and add - TODO */
9396 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
9397 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9398 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9399 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9400 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9401 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9402 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9403 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9404 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9405 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9406 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9407 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9409 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9410 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9411 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9412 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9413 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9414 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9415 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9416 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9417 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9418 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9419 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9420 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9422 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9423 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9424 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9425 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9426 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
9428 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9429 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9430 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9431 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9432 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9433 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9434 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9435 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9436 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9437 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9438 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9439 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9441 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9442 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9443 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9444 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9446 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9447 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9448 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9449 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9450 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9451 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9452 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9453 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9454 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9455 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9456 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9457 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9459 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9460 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9461 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9462 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9463 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9466 /*** SPE floating-point extension ***/
9467 #define GEN_SPEFPUOP_CONV_32_32(name) \
9468 static inline void gen_##name(DisasContext *ctx) \
9470 TCGv_i32 t0 = tcg_temp_new_i32(); \
9471 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9472 gen_helper_##name(t0, cpu_env, t0); \
9473 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9474 tcg_temp_free_i32(t0); \
9476 #define GEN_SPEFPUOP_CONV_32_64(name) \
9477 static inline void gen_##name(DisasContext *ctx) \
9479 TCGv_i64 t0 = tcg_temp_new_i64(); \
9480 TCGv_i32 t1 = tcg_temp_new_i32(); \
9481 gen_load_gpr64(t0, rB(ctx->opcode)); \
9482 gen_helper_##name(t1, cpu_env, t0); \
9483 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9484 tcg_temp_free_i64(t0); \
9485 tcg_temp_free_i32(t1); \
9487 #define GEN_SPEFPUOP_CONV_64_32(name) \
9488 static inline void gen_##name(DisasContext *ctx) \
9490 TCGv_i64 t0 = tcg_temp_new_i64(); \
9491 TCGv_i32 t1 = tcg_temp_new_i32(); \
9492 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9493 gen_helper_##name(t0, cpu_env, t1); \
9494 gen_store_gpr64(rD(ctx->opcode), t0); \
9495 tcg_temp_free_i64(t0); \
9496 tcg_temp_free_i32(t1); \
9498 #define GEN_SPEFPUOP_CONV_64_64(name) \
9499 static inline void gen_##name(DisasContext *ctx) \
9501 TCGv_i64 t0 = tcg_temp_new_i64(); \
9502 gen_load_gpr64(t0, rB(ctx->opcode)); \
9503 gen_helper_##name(t0, cpu_env, t0); \
9504 gen_store_gpr64(rD(ctx->opcode), t0); \
9505 tcg_temp_free_i64(t0); \
9507 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9508 static inline void gen_##name(DisasContext *ctx) \
9511 if (unlikely(!ctx->spe_enabled)) { \
9512 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9515 t0 = tcg_temp_new_i32(); \
9516 t1 = tcg_temp_new_i32(); \
9517 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9518 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9519 gen_helper_##name(t0, cpu_env, t0, t1); \
9520 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9522 tcg_temp_free_i32(t0); \
9523 tcg_temp_free_i32(t1); \
9525 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9526 static inline void gen_##name(DisasContext *ctx) \
9529 if (unlikely(!ctx->spe_enabled)) { \
9530 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9533 t0 = tcg_temp_new_i64(); \
9534 t1 = tcg_temp_new_i64(); \
9535 gen_load_gpr64(t0, rA(ctx->opcode)); \
9536 gen_load_gpr64(t1, rB(ctx->opcode)); \
9537 gen_helper_##name(t0, cpu_env, t0, t1); \
9538 gen_store_gpr64(rD(ctx->opcode), t0); \
9539 tcg_temp_free_i64(t0); \
9540 tcg_temp_free_i64(t1); \
9542 #define GEN_SPEFPUOP_COMP_32(name) \
9543 static inline void gen_##name(DisasContext *ctx) \
9546 if (unlikely(!ctx->spe_enabled)) { \
9547 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9550 t0 = tcg_temp_new_i32(); \
9551 t1 = tcg_temp_new_i32(); \
9553 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9554 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9555 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9557 tcg_temp_free_i32(t0); \
9558 tcg_temp_free_i32(t1); \
9560 #define GEN_SPEFPUOP_COMP_64(name) \
9561 static inline void gen_##name(DisasContext *ctx) \
9564 if (unlikely(!ctx->spe_enabled)) { \
9565 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9568 t0 = tcg_temp_new_i64(); \
9569 t1 = tcg_temp_new_i64(); \
9570 gen_load_gpr64(t0, rA(ctx->opcode)); \
9571 gen_load_gpr64(t1, rB(ctx->opcode)); \
9572 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9573 tcg_temp_free_i64(t0); \
9574 tcg_temp_free_i64(t1); \
9577 /* Single precision floating-point vectors operations */
9579 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
9580 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
9581 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
9582 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
9583 static inline void gen_evfsabs(DisasContext
*ctx
)
9585 if (unlikely(!ctx
->spe_enabled
)) {
9586 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9589 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9591 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9594 static inline void gen_evfsnabs(DisasContext
*ctx
)
9596 if (unlikely(!ctx
->spe_enabled
)) {
9597 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9600 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9602 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9605 static inline void gen_evfsneg(DisasContext
*ctx
)
9607 if (unlikely(!ctx
->spe_enabled
)) {
9608 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9611 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9613 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9618 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
9619 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
9620 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
9621 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
9622 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
9623 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
9624 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
9625 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
9626 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
9627 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
9630 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
9631 GEN_SPEFPUOP_COMP_64(evfscmplt
);
9632 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
9633 GEN_SPEFPUOP_COMP_64(evfststgt
);
9634 GEN_SPEFPUOP_COMP_64(evfststlt
);
9635 GEN_SPEFPUOP_COMP_64(evfststeq
);
9637 /* Opcodes definitions */
9638 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9639 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9640 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9641 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9642 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9643 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9644 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9645 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9646 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9647 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9648 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9649 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9650 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9651 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9653 /* Single precision floating-point operations */
9655 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
9656 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
9657 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
9658 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
9659 static inline void gen_efsabs(DisasContext
*ctx
)
9661 if (unlikely(!ctx
->spe_enabled
)) {
9662 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9665 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
9667 static inline void gen_efsnabs(DisasContext
*ctx
)
9669 if (unlikely(!ctx
->spe_enabled
)) {
9670 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9673 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9675 static inline void gen_efsneg(DisasContext
*ctx
)
9677 if (unlikely(!ctx
->spe_enabled
)) {
9678 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9681 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9685 GEN_SPEFPUOP_CONV_32_32(efscfui
);
9686 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
9687 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
9688 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
9689 GEN_SPEFPUOP_CONV_32_32(efsctui
);
9690 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
9691 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
9692 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
9693 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
9694 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
9695 GEN_SPEFPUOP_CONV_32_64(efscfd
);
9698 GEN_SPEFPUOP_COMP_32(efscmpgt
);
9699 GEN_SPEFPUOP_COMP_32(efscmplt
);
9700 GEN_SPEFPUOP_COMP_32(efscmpeq
);
9701 GEN_SPEFPUOP_COMP_32(efststgt
);
9702 GEN_SPEFPUOP_COMP_32(efststlt
);
9703 GEN_SPEFPUOP_COMP_32(efststeq
);
9705 /* Opcodes definitions */
9706 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9707 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9708 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9709 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9710 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9711 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
9712 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9713 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9714 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9715 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9716 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9717 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9718 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9719 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9721 /* Double precision floating-point operations */
9723 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
9724 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
9725 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
9726 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
9727 static inline void gen_efdabs(DisasContext
*ctx
)
9729 if (unlikely(!ctx
->spe_enabled
)) {
9730 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9733 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9734 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9737 static inline void gen_efdnabs(DisasContext
*ctx
)
9739 if (unlikely(!ctx
->spe_enabled
)) {
9740 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9743 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9744 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9747 static inline void gen_efdneg(DisasContext
*ctx
)
9749 if (unlikely(!ctx
->spe_enabled
)) {
9750 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9753 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9754 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9759 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
9760 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
9761 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
9762 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
9763 GEN_SPEFPUOP_CONV_32_64(efdctui
);
9764 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
9765 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
9766 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
9767 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
9768 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
9769 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
9770 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
9771 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
9772 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
9773 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
9776 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
9777 GEN_SPEFPUOP_COMP_64(efdcmplt
);
9778 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
9779 GEN_SPEFPUOP_COMP_64(efdtstgt
);
9780 GEN_SPEFPUOP_COMP_64(efdtstlt
);
9781 GEN_SPEFPUOP_COMP_64(efdtsteq
);
9783 /* Opcodes definitions */
9784 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9785 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9786 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
9787 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9788 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9789 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9790 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9791 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
9792 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9793 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9794 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9795 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9796 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9797 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9798 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9799 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9801 static void gen_tbegin(DisasContext
*ctx
)
9803 if (unlikely(!ctx
->tm_enabled
)) {
9804 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9807 gen_helper_tbegin(cpu_env
);
9810 #define GEN_TM_NOOP(name) \
9811 static inline void gen_##name(DisasContext *ctx) \
9813 if (unlikely(!ctx->tm_enabled)) { \
9814 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9817 /* Because tbegin always fails in QEMU, these user \
9818 * space instructions all have a simple implementation: \
9820 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9821 * = 0b0 || 0b00 || 0b0 \
9823 tcg_gen_movi_i32(cpu_crf[0], 0); \
9827 GEN_TM_NOOP(tabort
);
9828 GEN_TM_NOOP(tabortwc
);
9829 GEN_TM_NOOP(tabortwci
);
9830 GEN_TM_NOOP(tabortdc
);
9831 GEN_TM_NOOP(tabortdci
);
9834 static void gen_tcheck(DisasContext
*ctx
)
9836 if (unlikely(!ctx
->tm_enabled
)) {
9837 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9840 /* Because tbegin always fails, the tcheck implementation
9843 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9844 * = 0b1 || 0b00 || 0b0
9846 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
9849 #if defined(CONFIG_USER_ONLY)
9850 #define GEN_TM_PRIV_NOOP(name) \
9851 static inline void gen_##name(DisasContext *ctx) \
9853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9858 #define GEN_TM_PRIV_NOOP(name) \
9859 static inline void gen_##name(DisasContext *ctx) \
9861 if (unlikely(ctx->pr)) { \
9862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9865 if (unlikely(!ctx->tm_enabled)) { \
9866 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9869 /* Because tbegin always fails, the implementation is \
9872 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9873 * = 0b0 || 0b00 | 0b0 \
9875 tcg_gen_movi_i32(cpu_crf[0], 0); \
9880 GEN_TM_PRIV_NOOP(treclaim
);
9881 GEN_TM_PRIV_NOOP(trechkpt
);
9883 static opcode_t opcodes
[] = {
9884 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
9885 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
9886 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9887 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
9888 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9889 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
9890 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
9891 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9892 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9893 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9894 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9895 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
9896 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
9897 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
9898 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
9899 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9900 #if defined(TARGET_PPC64)
9901 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
9903 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
9904 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
9905 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9906 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9907 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9908 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
9909 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
9910 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
9911 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9912 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9913 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9914 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9915 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
9916 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
9917 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9918 #if defined(TARGET_PPC64)
9919 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
9920 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
9921 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9922 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
9924 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9925 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9926 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9927 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
9928 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
9929 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
9930 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
9931 #if defined(TARGET_PPC64)
9932 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
9933 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
9934 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
9935 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
9936 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
9938 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
9939 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9940 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9941 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
9942 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
9943 GEN_HANDLER(fabs
, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT
),
9944 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
9945 GEN_HANDLER(fnabs
, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT
),
9946 GEN_HANDLER(fneg
, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT
),
9947 GEN_HANDLER_E(fcpsgn
, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE
, PPC2_ISA205
),
9948 GEN_HANDLER_E(fmrgew
, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9949 GEN_HANDLER_E(fmrgow
, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9950 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
9951 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
9952 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
9953 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
9954 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT
),
9955 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT
),
9956 #if defined(TARGET_PPC64)
9957 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9958 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
9959 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9961 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9962 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9963 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
9964 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
9965 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
9966 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
9967 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
9968 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
9969 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9970 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9971 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
9972 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9973 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9974 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
9975 #if defined(TARGET_PPC64)
9976 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
9977 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9978 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
9979 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9981 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
9982 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
9983 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9984 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9985 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
9986 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
9987 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0, PPC_NONE
, PPC2_BCTAR_ISA207
),
9988 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
9989 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
9990 #if defined(TARGET_PPC64)
9991 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
9992 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
9994 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
9995 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
9996 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9997 #if defined(TARGET_PPC64)
9998 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
9999 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
10001 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
10002 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
10003 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
10004 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
10005 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
10006 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
10007 #if defined(TARGET_PPC64)
10008 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
10010 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
10011 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
10012 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
10013 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
10014 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
10015 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
10016 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
10017 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
10018 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
10019 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
10020 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
10021 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
10022 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
10023 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
10024 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
10025 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
10026 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
10027 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
10028 #if defined(TARGET_PPC64)
10029 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
10030 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10032 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
10033 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10035 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
10036 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
10037 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
10038 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
10040 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
10041 /* XXX Those instructions will need to be handled differently for
10042 * different ISA versions */
10043 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
10044 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
10045 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
10046 #if defined(TARGET_PPC64)
10047 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
10048 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
10050 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
10051 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
10052 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
10053 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
10054 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
10055 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
10056 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
10057 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
10058 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
10059 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
10060 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
10061 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
10062 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
10063 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
10064 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
10065 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
10066 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
10067 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
10068 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
10069 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
10070 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
10071 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
10072 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
10073 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
10074 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
10075 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
10076 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
10077 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
10078 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
10079 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
10080 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
10081 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
10082 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
10083 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
10084 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
10085 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
10086 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
10087 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
10088 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
10089 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
10090 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
10091 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
10092 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
10093 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
10094 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
10095 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
10096 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
10097 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
10098 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
10099 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10100 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10101 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
10102 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
10103 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10104 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10105 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
10106 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
10107 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
10108 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
10109 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
10110 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
10111 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
10112 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
10113 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
10114 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
10115 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
10116 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
10117 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
10118 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
10119 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
10120 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
10121 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
10122 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
10123 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
10124 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
10125 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
10126 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
10127 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
10128 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
10129 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
10130 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10131 PPC_NONE
, PPC2_BOOKE206
),
10132 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10133 PPC_NONE
, PPC2_BOOKE206
),
10134 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10135 PPC_NONE
, PPC2_BOOKE206
),
10136 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10137 PPC_NONE
, PPC2_BOOKE206
),
10138 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10139 PPC_NONE
, PPC2_BOOKE206
),
10140 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10141 PPC_NONE
, PPC2_PRCNTL
),
10142 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10143 PPC_NONE
, PPC2_PRCNTL
),
10144 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
10145 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
10146 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
10147 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
10148 PPC_BOOKE
, PPC2_BOOKE206
),
10149 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
10150 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10151 PPC_BOOKE
, PPC2_BOOKE206
),
10152 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
10153 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
10154 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
10155 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
10156 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
10157 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
10158 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
10159 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
10160 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
10162 #undef GEN_INT_ARITH_ADD
10163 #undef GEN_INT_ARITH_ADD_CONST
10164 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10165 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10166 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10167 add_ca, compute_ca, compute_ov) \
10168 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10169 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
10170 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
10171 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
10172 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
10173 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
10174 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
10175 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
10176 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
10177 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
10178 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
10180 #undef GEN_INT_ARITH_DIVW
10181 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10182 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10183 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
10184 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
10185 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
10186 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
10187 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10188 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10189 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10190 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10192 #if defined(TARGET_PPC64)
10193 #undef GEN_INT_ARITH_DIVD
10194 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10195 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10196 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
10197 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
10198 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
10199 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
10201 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10202 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10203 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10204 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10206 #undef GEN_INT_ARITH_MUL_HELPER
10207 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10208 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10209 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
10210 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
10211 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
10214 #undef GEN_INT_ARITH_SUBF
10215 #undef GEN_INT_ARITH_SUBF_CONST
10216 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10217 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10218 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10219 add_ca, compute_ca, compute_ov) \
10220 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10221 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
10222 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
10223 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
10224 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
10225 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
10226 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
10227 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
10228 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
10229 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
10230 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
10232 #undef GEN_LOGICAL1
10233 #undef GEN_LOGICAL2
10234 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10235 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10236 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10237 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10238 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
10239 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
10240 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
10241 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
10242 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
10243 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
10244 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
10245 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
10246 #if defined(TARGET_PPC64)
10247 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
10250 #if defined(TARGET_PPC64)
10251 #undef GEN_PPC64_R2
10252 #undef GEN_PPC64_R4
10253 #define GEN_PPC64_R2(name, opc1, opc2) \
10254 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10255 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10257 #define GEN_PPC64_R4(name, opc1, opc2) \
10258 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10259 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10261 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10263 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10265 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
10266 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
10267 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
10268 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
10269 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
10270 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
10273 #undef _GEN_FLOAT_ACB
10274 #undef GEN_FLOAT_ACB
10275 #undef _GEN_FLOAT_AB
10276 #undef GEN_FLOAT_AB
10277 #undef _GEN_FLOAT_AC
10278 #undef GEN_FLOAT_AC
10280 #undef GEN_FLOAT_BS
10281 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10282 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10283 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10284 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10285 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10286 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10287 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10288 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10289 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10290 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10291 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10292 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10293 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10294 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10295 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10296 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10297 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10298 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10299 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10301 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
10302 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
10303 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
10304 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
10305 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
10306 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
10307 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
10308 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
10309 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
10310 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
10311 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
10312 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
10313 GEN_HANDLER_E(ftdiv
, 0x3F, 0x00, 0x04, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10314 GEN_HANDLER_E(ftsqrt
, 0x3F, 0x00, 0x05, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10315 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
10316 GEN_HANDLER_E(fctiwu
, 0x3F, 0x0E, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10317 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
10318 GEN_HANDLER_E(fctiwuz
, 0x3F, 0x0F, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10319 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
10320 GEN_HANDLER_E(fcfid
, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10321 GEN_HANDLER_E(fcfids
, 0x3B, 0x0E, 0x1A, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10322 GEN_HANDLER_E(fcfidu
, 0x3F, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10323 GEN_HANDLER_E(fcfidus
, 0x3B, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10324 GEN_HANDLER_E(fctid
, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10325 GEN_HANDLER_E(fctidu
, 0x3F, 0x0E, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10326 GEN_HANDLER_E(fctidz
, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10327 GEN_HANDLER_E(fctiduz
, 0x3F, 0x0F, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10328 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
10329 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
10330 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
10331 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
10338 #define GEN_LD(name, ldop, opc, type) \
10339 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10340 #define GEN_LDU(name, ldop, opc, type) \
10341 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10342 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10343 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10344 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10345 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10346 #define GEN_LDS(name, ldop, op, type) \
10347 GEN_LD(name, ldop, op | 0x20, type) \
10348 GEN_LDU(name, ldop, op | 0x21, type) \
10349 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10350 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10352 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
10353 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
10354 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
10355 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
10356 #if defined(TARGET_PPC64)
10357 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
10358 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
10359 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
10360 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
10361 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
10363 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
10364 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
10371 #define GEN_ST(name, stop, opc, type) \
10372 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10373 #define GEN_STU(name, stop, opc, type) \
10374 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10375 #define GEN_STUX(name, stop, opc2, opc3, type) \
10376 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10377 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10378 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10379 #define GEN_STS(name, stop, op, type) \
10380 GEN_ST(name, stop, op | 0x20, type) \
10381 GEN_STU(name, stop, op | 0x21, type) \
10382 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10383 GEN_STX(name, stop, 0x17, op | 0x00, type)
10385 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
10386 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
10387 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
10388 #if defined(TARGET_PPC64)
10389 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
10390 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
10391 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
10393 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
10394 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
10401 #define GEN_LDF(name, ldop, opc, type) \
10402 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10403 #define GEN_LDUF(name, ldop, opc, type) \
10404 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10405 #define GEN_LDUXF(name, ldop, opc, type) \
10406 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10407 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10408 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10409 #define GEN_LDFS(name, ldop, op, type) \
10410 GEN_LDF(name, ldop, op | 0x20, type) \
10411 GEN_LDUF(name, ldop, op | 0x21, type) \
10412 GEN_LDUXF(name, ldop, op | 0x01, type) \
10413 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10415 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
10416 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
10417 GEN_HANDLER_E(lfiwax
, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE
, PPC2_ISA205
),
10418 GEN_HANDLER_E(lfiwzx
, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10419 GEN_HANDLER_E(lfdp
, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10420 GEN_HANDLER_E(lfdpx
, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10427 #define GEN_STF(name, stop, opc, type) \
10428 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10429 #define GEN_STUF(name, stop, opc, type) \
10430 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10431 #define GEN_STUXF(name, stop, opc, type) \
10432 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10433 #define GEN_STXF(name, stop, opc2, opc3, type) \
10434 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10435 #define GEN_STFS(name, stop, op, type) \
10436 GEN_STF(name, stop, op | 0x20, type) \
10437 GEN_STUF(name, stop, op | 0x21, type) \
10438 GEN_STUXF(name, stop, op | 0x01, type) \
10439 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10441 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
10442 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
10443 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
10444 GEN_HANDLER_E(stfdp
, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10445 GEN_HANDLER_E(stfdpx
, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10448 #define GEN_CRLOGIC(name, tcg_op, opc) \
10449 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10450 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
10451 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
10452 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
10453 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
10454 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
10455 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
10456 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
10457 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
10459 #undef GEN_MAC_HANDLER
10460 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10461 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10462 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
10463 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
10464 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
10465 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
10466 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
10467 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
10468 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
10469 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
10470 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
10471 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
10472 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
10473 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
10474 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
10475 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
10476 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
10477 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
10478 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
10479 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
10480 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
10481 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
10482 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
10483 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
10484 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
10485 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
10486 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
10487 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
10488 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
10489 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
10490 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
10491 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
10492 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
10493 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
10494 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
10495 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
10496 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
10497 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
10498 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
10499 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
10500 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
10501 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
10502 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
10503 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
10509 #define GEN_VR_LDX(name, opc2, opc3) \
10510 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10511 #define GEN_VR_STX(name, opc2, opc3) \
10512 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10513 #define GEN_VR_LVE(name, opc2, opc3) \
10514 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10515 #define GEN_VR_STVE(name, opc2, opc3) \
10516 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10517 GEN_VR_LDX(lvx
, 0x07, 0x03),
10518 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
10519 GEN_VR_LVE(bx
, 0x07, 0x00),
10520 GEN_VR_LVE(hx
, 0x07, 0x01),
10521 GEN_VR_LVE(wx
, 0x07, 0x02),
10522 GEN_VR_STX(svx
, 0x07, 0x07),
10523 GEN_VR_STX(svxl
, 0x07, 0x0F),
10524 GEN_VR_STVE(bx
, 0x07, 0x04),
10525 GEN_VR_STVE(hx
, 0x07, 0x05),
10526 GEN_VR_STVE(wx
, 0x07, 0x06),
10528 #undef GEN_VX_LOGICAL
10529 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10530 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10532 #undef GEN_VX_LOGICAL_207
10533 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10534 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10536 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
10537 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
10538 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
10539 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
10540 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
10541 GEN_VX_LOGICAL_207(veqv
, tcg_gen_eqv_i64
, 2, 26),
10542 GEN_VX_LOGICAL_207(vnand
, tcg_gen_nand_i64
, 2, 22),
10543 GEN_VX_LOGICAL_207(vorc
, tcg_gen_orc_i64
, 2, 21),
10546 #define GEN_VXFORM(name, opc2, opc3) \
10547 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10549 #undef GEN_VXFORM_207
10550 #define GEN_VXFORM_207(name, opc2, opc3) \
10551 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10553 #undef GEN_VXFORM_DUAL
10554 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10555 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10557 #undef GEN_VXRFORM_DUAL
10558 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10559 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10560 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10562 GEN_VXFORM(vaddubm
, 0, 0),
10563 GEN_VXFORM(vadduhm
, 0, 1),
10564 GEN_VXFORM(vadduwm
, 0, 2),
10565 GEN_VXFORM_207(vaddudm
, 0, 3),
10566 GEN_VXFORM_DUAL(vsububm
, bcdadd
, 0, 16, PPC_ALTIVEC
, PPC_NONE
),
10567 GEN_VXFORM_DUAL(vsubuhm
, bcdsub
, 0, 17, PPC_ALTIVEC
, PPC_NONE
),
10568 GEN_VXFORM(vsubuwm
, 0, 18),
10569 GEN_VXFORM_207(vsubudm
, 0, 19),
10570 GEN_VXFORM(vmaxub
, 1, 0),
10571 GEN_VXFORM(vmaxuh
, 1, 1),
10572 GEN_VXFORM(vmaxuw
, 1, 2),
10573 GEN_VXFORM_207(vmaxud
, 1, 3),
10574 GEN_VXFORM(vmaxsb
, 1, 4),
10575 GEN_VXFORM(vmaxsh
, 1, 5),
10576 GEN_VXFORM(vmaxsw
, 1, 6),
10577 GEN_VXFORM_207(vmaxsd
, 1, 7),
10578 GEN_VXFORM(vminub
, 1, 8),
10579 GEN_VXFORM(vminuh
, 1, 9),
10580 GEN_VXFORM(vminuw
, 1, 10),
10581 GEN_VXFORM_207(vminud
, 1, 11),
10582 GEN_VXFORM(vminsb
, 1, 12),
10583 GEN_VXFORM(vminsh
, 1, 13),
10584 GEN_VXFORM(vminsw
, 1, 14),
10585 GEN_VXFORM_207(vminsd
, 1, 15),
10586 GEN_VXFORM(vavgub
, 1, 16),
10587 GEN_VXFORM(vavguh
, 1, 17),
10588 GEN_VXFORM(vavguw
, 1, 18),
10589 GEN_VXFORM(vavgsb
, 1, 20),
10590 GEN_VXFORM(vavgsh
, 1, 21),
10591 GEN_VXFORM(vavgsw
, 1, 22),
10592 GEN_VXFORM(vmrghb
, 6, 0),
10593 GEN_VXFORM(vmrghh
, 6, 1),
10594 GEN_VXFORM(vmrghw
, 6, 2),
10595 GEN_VXFORM(vmrglb
, 6, 4),
10596 GEN_VXFORM(vmrglh
, 6, 5),
10597 GEN_VXFORM(vmrglw
, 6, 6),
10598 GEN_VXFORM_207(vmrgew
, 6, 30),
10599 GEN_VXFORM_207(vmrgow
, 6, 26),
10600 GEN_VXFORM(vmuloub
, 4, 0),
10601 GEN_VXFORM(vmulouh
, 4, 1),
10602 GEN_VXFORM_DUAL(vmulouw
, vmuluwm
, 4, 2, PPC_ALTIVEC
, PPC_NONE
),
10603 GEN_VXFORM(vmulosb
, 4, 4),
10604 GEN_VXFORM(vmulosh
, 4, 5),
10605 GEN_VXFORM_207(vmulosw
, 4, 6),
10606 GEN_VXFORM(vmuleub
, 4, 8),
10607 GEN_VXFORM(vmuleuh
, 4, 9),
10608 GEN_VXFORM_207(vmuleuw
, 4, 10),
10609 GEN_VXFORM(vmulesb
, 4, 12),
10610 GEN_VXFORM(vmulesh
, 4, 13),
10611 GEN_VXFORM_207(vmulesw
, 4, 14),
10612 GEN_VXFORM(vslb
, 2, 4),
10613 GEN_VXFORM(vslh
, 2, 5),
10614 GEN_VXFORM(vslw
, 2, 6),
10615 GEN_VXFORM_207(vsld
, 2, 23),
10616 GEN_VXFORM(vsrb
, 2, 8),
10617 GEN_VXFORM(vsrh
, 2, 9),
10618 GEN_VXFORM(vsrw
, 2, 10),
10619 GEN_VXFORM_207(vsrd
, 2, 27),
10620 GEN_VXFORM(vsrab
, 2, 12),
10621 GEN_VXFORM(vsrah
, 2, 13),
10622 GEN_VXFORM(vsraw
, 2, 14),
10623 GEN_VXFORM_207(vsrad
, 2, 15),
10624 GEN_VXFORM(vslo
, 6, 16),
10625 GEN_VXFORM(vsro
, 6, 17),
10626 GEN_VXFORM(vaddcuw
, 0, 6),
10627 GEN_VXFORM(vsubcuw
, 0, 22),
10628 GEN_VXFORM(vaddubs
, 0, 8),
10629 GEN_VXFORM(vadduhs
, 0, 9),
10630 GEN_VXFORM(vadduws
, 0, 10),
10631 GEN_VXFORM(vaddsbs
, 0, 12),
10632 GEN_VXFORM(vaddshs
, 0, 13),
10633 GEN_VXFORM(vaddsws
, 0, 14),
10634 GEN_VXFORM_DUAL(vsububs
, bcdadd
, 0, 24, PPC_ALTIVEC
, PPC_NONE
),
10635 GEN_VXFORM_DUAL(vsubuhs
, bcdsub
, 0, 25, PPC_ALTIVEC
, PPC_NONE
),
10636 GEN_VXFORM(vsubuws
, 0, 26),
10637 GEN_VXFORM(vsubsbs
, 0, 28),
10638 GEN_VXFORM(vsubshs
, 0, 29),
10639 GEN_VXFORM(vsubsws
, 0, 30),
10640 GEN_VXFORM_207(vadduqm
, 0, 4),
10641 GEN_VXFORM_207(vaddcuq
, 0, 5),
10642 GEN_VXFORM_DUAL(vaddeuqm
, vaddecuq
, 30, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10643 GEN_VXFORM_207(vsubuqm
, 0, 20),
10644 GEN_VXFORM_207(vsubcuq
, 0, 21),
10645 GEN_VXFORM_DUAL(vsubeuqm
, vsubecuq
, 31, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10646 GEN_VXFORM(vrlb
, 2, 0),
10647 GEN_VXFORM(vrlh
, 2, 1),
10648 GEN_VXFORM(vrlw
, 2, 2),
10649 GEN_VXFORM_207(vrld
, 2, 3),
10650 GEN_VXFORM(vsl
, 2, 7),
10651 GEN_VXFORM(vsr
, 2, 11),
10652 GEN_VXFORM(vpkuhum
, 7, 0),
10653 GEN_VXFORM(vpkuwum
, 7, 1),
10654 GEN_VXFORM_207(vpkudum
, 7, 17),
10655 GEN_VXFORM(vpkuhus
, 7, 2),
10656 GEN_VXFORM(vpkuwus
, 7, 3),
10657 GEN_VXFORM_207(vpkudus
, 7, 19),
10658 GEN_VXFORM(vpkshus
, 7, 4),
10659 GEN_VXFORM(vpkswus
, 7, 5),
10660 GEN_VXFORM_207(vpksdus
, 7, 21),
10661 GEN_VXFORM(vpkshss
, 7, 6),
10662 GEN_VXFORM(vpkswss
, 7, 7),
10663 GEN_VXFORM_207(vpksdss
, 7, 23),
10664 GEN_VXFORM(vpkpx
, 7, 12),
10665 GEN_VXFORM(vsum4ubs
, 4, 24),
10666 GEN_VXFORM(vsum4sbs
, 4, 28),
10667 GEN_VXFORM(vsum4shs
, 4, 25),
10668 GEN_VXFORM(vsum2sws
, 4, 26),
10669 GEN_VXFORM(vsumsws
, 4, 30),
10670 GEN_VXFORM(vaddfp
, 5, 0),
10671 GEN_VXFORM(vsubfp
, 5, 1),
10672 GEN_VXFORM(vmaxfp
, 5, 16),
10673 GEN_VXFORM(vminfp
, 5, 17),
10675 #undef GEN_VXRFORM1
10677 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10678 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10679 #define GEN_VXRFORM(name, opc2, opc3) \
10680 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10681 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10682 GEN_VXRFORM(vcmpequb
, 3, 0)
10683 GEN_VXRFORM(vcmpequh
, 3, 1)
10684 GEN_VXRFORM(vcmpequw
, 3, 2)
10685 GEN_VXRFORM(vcmpgtsb
, 3, 12)
10686 GEN_VXRFORM(vcmpgtsh
, 3, 13)
10687 GEN_VXRFORM(vcmpgtsw
, 3, 14)
10688 GEN_VXRFORM(vcmpgtub
, 3, 8)
10689 GEN_VXRFORM(vcmpgtuh
, 3, 9)
10690 GEN_VXRFORM(vcmpgtuw
, 3, 10)
10691 GEN_VXRFORM_DUAL(vcmpeqfp
, vcmpequd
, 3, 3, PPC_ALTIVEC
, PPC_NONE
)
10692 GEN_VXRFORM(vcmpgefp
, 3, 7)
10693 GEN_VXRFORM_DUAL(vcmpgtfp
, vcmpgtud
, 3, 11, PPC_ALTIVEC
, PPC_NONE
)
10694 GEN_VXRFORM_DUAL(vcmpbfp
, vcmpgtsd
, 3, 15, PPC_ALTIVEC
, PPC_NONE
)
10696 #undef GEN_VXFORM_SIMM
10697 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10698 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10699 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
10700 GEN_VXFORM_SIMM(vspltish
, 6, 13),
10701 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
10703 #undef GEN_VXFORM_NOA
10704 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10705 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10706 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
10707 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
10708 GEN_VXFORM_207(vupkhsw
, 7, 25),
10709 GEN_VXFORM_NOA(vupklsb
, 7, 10),
10710 GEN_VXFORM_NOA(vupklsh
, 7, 11),
10711 GEN_VXFORM_207(vupklsw
, 7, 27),
10712 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
10713 GEN_VXFORM_NOA(vupklpx
, 7, 15),
10714 GEN_VXFORM_NOA(vrefp
, 5, 4),
10715 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
10716 GEN_VXFORM_NOA(vexptefp
, 5, 6),
10717 GEN_VXFORM_NOA(vlogefp
, 5, 7),
10718 GEN_VXFORM_NOA(vrfim
, 5, 11),
10719 GEN_VXFORM_NOA(vrfin
, 5, 8),
10720 GEN_VXFORM_NOA(vrfip
, 5, 10),
10721 GEN_VXFORM_NOA(vrfiz
, 5, 9),
10723 #undef GEN_VXFORM_UIMM
10724 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10725 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10726 GEN_VXFORM_UIMM(vspltb
, 6, 8),
10727 GEN_VXFORM_UIMM(vsplth
, 6, 9),
10728 GEN_VXFORM_UIMM(vspltw
, 6, 10),
10729 GEN_VXFORM_UIMM(vcfux
, 5, 12),
10730 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
10731 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
10732 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
10734 #undef GEN_VAFORM_PAIRED
10735 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10736 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10737 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
10738 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
10739 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
10740 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
10741 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
10742 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
10744 GEN_VXFORM_DUAL(vclzb
, vpopcntb
, 1, 28, PPC_NONE
, PPC2_ALTIVEC_207
),
10745 GEN_VXFORM_DUAL(vclzh
, vpopcnth
, 1, 29, PPC_NONE
, PPC2_ALTIVEC_207
),
10746 GEN_VXFORM_DUAL(vclzw
, vpopcntw
, 1, 30, PPC_NONE
, PPC2_ALTIVEC_207
),
10747 GEN_VXFORM_DUAL(vclzd
, vpopcntd
, 1, 31, PPC_NONE
, PPC2_ALTIVEC_207
),
10749 GEN_VXFORM_207(vbpermq
, 6, 21),
10750 GEN_VXFORM_207(vgbbd
, 6, 20),
10751 GEN_VXFORM_207(vpmsumb
, 4, 16),
10752 GEN_VXFORM_207(vpmsumh
, 4, 17),
10753 GEN_VXFORM_207(vpmsumw
, 4, 18),
10754 GEN_VXFORM_207(vpmsumd
, 4, 19),
10756 GEN_VXFORM_207(vsbox
, 4, 23),
10758 GEN_VXFORM_DUAL(vcipher
, vcipherlast
, 4, 20, PPC_NONE
, PPC2_ALTIVEC_207
),
10759 GEN_VXFORM_DUAL(vncipher
, vncipherlast
, 4, 21, PPC_NONE
, PPC2_ALTIVEC_207
),
10761 GEN_VXFORM_207(vshasigmaw
, 1, 26),
10762 GEN_VXFORM_207(vshasigmad
, 1, 27),
10764 GEN_VXFORM_DUAL(vsldoi
, vpermxor
, 22, 0xFF, PPC_ALTIVEC
, PPC_NONE
),
10766 GEN_HANDLER_E(lxsdx
, 0x1F, 0x0C, 0x12, 0, PPC_NONE
, PPC2_VSX
),
10767 GEN_HANDLER_E(lxsiwax
, 0x1F, 0x0C, 0x02, 0, PPC_NONE
, PPC2_VSX207
),
10768 GEN_HANDLER_E(lxsiwzx
, 0x1F, 0x0C, 0x00, 0, PPC_NONE
, PPC2_VSX207
),
10769 GEN_HANDLER_E(lxsspx
, 0x1F, 0x0C, 0x10, 0, PPC_NONE
, PPC2_VSX207
),
10770 GEN_HANDLER_E(lxvd2x
, 0x1F, 0x0C, 0x1A, 0, PPC_NONE
, PPC2_VSX
),
10771 GEN_HANDLER_E(lxvdsx
, 0x1F, 0x0C, 0x0A, 0, PPC_NONE
, PPC2_VSX
),
10772 GEN_HANDLER_E(lxvw4x
, 0x1F, 0x0C, 0x18, 0, PPC_NONE
, PPC2_VSX
),
10774 GEN_HANDLER_E(stxsdx
, 0x1F, 0xC, 0x16, 0, PPC_NONE
, PPC2_VSX
),
10775 GEN_HANDLER_E(stxsiwx
, 0x1F, 0xC, 0x04, 0, PPC_NONE
, PPC2_VSX207
),
10776 GEN_HANDLER_E(stxsspx
, 0x1F, 0xC, 0x14, 0, PPC_NONE
, PPC2_VSX207
),
10777 GEN_HANDLER_E(stxvd2x
, 0x1F, 0xC, 0x1E, 0, PPC_NONE
, PPC2_VSX
),
10778 GEN_HANDLER_E(stxvw4x
, 0x1F, 0xC, 0x1C, 0, PPC_NONE
, PPC2_VSX
),
10780 GEN_HANDLER_E(mfvsrwz
, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10781 GEN_HANDLER_E(mtvsrwa
, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10782 GEN_HANDLER_E(mtvsrwz
, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10783 #if defined(TARGET_PPC64)
10784 GEN_HANDLER_E(mfvsrd
, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10785 GEN_HANDLER_E(mtvsrd
, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10789 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10790 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10791 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10794 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10795 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10796 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10797 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10798 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10800 #undef GEN_XX2IFORM
10801 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10802 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10803 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10804 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10805 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10807 #undef GEN_XX3_RC_FORM
10808 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10809 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10810 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10811 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10812 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10813 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10814 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10815 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10816 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10818 #undef GEN_XX3FORM_DM
10819 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10820 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10821 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10822 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10823 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10824 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10825 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10826 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10827 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10828 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10829 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10830 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10831 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10832 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10833 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10834 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10835 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10837 GEN_XX2FORM(xsabsdp
, 0x12, 0x15, PPC2_VSX
),
10838 GEN_XX2FORM(xsnabsdp
, 0x12, 0x16, PPC2_VSX
),
10839 GEN_XX2FORM(xsnegdp
, 0x12, 0x17, PPC2_VSX
),
10840 GEN_XX3FORM(xscpsgndp
, 0x00, 0x16, PPC2_VSX
),
10842 GEN_XX2FORM(xvabsdp
, 0x12, 0x1D, PPC2_VSX
),
10843 GEN_XX2FORM(xvnabsdp
, 0x12, 0x1E, PPC2_VSX
),
10844 GEN_XX2FORM(xvnegdp
, 0x12, 0x1F, PPC2_VSX
),
10845 GEN_XX3FORM(xvcpsgndp
, 0x00, 0x1E, PPC2_VSX
),
10846 GEN_XX2FORM(xvabssp
, 0x12, 0x19, PPC2_VSX
),
10847 GEN_XX2FORM(xvnabssp
, 0x12, 0x1A, PPC2_VSX
),
10848 GEN_XX2FORM(xvnegsp
, 0x12, 0x1B, PPC2_VSX
),
10849 GEN_XX3FORM(xvcpsgnsp
, 0x00, 0x1A, PPC2_VSX
),
10851 GEN_XX3FORM(xsadddp
, 0x00, 0x04, PPC2_VSX
),
10852 GEN_XX3FORM(xssubdp
, 0x00, 0x05, PPC2_VSX
),
10853 GEN_XX3FORM(xsmuldp
, 0x00, 0x06, PPC2_VSX
),
10854 GEN_XX3FORM(xsdivdp
, 0x00, 0x07, PPC2_VSX
),
10855 GEN_XX2FORM(xsredp
, 0x14, 0x05, PPC2_VSX
),
10856 GEN_XX2FORM(xssqrtdp
, 0x16, 0x04, PPC2_VSX
),
10857 GEN_XX2FORM(xsrsqrtedp
, 0x14, 0x04, PPC2_VSX
),
10858 GEN_XX3FORM(xstdivdp
, 0x14, 0x07, PPC2_VSX
),
10859 GEN_XX2FORM(xstsqrtdp
, 0x14, 0x06, PPC2_VSX
),
10860 GEN_XX3FORM(xsmaddadp
, 0x04, 0x04, PPC2_VSX
),
10861 GEN_XX3FORM(xsmaddmdp
, 0x04, 0x05, PPC2_VSX
),
10862 GEN_XX3FORM(xsmsubadp
, 0x04, 0x06, PPC2_VSX
),
10863 GEN_XX3FORM(xsmsubmdp
, 0x04, 0x07, PPC2_VSX
),
10864 GEN_XX3FORM(xsnmaddadp
, 0x04, 0x14, PPC2_VSX
),
10865 GEN_XX3FORM(xsnmaddmdp
, 0x04, 0x15, PPC2_VSX
),
10866 GEN_XX3FORM(xsnmsubadp
, 0x04, 0x16, PPC2_VSX
),
10867 GEN_XX3FORM(xsnmsubmdp
, 0x04, 0x17, PPC2_VSX
),
10868 GEN_XX2IFORM(xscmpodp
, 0x0C, 0x05, PPC2_VSX
),
10869 GEN_XX2IFORM(xscmpudp
, 0x0C, 0x04, PPC2_VSX
),
10870 GEN_XX3FORM(xsmaxdp
, 0x00, 0x14, PPC2_VSX
),
10871 GEN_XX3FORM(xsmindp
, 0x00, 0x15, PPC2_VSX
),
10872 GEN_XX2FORM(xscvdpsp
, 0x12, 0x10, PPC2_VSX
),
10873 GEN_XX2FORM(xscvdpspn
, 0x16, 0x10, PPC2_VSX207
),
10874 GEN_XX2FORM(xscvspdp
, 0x12, 0x14, PPC2_VSX
),
10875 GEN_XX2FORM(xscvspdpn
, 0x16, 0x14, PPC2_VSX207
),
10876 GEN_XX2FORM(xscvdpsxds
, 0x10, 0x15, PPC2_VSX
),
10877 GEN_XX2FORM(xscvdpsxws
, 0x10, 0x05, PPC2_VSX
),
10878 GEN_XX2FORM(xscvdpuxds
, 0x10, 0x14, PPC2_VSX
),
10879 GEN_XX2FORM(xscvdpuxws
, 0x10, 0x04, PPC2_VSX
),
10880 GEN_XX2FORM(xscvsxddp
, 0x10, 0x17, PPC2_VSX
),
10881 GEN_XX2FORM(xscvuxddp
, 0x10, 0x16, PPC2_VSX
),
10882 GEN_XX2FORM(xsrdpi
, 0x12, 0x04, PPC2_VSX
),
10883 GEN_XX2FORM(xsrdpic
, 0x16, 0x06, PPC2_VSX
),
10884 GEN_XX2FORM(xsrdpim
, 0x12, 0x07, PPC2_VSX
),
10885 GEN_XX2FORM(xsrdpip
, 0x12, 0x06, PPC2_VSX
),
10886 GEN_XX2FORM(xsrdpiz
, 0x12, 0x05, PPC2_VSX
),
10888 GEN_XX3FORM(xsaddsp
, 0x00, 0x00, PPC2_VSX207
),
10889 GEN_XX3FORM(xssubsp
, 0x00, 0x01, PPC2_VSX207
),
10890 GEN_XX3FORM(xsmulsp
, 0x00, 0x02, PPC2_VSX207
),
10891 GEN_XX3FORM(xsdivsp
, 0x00, 0x03, PPC2_VSX207
),
10892 GEN_XX2FORM(xsresp
, 0x14, 0x01, PPC2_VSX207
),
10893 GEN_XX2FORM(xsrsp
, 0x12, 0x11, PPC2_VSX207
),
10894 GEN_XX2FORM(xssqrtsp
, 0x16, 0x00, PPC2_VSX207
),
10895 GEN_XX2FORM(xsrsqrtesp
, 0x14, 0x00, PPC2_VSX207
),
10896 GEN_XX3FORM(xsmaddasp
, 0x04, 0x00, PPC2_VSX207
),
10897 GEN_XX3FORM(xsmaddmsp
, 0x04, 0x01, PPC2_VSX207
),
10898 GEN_XX3FORM(xsmsubasp
, 0x04, 0x02, PPC2_VSX207
),
10899 GEN_XX3FORM(xsmsubmsp
, 0x04, 0x03, PPC2_VSX207
),
10900 GEN_XX3FORM(xsnmaddasp
, 0x04, 0x10, PPC2_VSX207
),
10901 GEN_XX3FORM(xsnmaddmsp
, 0x04, 0x11, PPC2_VSX207
),
10902 GEN_XX3FORM(xsnmsubasp
, 0x04, 0x12, PPC2_VSX207
),
10903 GEN_XX3FORM(xsnmsubmsp
, 0x04, 0x13, PPC2_VSX207
),
10904 GEN_XX2FORM(xscvsxdsp
, 0x10, 0x13, PPC2_VSX207
),
10905 GEN_XX2FORM(xscvuxdsp
, 0x10, 0x12, PPC2_VSX207
),
10907 GEN_XX3FORM(xvadddp
, 0x00, 0x0C, PPC2_VSX
),
10908 GEN_XX3FORM(xvsubdp
, 0x00, 0x0D, PPC2_VSX
),
10909 GEN_XX3FORM(xvmuldp
, 0x00, 0x0E, PPC2_VSX
),
10910 GEN_XX3FORM(xvdivdp
, 0x00, 0x0F, PPC2_VSX
),
10911 GEN_XX2FORM(xvredp
, 0x14, 0x0D, PPC2_VSX
),
10912 GEN_XX2FORM(xvsqrtdp
, 0x16, 0x0C, PPC2_VSX
),
10913 GEN_XX2FORM(xvrsqrtedp
, 0x14, 0x0C, PPC2_VSX
),
10914 GEN_XX3FORM(xvtdivdp
, 0x14, 0x0F, PPC2_VSX
),
10915 GEN_XX2FORM(xvtsqrtdp
, 0x14, 0x0E, PPC2_VSX
),
10916 GEN_XX3FORM(xvmaddadp
, 0x04, 0x0C, PPC2_VSX
),
10917 GEN_XX3FORM(xvmaddmdp
, 0x04, 0x0D, PPC2_VSX
),
10918 GEN_XX3FORM(xvmsubadp
, 0x04, 0x0E, PPC2_VSX
),
10919 GEN_XX3FORM(xvmsubmdp
, 0x04, 0x0F, PPC2_VSX
),
10920 GEN_XX3FORM(xvnmaddadp
, 0x04, 0x1C, PPC2_VSX
),
10921 GEN_XX3FORM(xvnmaddmdp
, 0x04, 0x1D, PPC2_VSX
),
10922 GEN_XX3FORM(xvnmsubadp
, 0x04, 0x1E, PPC2_VSX
),
10923 GEN_XX3FORM(xvnmsubmdp
, 0x04, 0x1F, PPC2_VSX
),
10924 GEN_XX3FORM(xvmaxdp
, 0x00, 0x1C, PPC2_VSX
),
10925 GEN_XX3FORM(xvmindp
, 0x00, 0x1D, PPC2_VSX
),
10926 GEN_XX3_RC_FORM(xvcmpeqdp
, 0x0C, 0x0C, PPC2_VSX
),
10927 GEN_XX3_RC_FORM(xvcmpgtdp
, 0x0C, 0x0D, PPC2_VSX
),
10928 GEN_XX3_RC_FORM(xvcmpgedp
, 0x0C, 0x0E, PPC2_VSX
),
10929 GEN_XX2FORM(xvcvdpsp
, 0x12, 0x18, PPC2_VSX
),
10930 GEN_XX2FORM(xvcvdpsxds
, 0x10, 0x1D, PPC2_VSX
),
10931 GEN_XX2FORM(xvcvdpsxws
, 0x10, 0x0D, PPC2_VSX
),
10932 GEN_XX2FORM(xvcvdpuxds
, 0x10, 0x1C, PPC2_VSX
),
10933 GEN_XX2FORM(xvcvdpuxws
, 0x10, 0x0C, PPC2_VSX
),
10934 GEN_XX2FORM(xvcvsxddp
, 0x10, 0x1F, PPC2_VSX
),
10935 GEN_XX2FORM(xvcvuxddp
, 0x10, 0x1E, PPC2_VSX
),
10936 GEN_XX2FORM(xvcvsxwdp
, 0x10, 0x0F, PPC2_VSX
),
10937 GEN_XX2FORM(xvcvuxwdp
, 0x10, 0x0E, PPC2_VSX
),
10938 GEN_XX2FORM(xvrdpi
, 0x12, 0x0C, PPC2_VSX
),
10939 GEN_XX2FORM(xvrdpic
, 0x16, 0x0E, PPC2_VSX
),
10940 GEN_XX2FORM(xvrdpim
, 0x12, 0x0F, PPC2_VSX
),
10941 GEN_XX2FORM(xvrdpip
, 0x12, 0x0E, PPC2_VSX
),
10942 GEN_XX2FORM(xvrdpiz
, 0x12, 0x0D, PPC2_VSX
),
10944 GEN_XX3FORM(xvaddsp
, 0x00, 0x08, PPC2_VSX
),
10945 GEN_XX3FORM(xvsubsp
, 0x00, 0x09, PPC2_VSX
),
10946 GEN_XX3FORM(xvmulsp
, 0x00, 0x0A, PPC2_VSX
),
10947 GEN_XX3FORM(xvdivsp
, 0x00, 0x0B, PPC2_VSX
),
10948 GEN_XX2FORM(xvresp
, 0x14, 0x09, PPC2_VSX
),
10949 GEN_XX2FORM(xvsqrtsp
, 0x16, 0x08, PPC2_VSX
),
10950 GEN_XX2FORM(xvrsqrtesp
, 0x14, 0x08, PPC2_VSX
),
10951 GEN_XX3FORM(xvtdivsp
, 0x14, 0x0B, PPC2_VSX
),
10952 GEN_XX2FORM(xvtsqrtsp
, 0x14, 0x0A, PPC2_VSX
),
10953 GEN_XX3FORM(xvmaddasp
, 0x04, 0x08, PPC2_VSX
),
10954 GEN_XX3FORM(xvmaddmsp
, 0x04, 0x09, PPC2_VSX
),
10955 GEN_XX3FORM(xvmsubasp
, 0x04, 0x0A, PPC2_VSX
),
10956 GEN_XX3FORM(xvmsubmsp
, 0x04, 0x0B, PPC2_VSX
),
10957 GEN_XX3FORM(xvnmaddasp
, 0x04, 0x18, PPC2_VSX
),
10958 GEN_XX3FORM(xvnmaddmsp
, 0x04, 0x19, PPC2_VSX
),
10959 GEN_XX3FORM(xvnmsubasp
, 0x04, 0x1A, PPC2_VSX
),
10960 GEN_XX3FORM(xvnmsubmsp
, 0x04, 0x1B, PPC2_VSX
),
10961 GEN_XX3FORM(xvmaxsp
, 0x00, 0x18, PPC2_VSX
),
10962 GEN_XX3FORM(xvminsp
, 0x00, 0x19, PPC2_VSX
),
10963 GEN_XX3_RC_FORM(xvcmpeqsp
, 0x0C, 0x08, PPC2_VSX
),
10964 GEN_XX3_RC_FORM(xvcmpgtsp
, 0x0C, 0x09, PPC2_VSX
),
10965 GEN_XX3_RC_FORM(xvcmpgesp
, 0x0C, 0x0A, PPC2_VSX
),
10966 GEN_XX2FORM(xvcvspdp
, 0x12, 0x1C, PPC2_VSX
),
10967 GEN_XX2FORM(xvcvspsxds
, 0x10, 0x19, PPC2_VSX
),
10968 GEN_XX2FORM(xvcvspsxws
, 0x10, 0x09, PPC2_VSX
),
10969 GEN_XX2FORM(xvcvspuxds
, 0x10, 0x18, PPC2_VSX
),
10970 GEN_XX2FORM(xvcvspuxws
, 0x10, 0x08, PPC2_VSX
),
10971 GEN_XX2FORM(xvcvsxdsp
, 0x10, 0x1B, PPC2_VSX
),
10972 GEN_XX2FORM(xvcvuxdsp
, 0x10, 0x1A, PPC2_VSX
),
10973 GEN_XX2FORM(xvcvsxwsp
, 0x10, 0x0B, PPC2_VSX
),
10974 GEN_XX2FORM(xvcvuxwsp
, 0x10, 0x0A, PPC2_VSX
),
10975 GEN_XX2FORM(xvrspi
, 0x12, 0x08, PPC2_VSX
),
10976 GEN_XX2FORM(xvrspic
, 0x16, 0x0A, PPC2_VSX
),
10977 GEN_XX2FORM(xvrspim
, 0x12, 0x0B, PPC2_VSX
),
10978 GEN_XX2FORM(xvrspip
, 0x12, 0x0A, PPC2_VSX
),
10979 GEN_XX2FORM(xvrspiz
, 0x12, 0x09, PPC2_VSX
),
10982 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10983 GEN_XX3FORM(name, opc2, opc3, fl2)
10985 VSX_LOGICAL(xxland
, 0x8, 0x10, PPC2_VSX
),
10986 VSX_LOGICAL(xxlandc
, 0x8, 0x11, PPC2_VSX
),
10987 VSX_LOGICAL(xxlor
, 0x8, 0x12, PPC2_VSX
),
10988 VSX_LOGICAL(xxlxor
, 0x8, 0x13, PPC2_VSX
),
10989 VSX_LOGICAL(xxlnor
, 0x8, 0x14, PPC2_VSX
),
10990 VSX_LOGICAL(xxleqv
, 0x8, 0x17, PPC2_VSX207
),
10991 VSX_LOGICAL(xxlnand
, 0x8, 0x16, PPC2_VSX207
),
10992 VSX_LOGICAL(xxlorc
, 0x8, 0x15, PPC2_VSX207
),
10993 GEN_XX3FORM(xxmrghw
, 0x08, 0x02, PPC2_VSX
),
10994 GEN_XX3FORM(xxmrglw
, 0x08, 0x06, PPC2_VSX
),
10995 GEN_XX2FORM(xxspltw
, 0x08, 0x0A, PPC2_VSX
),
10996 GEN_XX3FORM_DM(xxsldwi
, 0x08, 0x00),
10998 #define GEN_XXSEL_ROW(opc3) \
10999 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
11000 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
11001 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11002 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11003 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11004 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11005 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11006 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11008 GEN_XXSEL_ROW(0x00)
11009 GEN_XXSEL_ROW(0x01)
11010 GEN_XXSEL_ROW(0x02)
11011 GEN_XXSEL_ROW(0x03)
11012 GEN_XXSEL_ROW(0x04)
11013 GEN_XXSEL_ROW(0x05)
11014 GEN_XXSEL_ROW(0x06)
11015 GEN_XXSEL_ROW(0x07)
11016 GEN_XXSEL_ROW(0x08)
11017 GEN_XXSEL_ROW(0x09)
11018 GEN_XXSEL_ROW(0x0A)
11019 GEN_XXSEL_ROW(0x0B)
11020 GEN_XXSEL_ROW(0x0C)
11021 GEN_XXSEL_ROW(0x0D)
11022 GEN_XXSEL_ROW(0x0E)
11023 GEN_XXSEL_ROW(0x0F)
11024 GEN_XXSEL_ROW(0x10)
11025 GEN_XXSEL_ROW(0x11)
11026 GEN_XXSEL_ROW(0x12)
11027 GEN_XXSEL_ROW(0x13)
11028 GEN_XXSEL_ROW(0x14)
11029 GEN_XXSEL_ROW(0x15)
11030 GEN_XXSEL_ROW(0x16)
11031 GEN_XXSEL_ROW(0x17)
11032 GEN_XXSEL_ROW(0x18)
11033 GEN_XXSEL_ROW(0x19)
11034 GEN_XXSEL_ROW(0x1A)
11035 GEN_XXSEL_ROW(0x1B)
11036 GEN_XXSEL_ROW(0x1C)
11037 GEN_XXSEL_ROW(0x1D)
11038 GEN_XXSEL_ROW(0x1E)
11039 GEN_XXSEL_ROW(0x1F)
11041 GEN_XX3FORM_DM(xxpermdi
, 0x08, 0x01),
11043 #undef GEN_DFP_T_A_B_Rc
11044 #undef GEN_DFP_BF_A_B
11045 #undef GEN_DFP_BF_A_DCM
11046 #undef GEN_DFP_T_B_U32_U32_Rc
11047 #undef GEN_DFP_T_A_B_I32_Rc
11048 #undef GEN_DFP_T_B_Rc
11049 #undef GEN_DFP_T_FPR_I32_Rc
11051 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11052 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11054 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11055 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11056 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11058 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11059 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11060 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11061 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11062 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11064 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11065 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11067 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11068 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11069 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11071 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11072 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11073 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11074 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11075 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11077 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11078 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11080 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11081 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11083 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11084 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11086 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11087 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11089 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11090 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11092 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11093 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11095 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11096 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11098 #define GEN_DFP_BF_A_B(name, op1, op2) \
11099 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11101 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11102 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11104 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11105 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11107 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11108 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11110 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11111 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11113 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11114 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11116 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11117 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11119 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11120 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11122 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11123 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11125 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11126 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11128 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11129 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11131 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11132 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11134 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11135 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11137 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11138 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11140 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11141 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11143 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11144 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11146 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11147 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11149 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11150 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11152 GEN_DFP_T_A_B_Rc(dadd
, 0x02, 0x00),
11153 GEN_DFP_Tp_Ap_Bp_Rc(daddq
, 0x02, 0x00),
11154 GEN_DFP_T_A_B_Rc(dsub
, 0x02, 0x10),
11155 GEN_DFP_Tp_Ap_Bp_Rc(dsubq
, 0x02, 0x10),
11156 GEN_DFP_T_A_B_Rc(dmul
, 0x02, 0x01),
11157 GEN_DFP_Tp_Ap_Bp_Rc(dmulq
, 0x02, 0x01),
11158 GEN_DFP_T_A_B_Rc(ddiv
, 0x02, 0x11),
11159 GEN_DFP_Tp_Ap_Bp_Rc(ddivq
, 0x02, 0x11),
11160 GEN_DFP_BF_A_B(dcmpu
, 0x02, 0x14),
11161 GEN_DFP_BF_Ap_Bp(dcmpuq
, 0x02, 0x14),
11162 GEN_DFP_BF_A_B(dcmpo
, 0x02, 0x04),
11163 GEN_DFP_BF_Ap_Bp(dcmpoq
, 0x02, 0x04),
11164 GEN_DFP_BF_A_DCM(dtstdc
, 0x02, 0x06),
11165 GEN_DFP_BF_Ap_DCM(dtstdcq
, 0x02, 0x06),
11166 GEN_DFP_BF_A_DCM(dtstdg
, 0x02, 0x07),
11167 GEN_DFP_BF_Ap_DCM(dtstdgq
, 0x02, 0x07),
11168 GEN_DFP_BF_A_B(dtstex
, 0x02, 0x05),
11169 GEN_DFP_BF_Ap_Bp(dtstexq
, 0x02, 0x05),
11170 GEN_DFP_BF_A_B(dtstsf
, 0x02, 0x15),
11171 GEN_DFP_BF_A_Bp(dtstsfq
, 0x02, 0x15),
11172 GEN_DFP_TE_T_B_RMC_Rc(dquai
, 0x03, 0x02),
11173 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq
, 0x03, 0x02),
11174 GEN_DFP_T_A_B_RMC_Rc(dqua
, 0x03, 0x00),
11175 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq
, 0x03, 0x00),
11176 GEN_DFP_T_A_B_RMC_Rc(drrnd
, 0x03, 0x01),
11177 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq
, 0x03, 0x01),
11178 GEN_DFP_R_T_B_RMC_Rc(drintx
, 0x03, 0x03),
11179 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq
, 0x03, 0x03),
11180 GEN_DFP_R_T_B_RMC_Rc(drintn
, 0x03, 0x07),
11181 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq
, 0x03, 0x07),
11182 GEN_DFP_T_B_Rc(dctdp
, 0x02, 0x08),
11183 GEN_DFP_Tp_B_Rc(dctqpq
, 0x02, 0x08),
11184 GEN_DFP_T_B_Rc(drsp
, 0x02, 0x18),
11185 GEN_DFP_Tp_Bp_Rc(drdpq
, 0x02, 0x18),
11186 GEN_DFP_T_B_Rc(dcffix
, 0x02, 0x19),
11187 GEN_DFP_Tp_B_Rc(dcffixq
, 0x02, 0x19),
11188 GEN_DFP_T_B_Rc(dctfix
, 0x02, 0x09),
11189 GEN_DFP_T_Bp_Rc(dctfixq
, 0x02, 0x09),
11190 GEN_DFP_SP_T_B_Rc(ddedpd
, 0x02, 0x0a),
11191 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq
, 0x02, 0x0a),
11192 GEN_DFP_S_T_B_Rc(denbcd
, 0x02, 0x1a),
11193 GEN_DFP_S_Tp_Bp_Rc(denbcdq
, 0x02, 0x1a),
11194 GEN_DFP_T_B_Rc(dxex
, 0x02, 0x0b),
11195 GEN_DFP_T_Bp_Rc(dxexq
, 0x02, 0x0b),
11196 GEN_DFP_T_A_B_Rc(diex
, 0x02, 0x1b),
11197 GEN_DFP_Tp_A_Bp_Rc(diexq
, 0x02, 0x1b),
11198 GEN_DFP_T_A_SH_Rc(dscli
, 0x02, 0x02),
11199 GEN_DFP_Tp_Ap_SH_Rc(dscliq
, 0x02, 0x02),
11200 GEN_DFP_T_A_SH_Rc(dscri
, 0x02, 0x03),
11201 GEN_DFP_Tp_Ap_SH_Rc(dscriq
, 0x02, 0x03),
11204 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11205 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11206 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11207 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11208 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11209 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11210 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11211 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11212 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11213 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
11214 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
11215 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11216 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11217 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11218 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11219 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11220 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11221 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
11222 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11223 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11224 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11225 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11226 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11227 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11228 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11229 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11230 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11231 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11232 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11233 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11234 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
11236 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11237 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11238 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11239 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11240 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11241 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11242 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11243 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11244 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11245 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11246 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11247 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11248 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11249 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11251 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11252 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11253 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11254 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11255 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11256 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
11257 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11258 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11259 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11260 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11261 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11262 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11263 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11264 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11266 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11267 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11268 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
11269 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11270 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11271 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11272 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11273 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
11274 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11275 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11276 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11277 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11278 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11279 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11280 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11281 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11283 #undef GEN_SPEOP_LDST
11284 #define GEN_SPEOP_LDST(name, opc2, sh) \
11285 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11286 GEN_SPEOP_LDST(evldd
, 0x00, 3),
11287 GEN_SPEOP_LDST(evldw
, 0x01, 3),
11288 GEN_SPEOP_LDST(evldh
, 0x02, 3),
11289 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
11290 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
11291 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
11292 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
11293 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
11294 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
11295 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
11296 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
11298 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
11299 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
11300 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
11301 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
11302 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
11303 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
11304 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
11306 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11307 PPC_NONE
, PPC2_TM
),
11308 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11309 PPC_NONE
, PPC2_TM
),
11310 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11311 PPC_NONE
, PPC2_TM
),
11312 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11313 PPC_NONE
, PPC2_TM
),
11314 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11315 PPC_NONE
, PPC2_TM
),
11316 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11317 PPC_NONE
, PPC2_TM
),
11318 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11319 PPC_NONE
, PPC2_TM
),
11320 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11321 PPC_NONE
, PPC2_TM
),
11322 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11323 PPC_NONE
, PPC2_TM
),
11324 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11325 PPC_NONE
, PPC2_TM
),
11326 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11327 PPC_NONE
, PPC2_TM
),
11330 #include "helper_regs.h"
11331 #include "translate_init.c"
11333 /*****************************************************************************/
11334 /* Misc PowerPC helpers */
11335 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
11341 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11342 CPUPPCState
*env
= &cpu
->env
;
11345 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
11346 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
11347 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
11349 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
11350 TARGET_FMT_lx
" iidx %d didx %d\n",
11351 env
->msr
, env
->spr
[SPR_HID0
],
11352 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
11353 #if !defined(NO_TIMER_DUMP)
11354 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
11355 #if !defined(CONFIG_USER_ONLY)
11359 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
11360 #if !defined(CONFIG_USER_ONLY)
11361 , cpu_ppc_load_decr(env
)
11365 for (i
= 0; i
< 32; i
++) {
11366 if ((i
& (RGPL
- 1)) == 0)
11367 cpu_fprintf(f
, "GPR%02d", i
);
11368 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
11369 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
11370 cpu_fprintf(f
, "\n");
11372 cpu_fprintf(f
, "CR ");
11373 for (i
= 0; i
< 8; i
++)
11374 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
11375 cpu_fprintf(f
, " [");
11376 for (i
= 0; i
< 8; i
++) {
11378 if (env
->crf
[i
] & 0x08)
11380 else if (env
->crf
[i
] & 0x04)
11382 else if (env
->crf
[i
] & 0x02)
11384 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
11386 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
11387 env
->reserve_addr
);
11388 for (i
= 0; i
< 32; i
++) {
11389 if ((i
& (RFPL
- 1)) == 0)
11390 cpu_fprintf(f
, "FPR%02d", i
);
11391 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
11392 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
11393 cpu_fprintf(f
, "\n");
11395 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
11396 #if !defined(CONFIG_USER_ONLY)
11397 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
11398 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
11399 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
11400 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
11402 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
11403 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
11404 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
11405 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
11407 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
11408 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
11409 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
11410 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
11412 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
11413 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
11414 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
11415 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
11416 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
11418 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
11419 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
11420 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
11421 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
11423 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
11424 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
11425 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
11426 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
11428 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
11429 " EPR " TARGET_FMT_lx
"\n",
11430 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
11431 env
->spr
[SPR_BOOKE_EPR
]);
11434 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
11435 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
11436 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
11437 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
11440 * IVORs are left out as they are large and do not change often --
11441 * they can be read with "p $ivor0", "p $ivor1", etc.
11445 #if defined(TARGET_PPC64)
11446 if (env
->flags
& POWERPC_FLAG_CFAR
) {
11447 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
11451 switch (env
->mmu_model
) {
11452 case POWERPC_MMU_32B
:
11453 case POWERPC_MMU_601
:
11454 case POWERPC_MMU_SOFT_6xx
:
11455 case POWERPC_MMU_SOFT_74xx
:
11456 #if defined(TARGET_PPC64)
11457 case POWERPC_MMU_64B
:
11458 case POWERPC_MMU_2_03
:
11459 case POWERPC_MMU_2_06
:
11460 case POWERPC_MMU_2_06a
:
11461 case POWERPC_MMU_2_07
:
11462 case POWERPC_MMU_2_07a
:
11464 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" DAR " TARGET_FMT_lx
11465 " DSISR " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
],
11466 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
11468 case POWERPC_MMU_BOOKE206
:
11469 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
11470 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
11471 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
11472 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
11474 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
11475 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
11476 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
11477 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
11479 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
11480 " TLB1CFG " TARGET_FMT_lx
"\n",
11481 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
11482 env
->spr
[SPR_BOOKE_TLB1CFG
]);
11493 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
11494 fprintf_function cpu_fprintf
, int flags
)
11496 #if defined(DO_PPC_STATISTICS)
11497 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11498 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
11501 t1
= cpu
->env
.opcodes
;
11502 for (op1
= 0; op1
< 64; op1
++) {
11504 if (is_indirect_opcode(handler
)) {
11505 t2
= ind_table(handler
);
11506 for (op2
= 0; op2
< 32; op2
++) {
11508 if (is_indirect_opcode(handler
)) {
11509 t3
= ind_table(handler
);
11510 for (op3
= 0; op3
< 32; op3
++) {
11512 if (handler
->count
== 0)
11514 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
11515 "%016" PRIx64
" %" PRId64
"\n",
11516 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
11518 handler
->count
, handler
->count
);
11521 if (handler
->count
== 0)
11523 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
11524 "%016" PRIx64
" %" PRId64
"\n",
11525 op1
, op2
, op1
, op2
, handler
->oname
,
11526 handler
->count
, handler
->count
);
11530 if (handler
->count
== 0)
11532 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
11534 op1
, op1
, handler
->oname
,
11535 handler
->count
, handler
->count
);
11541 /*****************************************************************************/
11542 void gen_intermediate_code(CPUPPCState
*env
, struct TranslationBlock
*tb
)
11544 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
11545 CPUState
*cs
= CPU(cpu
);
11546 DisasContext ctx
, *ctxp
= &ctx
;
11547 opc_handler_t
**table
, *handler
;
11548 target_ulong pc_start
;
11553 ctx
.nip
= pc_start
;
11555 ctx
.exception
= POWERPC_EXCP_NONE
;
11556 ctx
.spr_cb
= env
->spr_cb
;
11558 ctx
.mem_idx
= env
->dmmu_idx
;
11559 #if !defined(CONFIG_USER_ONLY)
11560 ctx
.hv
= msr_hv
|| !env
->has_hv_mode
;
11562 ctx
.insns_flags
= env
->insns_flags
;
11563 ctx
.insns_flags2
= env
->insns_flags2
;
11564 ctx
.access_type
= -1;
11565 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
11566 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
11567 #if defined(TARGET_PPC64)
11568 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
11569 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
11571 if (env
->mmu_model
== POWERPC_MMU_32B
||
11572 env
->mmu_model
== POWERPC_MMU_601
||
11573 (env
->mmu_model
& POWERPC_MMU_64B
))
11574 ctx
.lazy_tlb_flush
= true;
11576 ctx
.fpu_enabled
= msr_fp
;
11577 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
11578 ctx
.spe_enabled
= msr_spe
;
11580 ctx
.spe_enabled
= 0;
11581 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
11582 ctx
.altivec_enabled
= msr_vr
;
11584 ctx
.altivec_enabled
= 0;
11585 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
11586 ctx
.vsx_enabled
= msr_vsx
;
11588 ctx
.vsx_enabled
= 0;
11590 #if defined(TARGET_PPC64)
11591 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
11592 ctx
.tm_enabled
= msr_tm
;
11594 ctx
.tm_enabled
= 0;
11597 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
11598 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
11600 ctx
.singlestep_enabled
= 0;
11601 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
11602 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
11603 if (unlikely(cs
->singlestep_enabled
)) {
11604 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
11606 #if defined (DO_SINGLE_STEP) && 0
11607 /* Single step trace mode */
11611 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11612 if (max_insns
== 0) {
11613 max_insns
= CF_COUNT_MASK
;
11615 if (max_insns
> TCG_MAX_INSNS
) {
11616 max_insns
= TCG_MAX_INSNS
;
11620 tcg_clear_temp_count();
11621 /* Set env in case of segfault during code fetch */
11622 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
11623 tcg_gen_insn_start(ctx
.nip
);
11626 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
11627 gen_debug_exception(ctxp
);
11628 /* The address covered by the breakpoint must be included in
11629 [tb->pc, tb->pc + tb->size) in order to for it to be
11630 properly cleared -- thus we increment the PC here so that
11631 the logic setting tb->size below does the right thing. */
11636 LOG_DISAS("----------------\n");
11637 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
11638 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
11639 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
))
11641 if (unlikely(need_byteswap(&ctx
))) {
11642 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
11644 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
11646 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11647 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11648 opc3(ctx
.opcode
), ctx
.le_mode
? "little" : "big");
11650 table
= env
->opcodes
;
11651 handler
= table
[opc1(ctx
.opcode
)];
11652 if (is_indirect_opcode(handler
)) {
11653 table
= ind_table(handler
);
11654 handler
= table
[opc2(ctx
.opcode
)];
11655 if (is_indirect_opcode(handler
)) {
11656 table
= ind_table(handler
);
11657 handler
= table
[opc3(ctx
.opcode
)];
11660 /* Is opcode *REALLY* valid ? */
11661 if (unlikely(handler
->handler
== &gen_invalid
)) {
11662 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
11663 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
11664 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11665 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
11669 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
11670 inval
= handler
->inval2
;
11672 inval
= handler
->inval1
;
11675 if (unlikely((ctx
.opcode
& inval
) != 0)) {
11676 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
11677 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
11678 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
11679 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11680 ctx
.opcode
, ctx
.nip
- 4);
11681 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
11685 (*(handler
->handler
))(&ctx
);
11686 #if defined(DO_PPC_STATISTICS)
11689 /* Check trace mode exceptions */
11690 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
11691 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
11692 ctx
.exception
!= POWERPC_SYSCALL
&&
11693 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
11694 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
11695 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
11696 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
11697 (cs
->singlestep_enabled
) ||
11699 num_insns
>= max_insns
)) {
11700 /* if we reach a page boundary or are single stepping, stop
11705 if (tcg_check_temp_count()) {
11706 fprintf(stderr
, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11707 opc1(ctx
.opcode
), opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11712 if (tb
->cflags
& CF_LAST_IO
)
11714 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
11715 gen_goto_tb(&ctx
, 0, ctx
.nip
);
11716 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
11717 if (unlikely(cs
->singlestep_enabled
)) {
11718 gen_debug_exception(ctxp
);
11720 /* Generate the return instruction */
11721 tcg_gen_exit_tb(0);
11723 gen_tb_end(tb
, num_insns
);
11725 tb
->size
= ctx
.nip
- pc_start
;
11726 tb
->icount
= num_insns
;
11728 #if defined(DEBUG_DISAS)
11729 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
11730 && qemu_log_in_addr_range(pc_start
)) {
11732 flags
= env
->bfd_mach
;
11733 flags
|= ctx
.le_mode
<< 16;
11734 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11735 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, flags
);
11741 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,
11742 target_ulong
*data
)
11744 env
->nip
= data
[0];