target/riscv: Check SUM in the correct register
[qemu/kevin.git] / tcg / sparc64 / tcg-target-con-set.h
blob31e6fea1fc4670eaa120c2125a6c555db5fedd74
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define Sparc target-specific constraint sets.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
9 * Each operand should be a sequence of constraint letters as defined by
10 * tcg-target-con-str.h; the constraint combination is inclusive or.
12 C_O0_I1(r)
13 C_O0_I2(rZ, r)
14 C_O0_I2(rZ, rJ)
15 C_O0_I2(sZ, s)
16 C_O1_I1(r, s)
17 C_O1_I1(r, r)
18 C_O1_I2(r, r, r)
19 C_O1_I2(r, rZ, rJ)
20 C_O1_I4(r, rZ, rJ, rI, 0)
21 C_O2_I2(r, r, rZ, rJ)
22 C_O2_I4(r, r, rZ, rZ, rJ, rJ)