target/riscv: Check SUM in the correct register
[qemu/kevin.git] / tcg / 
treed1fa5962a22e84c3c2cb3d88f894d9bfca4615cc
drwxr-xr-x   ..
drwxr-xr-x - aarch64
drwxr-xr-x - arm
drwxr-xr-x - i386
drwxr-xr-x - loongarch64
-rw-r--r-- 448 meson.build
drwxr-xr-x - mips
-rw-r--r-- 58737 optimize.c
drwxr-xr-x - ppc
-rw-r--r-- 26471 region.c
drwxr-xr-x - riscv
drwxr-xr-x - s390x
drwxr-xr-x - sparc64
-rw-r--r-- 1443 tcg-common.c
-rw-r--r-- 4584 tcg-internal.h
-rw-r--r-- 3041 tcg-ldst.c.inc
-rw-r--r-- 123098 tcg-op-gvec.c
-rw-r--r-- 23766 tcg-op-vec.c
-rw-r--r-- 115627 tcg-op.c
-rw-r--r-- 5387 tcg-pool.c.inc
-rw-r--r-- 183978 tcg.c
-rw-r--r-- 43086 tci.c
drwxr-xr-x - tci