4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 * Copyright (c) 2021-2023 PLCT Lab
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef RISCV_CPU_CFG_H
22 #define RISCV_CPU_CFG_H
25 * map is a 16-bit bitmap: the most significant set bit in map is the maximum
26 * satp mode that is supported. It may be chosen by the user and must respect
27 * what qemu implements (valid_1_10_32/64) and what the hw is capable of
28 * (supported bitmap below).
30 * init is a 16-bit bitmap used to make sure the user selected a correct
31 * configuration as per the specification.
33 * supported is a 16-bit bitmap used to reflect the hw capabilities.
36 uint16_t map
, init
, supported
;
39 struct RISCVCPUConfig
{
133 * Always 'true' booleans for named features
134 * TCG always implement/can't be user disabled,
135 * based on spec version.
140 /* Vendor-specific custom extensions */
145 bool ext_xtheadcondmov
;
146 bool ext_xtheadfmemidx
;
149 bool ext_xtheadmemidx
;
150 bool ext_xtheadmempair
;
152 bool ext_XVentanaCondOps
;
157 uint16_t cbom_blocksize
;
158 uint16_t cbop_blocksize
;
159 uint16_t cboz_blocksize
;
165 bool short_isa_string
;
167 #ifndef CONFIG_USER_ONLY
168 RISCVSATPMap satp_mode
;
172 typedef struct RISCVCPUConfig RISCVCPUConfig
;
174 /* Helper functions to test for extensions. */
176 static inline bool always_true_p(const RISCVCPUConfig
*cfg
__attribute__((__unused__
)))
181 static inline bool has_xthead_p(const RISCVCPUConfig
*cfg
)
183 return cfg
->ext_xtheadba
|| cfg
->ext_xtheadbb
||
184 cfg
->ext_xtheadbs
|| cfg
->ext_xtheadcmo
||
185 cfg
->ext_xtheadcondmov
||
186 cfg
->ext_xtheadfmemidx
|| cfg
->ext_xtheadfmv
||
187 cfg
->ext_xtheadmac
|| cfg
->ext_xtheadmemidx
||
188 cfg
->ext_xtheadmempair
|| cfg
->ext_xtheadsync
;
191 #define MATERIALISE_EXT_PREDICATE(ext) \
192 static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \
194 return cfg->ext_ ## ext ; \
197 MATERIALISE_EXT_PREDICATE(xtheadba
)
198 MATERIALISE_EXT_PREDICATE(xtheadbb
)
199 MATERIALISE_EXT_PREDICATE(xtheadbs
)
200 MATERIALISE_EXT_PREDICATE(xtheadcmo
)
201 MATERIALISE_EXT_PREDICATE(xtheadcondmov
)
202 MATERIALISE_EXT_PREDICATE(xtheadfmemidx
)
203 MATERIALISE_EXT_PREDICATE(xtheadfmv
)
204 MATERIALISE_EXT_PREDICATE(xtheadmac
)
205 MATERIALISE_EXT_PREDICATE(xtheadmemidx
)
206 MATERIALISE_EXT_PREDICATE(xtheadmempair
)
207 MATERIALISE_EXT_PREDICATE(xtheadsync
)
208 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
)