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block: m25p80: Extend address mode
[qemu/kevin.git] / hw / block / m25p80.c
blob03f59ae528efaf9058cdf45ba82cb01ab0838704
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29
30 #ifndef M25P80_ERR_DEBUG
31 #define M25P80_ERR_DEBUG 0
32 #endif
33
34 #define DB_PRINT_L(level, ...) do { \
35 if (M25P80_ERR_DEBUG > (level)) { \
36 fprintf(stderr, ": %s: ", __func__); \
37 fprintf(stderr, ## __VA_ARGS__); \
38 } \
39 } while (0);
40
41 /* Fields for FlashPartInfo->flags */
42
43 /* erase capabilities */
44 #define ER_4K 1
45 #define ER_32K 2
46 /* set to allow the page program command to write 0s back to 1. Useful for
47 * modelling EEPROM with SPI flash command set
48 */
49 #define WR_1 0x100
50
51 /* 16 MiB max in 3 byte address mode */
52 #define MAX_3BYTES_SIZE 0x1000000
53
54 typedef struct FlashPartInfo {
55 const char *part_name;
56 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
57 uint32_t jedec;
58 /* extended jedec code */
59 uint16_t ext_jedec;
60 /* there is confusion between manufacturers as to what a sector is. In this
61 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
62 * command (opcode 0xd8).
63 */
64 uint32_t sector_size;
65 uint32_t n_sectors;
66 uint32_t page_size;
67 uint16_t flags;
68 } FlashPartInfo;
69
70 /* adapted from linux */
71
72 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
73 .part_name = (_part_name),\
74 .jedec = (_jedec),\
75 .ext_jedec = (_ext_jedec),\
76 .sector_size = (_sector_size),\
77 .n_sectors = (_n_sectors),\
78 .page_size = 256,\
79 .flags = (_flags),\
80
81 #define JEDEC_NUMONYX 0x20
82 #define JEDEC_WINBOND 0xEF
83 #define JEDEC_SPANSION 0x01
84
85 static const FlashPartInfo known_devices[] = {
86 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
87 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
88 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
89
90 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
91 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
92 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
93
94 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
95 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
96 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
97 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
98
99 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
100
101 /* EON -- en25xxx */
102 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
103 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
104 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
105 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
106 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
107
108 /* GigaDevice */
109 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
110 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
111
112 /* Intel/Numonyx -- xxxs33b */
113 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
114 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
115 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
116 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
117
118 /* Macronix */
119 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
120 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
121 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
122 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
123 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
124 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
125 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
126 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
127 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
128 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
129
130 /* Micron */
131 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
132 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
133 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
134 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
135 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
136 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
137 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
138 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
139
140 /* Spansion -- single (large) sector size only, at least
141 * for the chips listed here (without boot sectors).
142 */
143 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
144 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
145 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
146 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
147 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
148 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
149 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
150 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
151 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
152 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
153 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
154 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
155 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
156 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
157 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
158 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
159 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
160
161 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
162 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
163 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
164 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
165 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
166 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
167 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
168 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
169 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
170 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
171
172 /* ST Microelectronics -- newer production may have feature updates */
173 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
174 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
175 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
176 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
177 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
178 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
179 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
180 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
181 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
182 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
183
184 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
185 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
186 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
187
188 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
189 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
190 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
191
192 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
193 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
194 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
195 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
196
197 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
198 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
199 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
200 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
201 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
202 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
203 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
204 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
205 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
206 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
207 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
208 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
209 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
210 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
211
212 /* Numonyx -- n25q128 */
213 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
214 };
215
216 typedef enum {
217 NOP = 0,
218 WRSR = 0x1,
219 WRDI = 0x4,
220 RDSR = 0x5,
221 WREN = 0x6,
222 JEDEC_READ = 0x9f,
223 BULK_ERASE = 0xc7,
224
225 READ = 0x3,
226 FAST_READ = 0xb,
227 DOR = 0x3b,
228 QOR = 0x6b,
229 DIOR = 0xbb,
230 QIOR = 0xeb,
231
232 PP = 0x2,
233 DPP = 0xa2,
234 QPP = 0x32,
235
236 ERASE_4K = 0x20,
237 ERASE_32K = 0x52,
238 ERASE_SECTOR = 0xd8,
239
240 EXTEND_ADDR_READ = 0xC8,
241 EXTEND_ADDR_WRITE = 0xC5,
242
243 RESET_ENABLE = 0x66,
244 RESET_MEMORY = 0x99,
245 } FlashCMD;
246
247 typedef enum {
248 STATE_IDLE,
249 STATE_PAGE_PROGRAM,
250 STATE_READ,
251 STATE_COLLECTING_DATA,
252 STATE_READING_DATA,
253 } CMDState;
254
255 typedef struct Flash {
256 SSISlave parent_obj;
257
258 BlockBackend *blk;
259
260 uint8_t *storage;
261 uint32_t size;
262 int page_size;
263
264 uint8_t state;
265 uint8_t data[16];
266 uint32_t len;
267 uint32_t pos;
268 uint8_t needed_bytes;
269 uint8_t cmd_in_progress;
270 uint64_t cur_addr;
271 bool write_enable;
272 bool reset_enable;
273 uint8_t ear;
274
275 int64_t dirty_page;
276
277 const FlashPartInfo *pi;
278
279 } Flash;
280
281 typedef struct M25P80Class {
282 SSISlaveClass parent_class;
283 FlashPartInfo *pi;
284 } M25P80Class;
285
286 #define TYPE_M25P80 "m25p80-generic"
287 #define M25P80(obj) \
288 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
289 #define M25P80_CLASS(klass) \
290 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
291 #define M25P80_GET_CLASS(obj) \
292 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
293
294 static void blk_sync_complete(void *opaque, int ret)
295 {
296 /* do nothing. Masters do not directly interact with the backing store,
297 * only the working copy so no mutexing required.
298 */
299 }
300
301 static void flash_sync_page(Flash *s, int page)
302 {
303 int blk_sector, nb_sectors;
304 QEMUIOVector iov;
305
306 if (!s->blk || blk_is_read_only(s->blk)) {
307 return;
308 }
309
310 blk_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
311 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
312 qemu_iovec_init(&iov, 1);
313 qemu_iovec_add(&iov, s->storage + blk_sector * BDRV_SECTOR_SIZE,
314 nb_sectors * BDRV_SECTOR_SIZE);
315 blk_aio_writev(s->blk, blk_sector, &iov, nb_sectors, blk_sync_complete,
316 NULL);
317 }
318
319 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
320 {
321 int64_t start, end, nb_sectors;
322 QEMUIOVector iov;
323
324 if (!s->blk || blk_is_read_only(s->blk)) {
325 return;
326 }
327
328 assert(!(len % BDRV_SECTOR_SIZE));
329 start = off / BDRV_SECTOR_SIZE;
330 end = (off + len) / BDRV_SECTOR_SIZE;
331 nb_sectors = end - start;
332 qemu_iovec_init(&iov, 1);
333 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
334 nb_sectors * BDRV_SECTOR_SIZE);
335 blk_aio_writev(s->blk, start, &iov, nb_sectors, blk_sync_complete, NULL);
336 }
337
338 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
339 {
340 uint32_t len;
341 uint8_t capa_to_assert = 0;
342
343 switch (cmd) {
344 case ERASE_4K:
345 len = 4 << 10;
346 capa_to_assert = ER_4K;
347 break;
348 case ERASE_32K:
349 len = 32 << 10;
350 capa_to_assert = ER_32K;
351 break;
352 case ERASE_SECTOR:
353 len = s->pi->sector_size;
354 break;
355 case BULK_ERASE:
356 len = s->size;
357 break;
358 default:
359 abort();
360 }
361
362 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
363 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
364 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
365 " device\n", len);
366 }
367
368 if (!s->write_enable) {
369 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
370 return;
371 }
372 memset(s->storage + offset, 0xff, len);
373 flash_sync_area(s, offset, len);
374 }
375
376 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
377 {
378 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
379 flash_sync_page(s, s->dirty_page);
380 s->dirty_page = newpage;
381 }
382 }
383
384 static inline
385 void flash_write8(Flash *s, uint64_t addr, uint8_t data)
386 {
387 int64_t page = addr / s->pi->page_size;
388 uint8_t prev = s->storage[s->cur_addr];
389
390 if (!s->write_enable) {
391 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
392 }
393
394 if ((prev ^ data) & data) {
395 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
396 " -> %" PRIx8 "\n", addr, prev, data);
397 }
398
399 if (s->pi->flags & WR_1) {
400 s->storage[s->cur_addr] = data;
401 } else {
402 s->storage[s->cur_addr] &= data;
403 }
404
405 flash_sync_dirty(s, page);
406 s->dirty_page = page;
407 }
408
409 static void complete_collecting_data(Flash *s)
410 {
411 s->cur_addr = s->data[0] << 16;
412 s->cur_addr |= s->data[1] << 8;
413 s->cur_addr |= s->data[2];
414 s->cur_addr += (s->ear & 0x3) * MAX_3BYTES_SIZE;
415
416 s->state = STATE_IDLE;
417
418 switch (s->cmd_in_progress) {
419 case DPP:
420 case QPP:
421 case PP:
422 s->state = STATE_PAGE_PROGRAM;
423 break;
424 case READ:
425 case FAST_READ:
426 case DOR:
427 case QOR:
428 case DIOR:
429 case QIOR:
430 s->state = STATE_READ;
431 break;
432 case ERASE_4K:
433 case ERASE_32K:
434 case ERASE_SECTOR:
435 flash_erase(s, s->cur_addr, s->cmd_in_progress);
436 break;
437 case WRSR:
438 if (s->write_enable) {
439 s->write_enable = false;
440 }
441 break;
442 case EXTEND_ADDR_WRITE:
443 s->ear = s->data[0];
444 break;
445 default:
446 break;
447 }
448 }
449
450 static void reset_memory(Flash *s)
451 {
452 s->cmd_in_progress = NOP;
453 s->cur_addr = 0;
454 s->ear = 0;
455 s->len = 0;
456 s->needed_bytes = 0;
457 s->pos = 0;
458 s->state = STATE_IDLE;
459 s->write_enable = false;
460 s->reset_enable = false;
461
462 DB_PRINT_L(0, "Reset done.\n");
463 }
464
465 static void decode_new_cmd(Flash *s, uint32_t value)
466 {
467 s->cmd_in_progress = value;
468 DB_PRINT_L(0, "decoded new command:%x\n", value);
469
470 if (value != RESET_MEMORY) {
471 s->reset_enable = false;
472 }
473
474 switch (value) {
475
476 case ERASE_4K:
477 case ERASE_32K:
478 case ERASE_SECTOR:
479 case READ:
480 case DPP:
481 case QPP:
482 case PP:
483 s->needed_bytes = 3;
484 s->pos = 0;
485 s->len = 0;
486 s->state = STATE_COLLECTING_DATA;
487 break;
488
489 case FAST_READ:
490 case DOR:
491 case QOR:
492 s->needed_bytes = 4;
493 s->pos = 0;
494 s->len = 0;
495 s->state = STATE_COLLECTING_DATA;
496 break;
497
498 case DIOR:
499 switch ((s->pi->jedec >> 16) & 0xFF) {
500 case JEDEC_WINBOND:
501 case JEDEC_SPANSION:
502 s->needed_bytes = 4;
503 break;
504 case JEDEC_NUMONYX:
505 default:
506 s->needed_bytes = 5;
507 }
508 s->pos = 0;
509 s->len = 0;
510 s->state = STATE_COLLECTING_DATA;
511 break;
512
513 case QIOR:
514 switch ((s->pi->jedec >> 16) & 0xFF) {
515 case JEDEC_WINBOND:
516 case JEDEC_SPANSION:
517 s->needed_bytes = 6;
518 break;
519 case JEDEC_NUMONYX:
520 default:
521 s->needed_bytes = 8;
522 }
523 s->pos = 0;
524 s->len = 0;
525 s->state = STATE_COLLECTING_DATA;
526 break;
527
528 case WRSR:
529 if (s->write_enable) {
530 s->needed_bytes = 1;
531 s->pos = 0;
532 s->len = 0;
533 s->state = STATE_COLLECTING_DATA;
534 }
535 break;
536
537 case WRDI:
538 s->write_enable = false;
539 break;
540 case WREN:
541 s->write_enable = true;
542 break;
543
544 case RDSR:
545 s->data[0] = (!!s->write_enable) << 1;
546 s->pos = 0;
547 s->len = 1;
548 s->state = STATE_READING_DATA;
549 break;
550
551 case JEDEC_READ:
552 DB_PRINT_L(0, "populated jedec code\n");
553 s->data[0] = (s->pi->jedec >> 16) & 0xff;
554 s->data[1] = (s->pi->jedec >> 8) & 0xff;
555 s->data[2] = s->pi->jedec & 0xff;
556 if (s->pi->ext_jedec) {
557 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
558 s->data[4] = s->pi->ext_jedec & 0xff;
559 s->len = 5;
560 } else {
561 s->len = 3;
562 }
563 s->pos = 0;
564 s->state = STATE_READING_DATA;
565 break;
566
567 case BULK_ERASE:
568 if (s->write_enable) {
569 DB_PRINT_L(0, "chip erase\n");
570 flash_erase(s, 0, BULK_ERASE);
571 } else {
572 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
573 "protect!\n");
574 }
575 break;
576 case NOP:
577 break;
578 case EXTEND_ADDR_READ:
579 s->data[0] = s->ear;
580 s->pos = 0;
581 s->len = 1;
582 s->state = STATE_READING_DATA;
583 break;
584 case EXTEND_ADDR_WRITE:
585 if (s->write_enable) {
586 s->needed_bytes = 1;
587 s->pos = 0;
588 s->len = 0;
589 s->state = STATE_COLLECTING_DATA;
590 }
591 break;
592 case RESET_ENABLE:
593 s->reset_enable = true;
594 break;
595 case RESET_MEMORY:
596 if (s->reset_enable) {
597 reset_memory(s);
598 }
599 break;
600 default:
601 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
602 break;
603 }
604 }
605
606 static int m25p80_cs(SSISlave *ss, bool select)
607 {
608 Flash *s = M25P80(ss);
609
610 if (select) {
611 s->len = 0;
612 s->pos = 0;
613 s->state = STATE_IDLE;
614 flash_sync_dirty(s, -1);
615 }
616
617 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
618
619 return 0;
620 }
621
622 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
623 {
624 Flash *s = M25P80(ss);
625 uint32_t r = 0;
626
627 switch (s->state) {
628
629 case STATE_PAGE_PROGRAM:
630 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
631 s->cur_addr, (uint8_t)tx);
632 flash_write8(s, s->cur_addr, (uint8_t)tx);
633 s->cur_addr++;
634 break;
635
636 case STATE_READ:
637 r = s->storage[s->cur_addr];
638 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
639 (uint8_t)r);
640 s->cur_addr = (s->cur_addr + 1) % s->size;
641 break;
642
643 case STATE_COLLECTING_DATA:
644 s->data[s->len] = (uint8_t)tx;
645 s->len++;
646
647 if (s->len == s->needed_bytes) {
648 complete_collecting_data(s);
649 }
650 break;
651
652 case STATE_READING_DATA:
653 r = s->data[s->pos];
654 s->pos++;
655 if (s->pos == s->len) {
656 s->pos = 0;
657 s->state = STATE_IDLE;
658 }
659 break;
660
661 default:
662 case STATE_IDLE:
663 decode_new_cmd(s, (uint8_t)tx);
664 break;
665 }
666
667 return r;
668 }
669
670 static int m25p80_init(SSISlave *ss)
671 {
672 DriveInfo *dinfo;
673 Flash *s = M25P80(ss);
674 M25P80Class *mc = M25P80_GET_CLASS(s);
675
676 s->pi = mc->pi;
677
678 s->size = s->pi->sector_size * s->pi->n_sectors;
679 s->dirty_page = -1;
680
681 /* FIXME use a qdev drive property instead of drive_get_next() */
682 dinfo = drive_get_next(IF_MTD);
683
684 if (dinfo) {
685 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
686 s->blk = blk_by_legacy_dinfo(dinfo);
687 blk_attach_dev_nofail(s->blk, s);
688
689 s->storage = blk_blockalign(s->blk, s->size);
690
691 /* FIXME: Move to late init */
692 if (blk_read(s->blk, 0, s->storage,
693 DIV_ROUND_UP(s->size, BDRV_SECTOR_SIZE))) {
694 fprintf(stderr, "Failed to initialize SPI flash!\n");
695 return 1;
696 }
697 } else {
698 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
699 s->storage = blk_blockalign(NULL, s->size);
700 memset(s->storage, 0xFF, s->size);
701 }
702
703 return 0;
704 }
705
706 static void m25p80_reset(DeviceState *d)
707 {
708 Flash *s = M25P80(d);
709
710 reset_memory(s);
711 }
712
713 static void m25p80_pre_save(void *opaque)
714 {
715 flash_sync_dirty((Flash *)opaque, -1);
716 }
717
718 static const VMStateDescription vmstate_m25p80 = {
719 .name = "xilinx_spi",
720 .version_id = 2,
721 .minimum_version_id = 1,
722 .pre_save = m25p80_pre_save,
723 .fields = (VMStateField[]) {
724 VMSTATE_UINT8(state, Flash),
725 VMSTATE_UINT8_ARRAY(data, Flash, 16),
726 VMSTATE_UINT32(len, Flash),
727 VMSTATE_UINT32(pos, Flash),
728 VMSTATE_UINT8(needed_bytes, Flash),
729 VMSTATE_UINT8(cmd_in_progress, Flash),
730 VMSTATE_UINT64(cur_addr, Flash),
731 VMSTATE_BOOL(write_enable, Flash),
732 VMSTATE_BOOL_V(reset_enable, Flash, 2),
733 VMSTATE_UINT8_V(ear, Flash, 2),
734 VMSTATE_END_OF_LIST()
735 }
736 };
737
738 static void m25p80_class_init(ObjectClass *klass, void *data)
739 {
740 DeviceClass *dc = DEVICE_CLASS(klass);
741 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
742 M25P80Class *mc = M25P80_CLASS(klass);
743
744 k->init = m25p80_init;
745 k->transfer = m25p80_transfer8;
746 k->set_cs = m25p80_cs;
747 k->cs_polarity = SSI_CS_LOW;
748 dc->vmsd = &vmstate_m25p80;
749 dc->reset = m25p80_reset;
750 mc->pi = data;
751 }
752
753 static const TypeInfo m25p80_info = {
754 .name = TYPE_M25P80,
755 .parent = TYPE_SSI_SLAVE,
756 .instance_size = sizeof(Flash),
757 .class_size = sizeof(M25P80Class),
758 .abstract = true,
759 };
760
761 static void m25p80_register_types(void)
762 {
763 int i;
764
765 type_register_static(&m25p80_info);
766 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
767 TypeInfo ti = {
768 .name = known_devices[i].part_name,
769 .parent = TYPE_M25P80,
770 .class_init = m25p80_class_init,
771 .class_data = (void *)&known_devices[i],
772 };
773 type_register(&ti);
774 }
775 }
776
777 type_init(m25p80_register_types)
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