1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47 #include "sysemu/numa.h"
49 /* Supported chipsets: */
50 #include "hw/acpi/piix4.h"
51 #include "hw/acpi/pcihp.h"
52 #include "hw/i386/ich9.h"
53 #include "hw/pci/pci_bus.h"
54 #include "hw/pci-host/q35.h"
55 #include "hw/i386/x86-iommu.h"
56 #include "hw/timer/hpet.h"
58 #include "hw/acpi/aml-build.h"
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
65 #include "hw/acpi/ipmi.h"
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
88 typedef struct AcpiMcfgInfo
{
93 typedef struct AcpiPmInfo
{
99 uint8_t acpi_enable_cmd
;
100 uint8_t acpi_disable_cmd
;
102 uint32_t gpe0_blk_len
;
104 uint16_t cpu_hp_io_base
;
105 uint16_t mem_hp_io_base
;
106 uint16_t mem_hp_io_len
;
107 uint16_t pcihp_io_base
;
108 uint16_t pcihp_io_len
;
111 typedef struct AcpiMiscInfo
{
114 TPMVersion tpm_version
;
115 const unsigned char *dsdt_code
;
117 uint16_t pvpanic_port
;
118 uint16_t applesmc_io_base
;
121 typedef struct AcpiBuildPciBusHotplugState
{
122 GArray
*device_table
;
123 GArray
*notify_table
;
124 struct AcpiBuildPciBusHotplugState
*parent
;
125 bool pcihp_bridge_en
;
126 } AcpiBuildPciBusHotplugState
;
128 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
130 Object
*piix
= piix4_pm_find();
131 Object
*lpc
= ich9_lpc_find();
135 pm
->cpu_hp_io_base
= 0;
136 pm
->pcihp_io_base
= 0;
137 pm
->pcihp_io_len
= 0;
140 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
142 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
144 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
148 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
152 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
153 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
155 /* Fill in optional s3/s4 related properties */
156 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
158 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
160 pm
->s3_disabled
= false;
163 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
165 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
167 pm
->s4_disabled
= false;
170 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
172 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
178 /* Fill in mandatory properties */
179 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
181 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
182 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
184 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
185 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
187 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
189 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
191 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
193 pm
->pcihp_bridge_en
=
194 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
198 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
200 Object
*piix
= piix4_pm_find();
201 Object
*lpc
= ich9_lpc_find();
202 assert(!!piix
!= !!lpc
);
205 info
->is_piix4
= true;
208 info
->is_piix4
= false;
211 info
->has_hpet
= hpet_find();
212 info
->tpm_version
= tpm_get_version();
213 info
->pvpanic_port
= pvpanic_port();
214 info
->applesmc_io_base
= applesmc_port();
218 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
219 * On i386 arch we only have two pci hosts, so we can look only for them.
221 static Object
*acpi_get_i386_pci_host(void)
225 host
= OBJECT_CHECK(PCIHostState
,
226 object_resolve_path("/machine/i440fx", NULL
),
227 TYPE_PCI_HOST_BRIDGE
);
229 host
= OBJECT_CHECK(PCIHostState
,
230 object_resolve_path("/machine/q35", NULL
),
231 TYPE_PCI_HOST_BRIDGE
);
237 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
241 pci_host
= acpi_get_i386_pci_host();
244 range_set_bounds1(hole
,
245 object_property_get_int(pci_host
,
246 PCI_HOST_PROP_PCI_HOLE_START
,
248 object_property_get_int(pci_host
,
249 PCI_HOST_PROP_PCI_HOLE_END
,
251 range_set_bounds1(hole64
,
252 object_property_get_int(pci_host
,
253 PCI_HOST_PROP_PCI_HOLE64_START
,
255 object_property_get_int(pci_host
,
256 PCI_HOST_PROP_PCI_HOLE64_END
,
260 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
262 static void acpi_align_size(GArray
*blob
, unsigned align
)
264 /* Align size to multiple of given size. This reduces the chance
265 * we need to change size in the future (breaking cross version migration).
267 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
272 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
274 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
275 memcpy(&facs
->signature
, "FACS", 4);
276 facs
->length
= cpu_to_le32(sizeof(*facs
));
279 /* Load chipset information in FADT */
280 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
284 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
285 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
286 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
287 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
288 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
289 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
290 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
291 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
292 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
293 /* EVT, CNT, TMR length matches hw/acpi/core.c */
294 fadt
->pm1_evt_len
= 4;
295 fadt
->pm1_cnt_len
= 2;
296 fadt
->pm_tmr_len
= 4;
297 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
298 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
299 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
300 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
301 (1 << ACPI_FADT_F_PROC_C1
) |
302 (1 << ACPI_FADT_F_SLP_BUTTON
) |
303 (1 << ACPI_FADT_F_RTC_S4
));
304 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
305 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
306 * For more than 8 CPUs, "Clustered Logical" mode has to be used
309 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
311 fadt
->century
= RTC_CENTURY
;
317 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
318 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
319 const char *oem_id
, const char *oem_table_id
)
321 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
322 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
323 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
325 /* FACS address to be filled by Guest linker */
326 bios_linker_loader_add_pointer(linker
,
327 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
328 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
330 /* DSDT address to be filled by Guest linker */
331 fadt_setup(fadt
, pm
);
332 bios_linker_loader_add_pointer(linker
,
333 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
334 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
336 build_header(linker
, table_data
,
337 (void *)fadt
, "FACP", sizeof(*fadt
), 1, oem_id
, oem_table_id
);
340 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
341 CPUArchIdList
*apic_ids
, GArray
*entry
)
343 uint32_t apic_id
= apic_ids
->cpus
[uid
].arch_id
;
345 /* ACPI spec says that LAPIC entry for non present
346 * CPU may be omitted from MADT or it must be marked
347 * as disabled. However omitting non present CPU from
348 * MADT breaks hotplug on linux. So possible CPUs
349 * should be put in MADT but kept disabled.
352 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
354 apic
->type
= ACPI_APIC_PROCESSOR
;
355 apic
->length
= sizeof(*apic
);
356 apic
->processor_id
= uid
;
357 apic
->local_apic_id
= apic_id
;
358 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
359 apic
->flags
= cpu_to_le32(1);
361 apic
->flags
= cpu_to_le32(0);
364 AcpiMadtProcessorX2Apic
*apic
= acpi_data_push(entry
, sizeof *apic
);
366 apic
->type
= ACPI_APIC_LOCAL_X2APIC
;
367 apic
->length
= sizeof(*apic
);
368 apic
->uid
= cpu_to_le32(uid
);
369 apic
->x2apic_id
= cpu_to_le32(apic_id
);
370 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
371 apic
->flags
= cpu_to_le32(1);
373 apic
->flags
= cpu_to_le32(0);
379 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
381 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
382 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
383 int madt_start
= table_data
->len
;
384 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
385 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
386 bool x2apic_mode
= false;
388 AcpiMultipleApicTable
*madt
;
389 AcpiMadtIoApic
*io_apic
;
390 AcpiMadtIntsrcovr
*intsrcovr
;
393 madt
= acpi_data_push(table_data
, sizeof *madt
);
394 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
395 madt
->flags
= cpu_to_le32(1);
397 for (i
= 0; i
< apic_ids
->len
; i
++) {
398 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
399 if (apic_ids
->cpus
[i
].arch_id
> 254) {
405 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
406 io_apic
->type
= ACPI_APIC_IO
;
407 io_apic
->length
= sizeof(*io_apic
);
408 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
409 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
410 io_apic
->interrupt
= cpu_to_le32(0);
412 if (pcms
->apic_xrupt_override
) {
413 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
414 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
415 intsrcovr
->length
= sizeof(*intsrcovr
);
416 intsrcovr
->source
= 0;
417 intsrcovr
->gsi
= cpu_to_le32(2);
418 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
420 for (i
= 1; i
< 16; i
++) {
421 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
422 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
423 /* No need for a INT source override structure. */
426 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
427 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
428 intsrcovr
->length
= sizeof(*intsrcovr
);
429 intsrcovr
->source
= i
;
430 intsrcovr
->gsi
= cpu_to_le32(i
);
431 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
435 AcpiMadtLocalX2ApicNmi
*local_nmi
;
437 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
438 local_nmi
->type
= ACPI_APIC_LOCAL_X2APIC_NMI
;
439 local_nmi
->length
= sizeof(*local_nmi
);
440 local_nmi
->uid
= 0xFFFFFFFF; /* all processors */
441 local_nmi
->flags
= cpu_to_le16(0);
442 local_nmi
->lint
= 1; /* ACPI_LINT1 */
444 AcpiMadtLocalNmi
*local_nmi
;
446 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
447 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
448 local_nmi
->length
= sizeof(*local_nmi
);
449 local_nmi
->processor_id
= 0xff; /* all processors */
450 local_nmi
->flags
= cpu_to_le16(0);
451 local_nmi
->lint
= 1; /* ACPI_LINT1 */
454 build_header(linker
, table_data
,
455 (void *)(table_data
->data
+ madt_start
), "APIC",
456 table_data
->len
- madt_start
, 1, NULL
, NULL
);
459 /* Assign BSEL property to all buses. In the future, this can be changed
460 * to only assign to buses that support hotplug.
462 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
464 unsigned *bsel_alloc
= opaque
;
467 if (qbus_is_hotpluggable(BUS(bus
))) {
468 bus_bsel
= g_malloc(sizeof *bus_bsel
);
470 *bus_bsel
= (*bsel_alloc
)++;
471 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
478 static void acpi_set_pci_info(void)
480 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
481 unsigned bsel_alloc
= 0;
484 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
485 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
489 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
492 int32_t devfn
= PCI_DEVFN(slot
, 0);
494 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
495 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
496 aml_append(method
, if_ctx
);
499 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
500 bool pcihp_bridge_en
)
502 Aml
*dev
, *notify_method
, *method
;
507 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
509 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
511 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
512 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
515 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
518 PCIDevice
*pdev
= bus
->devices
[i
];
519 int slot
= PCI_SLOT(i
);
520 bool hotplug_enabled_dev
;
524 if (bsel
) { /* add hotplug slots for non present devices */
525 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
526 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
527 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
528 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
530 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
532 aml_append(dev
, method
);
533 aml_append(parent_scope
, dev
);
535 build_append_pcihp_notify_entry(notify_method
, slot
);
540 pc
= PCI_DEVICE_GET_CLASS(pdev
);
541 dc
= DEVICE_GET_CLASS(pdev
);
543 /* When hotplug for bridges is enabled, bridges are
544 * described in ACPI separately (see build_pci_bus_end).
545 * In this case they aren't themselves hot-pluggable.
546 * Hotplugged bridges *are* hot-pluggable.
548 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
549 !DEVICE(pdev
)->hotplugged
;
551 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
553 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
557 /* start to compose PCI slot descriptor */
558 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
559 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
561 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
562 /* add VGA specific AML methods */
565 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
571 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
572 aml_append(method
, aml_return(aml_int(0)));
573 aml_append(dev
, method
);
575 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
576 aml_append(method
, aml_return(aml_int(0)));
577 aml_append(dev
, method
);
579 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
580 aml_append(method
, aml_return(aml_int(s3d
)));
581 aml_append(dev
, method
);
582 } else if (hotplug_enabled_dev
) {
583 /* add _SUN/_EJ0 to make slot hotpluggable */
584 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
586 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
588 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
590 aml_append(dev
, method
);
593 build_append_pcihp_notify_entry(notify_method
, slot
);
595 } else if (bridge_in_acpi
) {
597 * device is coldplugged bridge,
598 * add child device descriptions into its scope
600 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
602 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
604 /* slot descriptor has been composed, add it into parent context */
605 aml_append(parent_scope
, dev
);
609 aml_append(parent_scope
, notify_method
);
612 /* Append PCNT method to notify about events on local and child buses.
613 * Add unconditionally for root since DSDT expects it.
615 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
617 /* If bus supports hotplug select it and notify about local events */
619 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
620 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
622 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
625 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
629 /* Notify about child bus events in any case */
630 if (pcihp_bridge_en
) {
631 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
632 int32_t devfn
= sec
->parent_dev
->devfn
;
634 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
638 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
641 aml_append(parent_scope
, method
);
642 qobject_decref(bsel
);
647 * @link_name: link name for PCI route entry
649 * build AML package containing a PCI route entry for @link_name
651 static Aml
*build_prt_entry(const char *link_name
)
653 Aml
*a_zero
= aml_int(0);
654 Aml
*pkg
= aml_package(4);
655 aml_append(pkg
, a_zero
);
656 aml_append(pkg
, a_zero
);
657 aml_append(pkg
, aml_name("%s", link_name
));
658 aml_append(pkg
, a_zero
);
663 * initialize_route - Initialize the interrupt routing rule
664 * through a specific LINK:
665 * if (lnk_idx == idx)
666 * route using link 'link_name'
668 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
669 Aml
*lnk_idx
, int idx
)
671 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
672 Aml
*pkg
= build_prt_entry(link_name
);
674 aml_append(if_ctx
, aml_store(pkg
, route
));
680 * build_prt - Define interrupt rounting rules
682 * Returns an array of 128 routes, one for each device,
683 * based on device location.
684 * The main goal is to equaly distribute the interrupts
685 * over the 4 existing ACPI links (works only for i440fx).
686 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
689 static Aml
*build_prt(bool is_pci0_prt
)
691 Aml
*method
, *while_ctx
, *pin
, *res
;
693 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
696 aml_append(method
, aml_store(aml_package(128), res
));
697 aml_append(method
, aml_store(aml_int(0), pin
));
699 /* while (pin < 128) */
700 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
702 Aml
*slot
= aml_local(2);
703 Aml
*lnk_idx
= aml_local(3);
704 Aml
*route
= aml_local(4);
706 /* slot = pin >> 2 */
707 aml_append(while_ctx
,
708 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
709 /* lnk_idx = (slot + pin) & 3 */
710 aml_append(while_ctx
,
711 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
714 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
715 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
717 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
719 /* device 1 is the power-management device, needs SCI */
720 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
722 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
725 aml_store(build_prt_entry("LNKS"), route
));
727 aml_append(if_device_1
, if_pin_4
);
728 else_pin_4
= aml_else();
730 aml_append(else_pin_4
,
731 aml_store(build_prt_entry("LNKA"), route
));
733 aml_append(if_device_1
, else_pin_4
);
735 aml_append(while_ctx
, if_device_1
);
737 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
739 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
740 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
742 /* route[0] = 0x[slot]FFFF */
743 aml_append(while_ctx
,
744 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
746 aml_index(route
, aml_int(0))));
747 /* route[1] = pin & 3 */
748 aml_append(while_ctx
,
749 aml_store(aml_and(pin
, aml_int(3), NULL
),
750 aml_index(route
, aml_int(1))));
751 /* res[pin] = route */
752 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
754 aml_append(while_ctx
, aml_increment(pin
));
756 aml_append(method
, while_ctx
);
758 aml_append(method
, aml_return(res
));
763 typedef struct CrsRangeEntry
{
768 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
770 CrsRangeEntry
*entry
;
772 entry
= g_malloc(sizeof(*entry
));
774 entry
->limit
= limit
;
776 g_ptr_array_add(ranges
, entry
);
779 static void crs_range_free(gpointer data
)
781 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
785 typedef struct CrsRangeSet
{
786 GPtrArray
*io_ranges
;
787 GPtrArray
*mem_ranges
;
788 GPtrArray
*mem_64bit_ranges
;
791 static void crs_range_set_init(CrsRangeSet
*range_set
)
793 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
794 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
795 range_set
->mem_64bit_ranges
=
796 g_ptr_array_new_with_free_func(crs_range_free
);
799 static void crs_range_set_free(CrsRangeSet
*range_set
)
801 g_ptr_array_free(range_set
->io_ranges
, true);
802 g_ptr_array_free(range_set
->mem_ranges
, true);
803 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
806 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
808 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
809 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
811 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
815 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
816 * interval, computes the 'free' ranges from the same interval.
817 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
818 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
820 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
821 uint64_t start
, uint64_t end
)
823 GPtrArray
*free_ranges
= g_ptr_array_new();
824 uint64_t free_base
= start
;
827 g_ptr_array_sort(ranges
, crs_range_compare
);
828 for (i
= 0; i
< ranges
->len
; i
++) {
829 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
831 if (free_base
< used
->base
) {
832 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
835 free_base
= used
->limit
+ 1;
838 if (free_base
< end
) {
839 crs_range_insert(free_ranges
, free_base
, end
);
842 g_ptr_array_set_size(ranges
, 0);
843 for (i
= 0; i
< free_ranges
->len
; i
++) {
844 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
847 g_ptr_array_free(free_ranges
, true);
851 * crs_range_merge - merges adjacent ranges in the given array.
852 * Array elements are deleted and replaced with the merged ranges.
854 static void crs_range_merge(GPtrArray
*range
)
856 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
857 CrsRangeEntry
*entry
;
858 uint64_t range_base
, range_limit
;
865 g_ptr_array_sort(range
, crs_range_compare
);
867 entry
= g_ptr_array_index(range
, 0);
868 range_base
= entry
->base
;
869 range_limit
= entry
->limit
;
870 for (i
= 1; i
< range
->len
; i
++) {
871 entry
= g_ptr_array_index(range
, i
);
872 if (entry
->base
- 1 == range_limit
) {
873 range_limit
= entry
->limit
;
875 crs_range_insert(tmp
, range_base
, range_limit
);
876 range_base
= entry
->base
;
877 range_limit
= entry
->limit
;
880 crs_range_insert(tmp
, range_base
, range_limit
);
882 g_ptr_array_set_size(range
, 0);
883 for (i
= 0; i
< tmp
->len
; i
++) {
884 entry
= g_ptr_array_index(tmp
, i
);
885 crs_range_insert(range
, entry
->base
, entry
->limit
);
887 g_ptr_array_free(tmp
, true);
890 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
892 Aml
*crs
= aml_resource_template();
893 CrsRangeSet temp_range_set
;
894 CrsRangeEntry
*entry
;
895 uint8_t max_bus
= pci_bus_num(host
->bus
);
900 crs_range_set_init(&temp_range_set
);
901 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
902 uint64_t range_base
, range_limit
;
903 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
909 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
910 PCIIORegion
*r
= &dev
->io_regions
[i
];
912 range_base
= r
->addr
;
913 range_limit
= r
->addr
+ r
->size
- 1;
916 * Work-around for old bioses
917 * that do not support multiple root buses
919 if (!range_base
|| range_base
> range_limit
) {
923 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
924 crs_range_insert(temp_range_set
.io_ranges
,
925 range_base
, range_limit
);
926 } else { /* "memory" */
927 crs_range_insert(temp_range_set
.mem_ranges
,
928 range_base
, range_limit
);
932 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
933 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
934 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
935 if (subordinate
> max_bus
) {
936 max_bus
= subordinate
;
939 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
940 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
943 * Work-around for old bioses
944 * that do not support multiple root buses
946 if (range_base
&& range_base
<= range_limit
) {
947 crs_range_insert(temp_range_set
.io_ranges
,
948 range_base
, range_limit
);
952 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
954 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
957 * Work-around for old bioses
958 * that do not support multiple root buses
960 if (range_base
&& range_base
<= range_limit
) {
961 uint64_t length
= range_limit
- range_base
+ 1;
962 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
963 crs_range_insert(temp_range_set
.mem_ranges
,
964 range_base
, range_limit
);
966 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
967 range_base
, range_limit
);
972 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
974 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
977 * Work-around for old bioses
978 * that do not support multiple root buses
980 if (range_base
&& range_base
<= range_limit
) {
981 uint64_t length
= range_limit
- range_base
+ 1;
982 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
983 crs_range_insert(temp_range_set
.mem_ranges
,
984 range_base
, range_limit
);
986 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
987 range_base
, range_limit
);
993 crs_range_merge(temp_range_set
.io_ranges
);
994 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
995 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
997 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
998 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
999 0, entry
->base
, entry
->limit
, 0,
1000 entry
->limit
- entry
->base
+ 1));
1001 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
1004 crs_range_merge(temp_range_set
.mem_ranges
);
1005 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
1006 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
1008 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1009 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1011 0, entry
->base
, entry
->limit
, 0,
1012 entry
->limit
- entry
->base
+ 1));
1013 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
1016 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
1017 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
1018 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
1020 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1021 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
1023 0, entry
->base
, entry
->limit
, 0,
1024 entry
->limit
- entry
->base
+ 1));
1025 crs_range_insert(range_set
->mem_64bit_ranges
,
1026 entry
->base
, entry
->limit
);
1029 crs_range_set_free(&temp_range_set
);
1032 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1034 pci_bus_num(host
->bus
),
1037 max_bus
- pci_bus_num(host
->bus
) + 1));
1042 static void build_memory_devices(Aml
*sb_scope
, int nr_mem
,
1043 uint16_t io_base
, uint16_t io_len
)
1053 /* build memory devices */
1054 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
1055 scope
= aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE
);
1057 aml_name_decl(MEMORY_SLOTS_NUMBER
, aml_int(nr_mem
))
1060 crs
= aml_resource_template();
1062 aml_io(AML_DECODE16
, io_base
, io_base
, 0, io_len
)
1064 aml_append(scope
, aml_name_decl("_CRS", crs
));
1066 aml_append(scope
, aml_operation_region(
1067 MEMORY_HOTPLUG_IO_REGION
, AML_SYSTEM_IO
,
1068 aml_int(io_base
), io_len
)
1071 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1072 AML_NOLOCK
, AML_PRESERVE
);
1073 aml_append(field
, /* read only */
1074 aml_named_field(MEMORY_SLOT_ADDR_LOW
, 32));
1075 aml_append(field
, /* read only */
1076 aml_named_field(MEMORY_SLOT_ADDR_HIGH
, 32));
1077 aml_append(field
, /* read only */
1078 aml_named_field(MEMORY_SLOT_SIZE_LOW
, 32));
1079 aml_append(field
, /* read only */
1080 aml_named_field(MEMORY_SLOT_SIZE_HIGH
, 32));
1081 aml_append(field
, /* read only */
1082 aml_named_field(MEMORY_SLOT_PROXIMITY
, 32));
1083 aml_append(scope
, field
);
1085 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_BYTE_ACC
,
1086 AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1087 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
1088 aml_append(field
, /* 1 if enabled, read only */
1089 aml_named_field(MEMORY_SLOT_ENABLED
, 1));
1091 /*(read) 1 if has a insert event. (write) 1 to clear event */
1092 aml_named_field(MEMORY_SLOT_INSERT_EVENT
, 1));
1094 /* (read) 1 if has a remove event. (write) 1 to clear event */
1095 aml_named_field(MEMORY_SLOT_REMOVE_EVENT
, 1));
1097 /* initiates device eject, write only */
1098 aml_named_field(MEMORY_SLOT_EJECT
, 1));
1099 aml_append(scope
, field
);
1101 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1102 AML_NOLOCK
, AML_PRESERVE
);
1103 aml_append(field
, /* DIMM selector, write only */
1104 aml_named_field(MEMORY_SLOT_SLECTOR
, 32));
1105 aml_append(field
, /* _OST event code, write only */
1106 aml_named_field(MEMORY_SLOT_OST_EVENT
, 32));
1107 aml_append(field
, /* _OST status code, write only */
1108 aml_named_field(MEMORY_SLOT_OST_STATUS
, 32));
1109 aml_append(scope
, field
);
1110 aml_append(sb_scope
, scope
);
1112 for (i
= 0; i
< nr_mem
; i
++) {
1113 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1116 dev
= aml_device("MP%02X", i
);
1117 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1118 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1120 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1121 s
= BASEPATH MEMORY_SLOT_CRS_METHOD
;
1122 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1123 aml_append(dev
, method
);
1125 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1126 s
= BASEPATH MEMORY_SLOT_STATUS_METHOD
;
1127 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1128 aml_append(dev
, method
);
1130 method
= aml_method("_PXM", 0, AML_NOTSERIALIZED
);
1131 s
= BASEPATH MEMORY_SLOT_PROXIMITY_METHOD
;
1132 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1133 aml_append(dev
, method
);
1135 method
= aml_method("_OST", 3, AML_NOTSERIALIZED
);
1136 s
= BASEPATH MEMORY_SLOT_OST_METHOD
;
1138 aml_append(method
, aml_return(aml_call4(
1139 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1141 aml_append(dev
, method
);
1143 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
1144 s
= BASEPATH MEMORY_SLOT_EJECT_METHOD
;
1145 aml_append(method
, aml_return(aml_call2(
1146 s
, aml_name("_UID"), aml_arg(0))));
1147 aml_append(dev
, method
);
1149 aml_append(sb_scope
, dev
);
1152 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1153 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1155 method
= aml_method(MEMORY_SLOT_NOTIFY_METHOD
, 2, AML_NOTSERIALIZED
);
1156 for (i
= 0; i
< nr_mem
; i
++) {
1157 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1159 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1161 aml_append(method
, ifctx
);
1163 aml_append(sb_scope
, method
);
1166 static void build_hpet_aml(Aml
*table
)
1172 Aml
*scope
= aml_scope("_SB");
1173 Aml
*dev
= aml_device("HPET");
1174 Aml
*zero
= aml_int(0);
1175 Aml
*id
= aml_local(0);
1176 Aml
*period
= aml_local(1);
1178 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1179 aml_append(dev
, aml_name_decl("_UID", zero
));
1182 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1184 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1185 aml_append(field
, aml_named_field("VEND", 32));
1186 aml_append(field
, aml_named_field("PRD", 32));
1187 aml_append(dev
, field
);
1189 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1190 aml_append(method
, aml_store(aml_name("VEND"), id
));
1191 aml_append(method
, aml_store(aml_name("PRD"), period
));
1192 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1193 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1194 aml_equal(id
, aml_int(0xffff))));
1196 aml_append(if_ctx
, aml_return(zero
));
1198 aml_append(method
, if_ctx
);
1200 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1201 aml_lgreater(period
, aml_int(100000000))));
1203 aml_append(if_ctx
, aml_return(zero
));
1205 aml_append(method
, if_ctx
);
1207 aml_append(method
, aml_return(aml_int(0x0F)));
1208 aml_append(dev
, method
);
1210 crs
= aml_resource_template();
1211 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1212 aml_append(dev
, aml_name_decl("_CRS", crs
));
1214 aml_append(scope
, dev
);
1215 aml_append(table
, scope
);
1218 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1221 uint8_t maxc
, maxh
, maxs
;
1223 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1225 dev
= aml_device("FLP%c", 'A' + idx
);
1227 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1229 fdi
= aml_package(16);
1230 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1232 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1234 * the values below are the limits of the drive, and are thus independent
1235 * of the inserted media
1237 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1238 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1239 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1241 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1242 * the drive type, so shall we
1244 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1245 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1246 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1247 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1248 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1249 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1250 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1251 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1252 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1253 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1254 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1256 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1260 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1266 #define ACPI_FDE_MAX_FD 4
1267 uint32_t fde_buf
[5] = {
1268 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1269 cpu_to_le32(2) /* tape presence (2 == never present) */
1272 dev
= aml_device("FDC0");
1273 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1275 crs
= aml_resource_template();
1276 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1277 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1278 aml_append(crs
, aml_irq_no_flags(6));
1280 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1281 aml_append(dev
, aml_name_decl("_CRS", crs
));
1283 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1284 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1286 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1287 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1288 aml_append(dev
, build_fdinfo_aml(i
, type
));
1291 aml_append(dev
, aml_name_decl("_FDE",
1292 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1297 static Aml
*build_rtc_device_aml(void)
1302 dev
= aml_device("RTC");
1303 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1304 crs
= aml_resource_template();
1305 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1306 aml_append(crs
, aml_irq_no_flags(8));
1307 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1308 aml_append(dev
, aml_name_decl("_CRS", crs
));
1313 static Aml
*build_kbd_device_aml(void)
1319 dev
= aml_device("KBD");
1320 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1322 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1323 aml_append(method
, aml_return(aml_int(0x0f)));
1324 aml_append(dev
, method
);
1326 crs
= aml_resource_template();
1327 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1328 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1329 aml_append(crs
, aml_irq_no_flags(1));
1330 aml_append(dev
, aml_name_decl("_CRS", crs
));
1335 static Aml
*build_mouse_device_aml(void)
1341 dev
= aml_device("MOU");
1342 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1344 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1345 aml_append(method
, aml_return(aml_int(0x0f)));
1346 aml_append(dev
, method
);
1348 crs
= aml_resource_template();
1349 aml_append(crs
, aml_irq_no_flags(12));
1350 aml_append(dev
, aml_name_decl("_CRS", crs
));
1355 static Aml
*build_lpt_device_aml(void)
1362 Aml
*zero
= aml_int(0);
1363 Aml
*is_present
= aml_local(0);
1365 dev
= aml_device("LPT");
1366 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1368 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1369 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1370 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1372 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1374 aml_append(method
, if_ctx
);
1375 else_ctx
= aml_else();
1377 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1379 aml_append(method
, else_ctx
);
1380 aml_append(dev
, method
);
1382 crs
= aml_resource_template();
1383 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1384 aml_append(crs
, aml_irq_no_flags(7));
1385 aml_append(dev
, aml_name_decl("_CRS", crs
));
1390 static Aml
*build_com_device_aml(uint8_t uid
)
1397 Aml
*zero
= aml_int(0);
1398 Aml
*is_present
= aml_local(0);
1399 const char *enabled_field
= "CAEN";
1401 uint16_t io_port
= 0x03F8;
1403 assert(uid
== 1 || uid
== 2);
1405 enabled_field
= "CBEN";
1410 dev
= aml_device("COM%d", uid
);
1411 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1412 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1414 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1415 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1416 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1418 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1420 aml_append(method
, if_ctx
);
1421 else_ctx
= aml_else();
1423 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1425 aml_append(method
, else_ctx
);
1426 aml_append(dev
, method
);
1428 crs
= aml_resource_template();
1429 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1430 aml_append(crs
, aml_irq_no_flags(irq
));
1431 aml_append(dev
, aml_name_decl("_CRS", crs
));
1436 static void build_isa_devices_aml(Aml
*table
)
1438 ISADevice
*fdc
= pc_find_fdc0();
1441 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1442 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1444 aml_append(scope
, build_rtc_device_aml());
1445 aml_append(scope
, build_kbd_device_aml());
1446 aml_append(scope
, build_mouse_device_aml());
1448 aml_append(scope
, build_fdc_device_aml(fdc
));
1450 aml_append(scope
, build_lpt_device_aml());
1451 aml_append(scope
, build_com_device_aml(1));
1452 aml_append(scope
, build_com_device_aml(2));
1455 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1457 error_report("No ISA bus, unable to define IPMI ACPI data");
1459 build_acpi_ipmi_devices(scope
, BUS(obj
));
1462 aml_append(table
, scope
);
1465 static void build_dbg_aml(Aml
*table
)
1470 Aml
*scope
= aml_scope("\\");
1471 Aml
*buf
= aml_local(0);
1472 Aml
*len
= aml_local(1);
1473 Aml
*idx
= aml_local(2);
1476 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1477 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1478 aml_append(field
, aml_named_field("DBGB", 8));
1479 aml_append(scope
, field
);
1481 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1483 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1484 aml_append(method
, aml_to_buffer(buf
, buf
));
1485 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1486 aml_append(method
, aml_store(aml_int(0), idx
));
1488 while_ctx
= aml_while(aml_lless(idx
, len
));
1489 aml_append(while_ctx
,
1490 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1491 aml_append(while_ctx
, aml_increment(idx
));
1492 aml_append(method
, while_ctx
);
1494 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1495 aml_append(scope
, method
);
1497 aml_append(table
, scope
);
1500 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1505 uint32_t irqs
[] = {5, 10, 11};
1507 dev
= aml_device("%s", name
);
1508 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1509 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1511 crs
= aml_resource_template();
1512 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1513 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1514 aml_append(dev
, aml_name_decl("_PRS", crs
));
1516 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1517 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1518 aml_append(dev
, method
);
1520 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1521 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1522 aml_append(dev
, method
);
1524 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1525 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1526 aml_append(dev
, method
);
1528 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1529 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1530 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1531 aml_append(dev
, method
);
1536 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1543 dev
= aml_device("%s", name
);
1544 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1545 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1547 crs
= aml_resource_template();
1549 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1550 AML_SHARED
, &irqs
, 1));
1551 aml_append(dev
, aml_name_decl("_PRS", crs
));
1553 aml_append(dev
, aml_name_decl("_CRS", crs
));
1556 * _DIS can be no-op because the interrupt cannot be disabled.
1558 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1559 aml_append(dev
, method
);
1561 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1562 aml_append(dev
, method
);
1567 /* _CRS method - get current settings */
1568 static Aml
*build_iqcr_method(bool is_piix4
)
1572 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1573 Aml
*crs
= aml_resource_template();
1576 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1577 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1578 aml_append(method
, aml_name_decl("PRR0", crs
));
1581 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1584 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1585 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1586 aml_append(method
, if_ctx
);
1589 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1593 aml_append(method
, aml_return(aml_name("PRR0")));
1597 /* _STA method - get status */
1598 static Aml
*build_irq_status_method(void)
1601 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1603 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1604 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1605 aml_append(method
, if_ctx
);
1606 aml_append(method
, aml_return(aml_int(0x0B)));
1610 static void build_piix4_pci0_int(Aml
*table
)
1617 Aml
*sb_scope
= aml_scope("_SB");
1618 Aml
*pci0_scope
= aml_scope("PCI0");
1620 aml_append(pci0_scope
, build_prt(true));
1621 aml_append(sb_scope
, pci0_scope
);
1623 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1624 aml_append(field
, aml_named_field("PRQ0", 8));
1625 aml_append(field
, aml_named_field("PRQ1", 8));
1626 aml_append(field
, aml_named_field("PRQ2", 8));
1627 aml_append(field
, aml_named_field("PRQ3", 8));
1628 aml_append(sb_scope
, field
);
1630 aml_append(sb_scope
, build_irq_status_method());
1631 aml_append(sb_scope
, build_iqcr_method(true));
1633 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1634 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1635 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1636 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1638 dev
= aml_device("LNKS");
1640 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1641 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1643 crs
= aml_resource_template();
1645 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1646 AML_ACTIVE_HIGH
, AML_SHARED
,
1648 aml_append(dev
, aml_name_decl("_PRS", crs
));
1650 /* The SCI cannot be disabled and is always attached to GSI 9,
1651 * so these are no-ops. We only need this link to override the
1652 * polarity to active high and match the content of the MADT.
1654 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1655 aml_append(method
, aml_return(aml_int(0x0b)));
1656 aml_append(dev
, method
);
1658 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1659 aml_append(dev
, method
);
1661 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1662 aml_append(method
, aml_return(aml_name("_PRS")));
1663 aml_append(dev
, method
);
1665 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1666 aml_append(dev
, method
);
1668 aml_append(sb_scope
, dev
);
1670 aml_append(table
, sb_scope
);
1673 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1678 char base
= name
[3] < 'E' ? 'A' : 'E';
1679 char *s
= g_strdup(name
);
1680 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1682 assert(strlen(s
) == 4);
1684 head
= name
[3] - base
;
1685 for (i
= 0; i
< 4; i
++) {
1689 s
[3] = base
+ head
+ i
;
1690 pkg
= aml_package(4);
1691 aml_append(pkg
, a_nr
);
1692 aml_append(pkg
, aml_int(i
));
1693 aml_append(pkg
, aml_name("%s", s
));
1694 aml_append(pkg
, aml_int(0));
1695 aml_append(ctx
, pkg
);
1700 static Aml
*build_q35_routing_table(const char *str
)
1704 char *name
= g_strdup_printf("%s ", str
);
1706 pkg
= aml_package(128);
1707 for (i
= 0; i
< 0x18; i
++) {
1708 name
[3] = 'E' + (i
& 0x3);
1709 append_q35_prt_entry(pkg
, i
, name
);
1713 append_q35_prt_entry(pkg
, 0x18, name
);
1715 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1716 for (i
= 0x0019; i
< 0x1e; i
++) {
1718 append_q35_prt_entry(pkg
, i
, name
);
1721 /* PCIe->PCI bridge. use PIRQ[E-H] */
1723 append_q35_prt_entry(pkg
, 0x1e, name
);
1725 append_q35_prt_entry(pkg
, 0x1f, name
);
1731 static void build_q35_pci0_int(Aml
*table
)
1735 Aml
*sb_scope
= aml_scope("_SB");
1736 Aml
*pci0_scope
= aml_scope("PCI0");
1738 /* Zero => PIC mode, One => APIC Mode */
1739 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1740 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1742 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1744 aml_append(table
, method
);
1746 aml_append(pci0_scope
,
1747 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1748 aml_append(pci0_scope
,
1749 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1751 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1756 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1758 /* Note: we provide the same info as the PCI routing
1759 table of the Bochs BIOS */
1760 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1761 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1762 aml_append(method
, if_ctx
);
1763 else_ctx
= aml_else();
1764 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1765 aml_append(method
, else_ctx
);
1767 aml_append(pci0_scope
, method
);
1768 aml_append(sb_scope
, pci0_scope
);
1770 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1771 aml_append(field
, aml_named_field("PRQA", 8));
1772 aml_append(field
, aml_named_field("PRQB", 8));
1773 aml_append(field
, aml_named_field("PRQC", 8));
1774 aml_append(field
, aml_named_field("PRQD", 8));
1775 aml_append(field
, aml_reserved_field(0x20));
1776 aml_append(field
, aml_named_field("PRQE", 8));
1777 aml_append(field
, aml_named_field("PRQF", 8));
1778 aml_append(field
, aml_named_field("PRQG", 8));
1779 aml_append(field
, aml_named_field("PRQH", 8));
1780 aml_append(sb_scope
, field
);
1782 aml_append(sb_scope
, build_irq_status_method());
1783 aml_append(sb_scope
, build_iqcr_method(false));
1785 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1786 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1787 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1788 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1789 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1790 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1791 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1792 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1794 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1795 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1796 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1797 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1798 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1799 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1800 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1801 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1803 aml_append(table
, sb_scope
);
1806 static void build_q35_isa_bridge(Aml
*table
)
1812 scope
= aml_scope("_SB.PCI0");
1813 dev
= aml_device("ISA");
1814 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1816 /* ICH9 PCI to ISA irq remapping */
1817 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1818 aml_int(0x60), 0x0C));
1820 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1821 aml_int(0x80), 0x02));
1822 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1823 aml_append(field
, aml_named_field("COMA", 3));
1824 aml_append(field
, aml_reserved_field(1));
1825 aml_append(field
, aml_named_field("COMB", 3));
1826 aml_append(field
, aml_reserved_field(1));
1827 aml_append(field
, aml_named_field("LPTD", 2));
1828 aml_append(dev
, field
);
1830 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1831 aml_int(0x82), 0x02));
1833 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1834 aml_append(field
, aml_named_field("CAEN", 1));
1835 aml_append(field
, aml_named_field("CBEN", 1));
1836 aml_append(field
, aml_named_field("LPEN", 1));
1837 aml_append(dev
, field
);
1839 aml_append(scope
, dev
);
1840 aml_append(table
, scope
);
1843 static void build_piix4_pm(Aml
*table
)
1848 scope
= aml_scope("_SB.PCI0");
1849 dev
= aml_device("PX13");
1850 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1852 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1853 aml_int(0x00), 0xff));
1854 aml_append(scope
, dev
);
1855 aml_append(table
, scope
);
1858 static void build_piix4_isa_bridge(Aml
*table
)
1864 scope
= aml_scope("_SB.PCI0");
1865 dev
= aml_device("ISA");
1866 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1868 /* PIIX PCI to ISA irq remapping */
1869 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1870 aml_int(0x60), 0x04));
1872 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1873 /* Offset(0x5f),, 7, */
1874 aml_append(field
, aml_reserved_field(0x2f8));
1875 aml_append(field
, aml_reserved_field(7));
1876 aml_append(field
, aml_named_field("LPEN", 1));
1877 /* Offset(0x67),, 3, */
1878 aml_append(field
, aml_reserved_field(0x38));
1879 aml_append(field
, aml_reserved_field(3));
1880 aml_append(field
, aml_named_field("CAEN", 1));
1881 aml_append(field
, aml_reserved_field(3));
1882 aml_append(field
, aml_named_field("CBEN", 1));
1883 aml_append(dev
, field
);
1885 aml_append(scope
, dev
);
1886 aml_append(table
, scope
);
1889 static void build_piix4_pci_hotplug(Aml
*table
)
1895 scope
= aml_scope("_SB.PCI0");
1898 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1899 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1900 aml_append(field
, aml_named_field("PCIU", 32));
1901 aml_append(field
, aml_named_field("PCID", 32));
1902 aml_append(scope
, field
);
1905 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1906 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1907 aml_append(field
, aml_named_field("B0EJ", 32));
1908 aml_append(scope
, field
);
1911 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1912 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1913 aml_append(field
, aml_named_field("BNUM", 32));
1914 aml_append(scope
, field
);
1916 aml_append(scope
, aml_mutex("BLCK", 0));
1918 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1919 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1920 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1922 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1923 aml_append(method
, aml_release(aml_name("BLCK")));
1924 aml_append(method
, aml_return(aml_int(0)));
1925 aml_append(scope
, method
);
1927 aml_append(table
, scope
);
1930 static Aml
*build_q35_osc_method(void)
1936 Aml
*a_cwd1
= aml_name("CDW1");
1937 Aml
*a_ctrl
= aml_name("CTRL");
1939 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1940 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1942 if_ctx
= aml_if(aml_equal(
1943 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1944 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1945 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1947 aml_append(if_ctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1948 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1951 * Always allow native PME, AER (no dependencies)
1952 * Never allow SHPC (no SHPC controller in this system)
1954 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1956 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1957 /* Unknown revision */
1958 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1959 aml_append(if_ctx
, if_ctx2
);
1961 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1962 /* Capabilities bits were masked */
1963 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1964 aml_append(if_ctx
, if_ctx2
);
1966 /* Update DWORD3 in the buffer */
1967 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1968 aml_append(method
, if_ctx
);
1970 else_ctx
= aml_else();
1971 /* Unrecognized UUID */
1972 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1973 aml_append(method
, else_ctx
);
1975 aml_append(method
, aml_return(aml_arg(3)));
1980 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1981 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1982 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1984 CrsRangeEntry
*entry
;
1985 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1986 CrsRangeSet crs_range_set
;
1987 PCMachineState
*pcms
= PC_MACHINE(machine
);
1988 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1989 uint32_t nr_mem
= machine
->ram_slots
;
1990 int root_bus_limit
= 0xFF;
1994 dsdt
= init_aml_allocator();
1996 /* Reserve space for header */
1997 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1999 build_dbg_aml(dsdt
);
2000 if (misc
->is_piix4
) {
2001 sb_scope
= aml_scope("_SB");
2002 dev
= aml_device("PCI0");
2003 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2004 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
2005 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
2006 aml_append(sb_scope
, dev
);
2007 aml_append(dsdt
, sb_scope
);
2009 build_hpet_aml(dsdt
);
2010 build_piix4_pm(dsdt
);
2011 build_piix4_isa_bridge(dsdt
);
2012 build_isa_devices_aml(dsdt
);
2013 build_piix4_pci_hotplug(dsdt
);
2014 build_piix4_pci0_int(dsdt
);
2016 sb_scope
= aml_scope("_SB");
2017 aml_append(sb_scope
,
2018 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
2019 aml_append(sb_scope
,
2020 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
2021 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
2022 aml_append(field
, aml_named_field("PCIB", 8));
2023 aml_append(sb_scope
, field
);
2024 aml_append(dsdt
, sb_scope
);
2026 sb_scope
= aml_scope("_SB");
2027 dev
= aml_device("PCI0");
2028 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2029 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2030 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
2031 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
2032 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
2033 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
2034 aml_append(dev
, build_q35_osc_method());
2035 aml_append(sb_scope
, dev
);
2036 aml_append(dsdt
, sb_scope
);
2038 build_hpet_aml(dsdt
);
2039 build_q35_isa_bridge(dsdt
);
2040 build_isa_devices_aml(dsdt
);
2041 build_q35_pci0_int(dsdt
);
2044 if (pcmc
->legacy_cpu_hotplug
) {
2045 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
2047 CPUHotplugFeatures opts
= {
2048 .apci_1_compatible
= true, .has_legacy_cphp
= true
2050 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
2051 "\\_SB.PCI0", "\\_GPE._E02");
2053 build_memory_hotplug_aml(dsdt
, nr_mem
, pm
->mem_hp_io_base
,
2056 scope
= aml_scope("_GPE");
2058 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
2060 if (misc
->is_piix4
) {
2061 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
2063 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2064 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
2065 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2066 aml_append(scope
, method
);
2069 method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
2070 aml_append(method
, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH
));
2071 aml_append(scope
, method
);
2073 aml_append(dsdt
, scope
);
2075 crs_range_set_init(&crs_range_set
);
2076 bus
= PC_MACHINE(machine
)->bus
;
2078 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
2079 uint8_t bus_num
= pci_bus_num(bus
);
2080 uint8_t numa_node
= pci_bus_numa_node(bus
);
2082 /* look only for expander root buses */
2083 if (!pci_bus_is_root(bus
)) {
2087 if (bus_num
< root_bus_limit
) {
2088 root_bus_limit
= bus_num
- 1;
2091 scope
= aml_scope("\\_SB");
2092 dev
= aml_device("PC%.02X", bus_num
);
2093 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
2094 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2095 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
2097 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
2098 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
2101 aml_append(dev
, build_prt(false));
2102 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
2103 aml_append(dev
, aml_name_decl("_CRS", crs
));
2104 aml_append(scope
, dev
);
2105 aml_append(dsdt
, scope
);
2109 scope
= aml_scope("\\_SB.PCI0");
2110 /* build PCI0._CRS */
2111 crs
= aml_resource_template();
2113 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
2114 0x0000, 0x0, root_bus_limit
,
2115 0x0000, root_bus_limit
+ 1));
2116 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
2119 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2120 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2121 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2123 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
2124 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
2125 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
2127 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2128 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2129 0x0000, entry
->base
, entry
->limit
,
2130 0x0000, entry
->limit
- entry
->base
+ 1));
2134 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2135 AML_CACHEABLE
, AML_READ_WRITE
,
2136 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2138 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
2139 range_lob(pci_hole
),
2140 range_upb(pci_hole
));
2141 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
2142 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
2144 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2145 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2146 0, entry
->base
, entry
->limit
,
2147 0, entry
->limit
- entry
->base
+ 1));
2150 if (!range_is_empty(pci_hole64
)) {
2151 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
2152 range_lob(pci_hole64
),
2153 range_upb(pci_hole64
));
2154 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
2155 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
2157 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
2159 AML_CACHEABLE
, AML_READ_WRITE
,
2160 0, entry
->base
, entry
->limit
,
2161 0, entry
->limit
- entry
->base
+ 1));
2165 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2166 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2167 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2169 aml_append(scope
, aml_name_decl("_CRS", crs
));
2171 /* reserve GPE0 block resources */
2172 dev
= aml_device("GPE0");
2173 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2174 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2175 /* device present, functioning, decoding, not shown in UI */
2176 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2177 crs
= aml_resource_template();
2179 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2181 aml_append(dev
, aml_name_decl("_CRS", crs
));
2182 aml_append(scope
, dev
);
2184 crs_range_set_free(&crs_range_set
);
2186 /* reserve PCIHP resources */
2187 if (pm
->pcihp_io_len
) {
2188 dev
= aml_device("PHPR");
2189 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2191 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2192 /* device present, functioning, decoding, not shown in UI */
2193 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2194 crs
= aml_resource_template();
2196 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2199 aml_append(dev
, aml_name_decl("_CRS", crs
));
2200 aml_append(scope
, dev
);
2202 aml_append(dsdt
, scope
);
2204 /* create S3_ / S4_ / S5_ packages if necessary */
2205 scope
= aml_scope("\\");
2206 if (!pm
->s3_disabled
) {
2207 pkg
= aml_package(4);
2208 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2209 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2210 aml_append(pkg
, aml_int(0)); /* reserved */
2211 aml_append(pkg
, aml_int(0)); /* reserved */
2212 aml_append(scope
, aml_name_decl("_S3", pkg
));
2215 if (!pm
->s4_disabled
) {
2216 pkg
= aml_package(4);
2217 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2218 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2219 aml_append(pkg
, aml_int(pm
->s4_val
));
2220 aml_append(pkg
, aml_int(0)); /* reserved */
2221 aml_append(pkg
, aml_int(0)); /* reserved */
2222 aml_append(scope
, aml_name_decl("_S4", pkg
));
2225 pkg
= aml_package(4);
2226 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2227 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2228 aml_append(pkg
, aml_int(0)); /* reserved */
2229 aml_append(pkg
, aml_int(0)); /* reserved */
2230 aml_append(scope
, aml_name_decl("_S5", pkg
));
2231 aml_append(dsdt
, scope
);
2233 /* create fw_cfg node, unconditionally */
2235 /* when using port i/o, the 8-bit data register *always* overlaps
2236 * with half of the 16-bit control register. Hence, the total size
2237 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2238 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2239 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2240 "dma_enabled", NULL
) ?
2241 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2244 scope
= aml_scope("\\_SB.PCI0");
2245 dev
= aml_device("FWCF");
2247 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2249 /* device present, functioning, decoding, not shown in UI */
2250 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2252 crs
= aml_resource_template();
2254 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2256 aml_append(dev
, aml_name_decl("_CRS", crs
));
2258 aml_append(scope
, dev
);
2259 aml_append(dsdt
, scope
);
2262 if (misc
->applesmc_io_base
) {
2263 scope
= aml_scope("\\_SB.PCI0.ISA");
2264 dev
= aml_device("SMC");
2266 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2267 /* device present, functioning, decoding, not shown in UI */
2268 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2270 crs
= aml_resource_template();
2272 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2273 0x01, APPLESMC_MAX_DATA_LENGTH
)
2275 aml_append(crs
, aml_irq_no_flags(6));
2276 aml_append(dev
, aml_name_decl("_CRS", crs
));
2278 aml_append(scope
, dev
);
2279 aml_append(dsdt
, scope
);
2282 if (misc
->pvpanic_port
) {
2283 scope
= aml_scope("\\_SB.PCI0.ISA");
2285 dev
= aml_device("PEVT");
2286 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2288 crs
= aml_resource_template();
2290 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2292 aml_append(dev
, aml_name_decl("_CRS", crs
));
2294 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2295 aml_int(misc
->pvpanic_port
), 1));
2296 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2297 aml_append(field
, aml_named_field("PEPT", 8));
2298 aml_append(dev
, field
);
2300 /* device present, functioning, decoding, shown in UI */
2301 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2303 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2304 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2305 aml_append(method
, aml_return(aml_local(0)));
2306 aml_append(dev
, method
);
2308 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2309 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2310 aml_append(dev
, method
);
2312 aml_append(scope
, dev
);
2313 aml_append(dsdt
, scope
);
2316 sb_scope
= aml_scope("\\_SB");
2318 build_memory_devices(sb_scope
, nr_mem
, pm
->mem_hp_io_base
,
2325 pci_host
= acpi_get_i386_pci_host();
2327 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2331 Aml
*scope
= aml_scope("PCI0");
2332 /* Scan all PCI buses. Generate tables to support hotplug. */
2333 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2335 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2336 dev
= aml_device("ISA.TPM");
2337 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2338 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2339 crs
= aml_resource_template();
2340 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2341 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2343 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2344 Rewrite to take IRQ from TPM device model and
2345 fix default IRQ value there to use some unused IRQ
2347 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2348 aml_append(dev
, aml_name_decl("_CRS", crs
));
2349 aml_append(scope
, dev
);
2352 aml_append(sb_scope
, scope
);
2355 aml_append(dsdt
, sb_scope
);
2358 /* copy AML table into ACPI tables blob and patch header there */
2359 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2360 build_header(linker
, table_data
,
2361 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2362 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2363 free_aml_allocator();
2367 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2371 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2372 /* Note timer_block_id value must be kept in sync with value advertised by
2375 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2376 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2377 build_header(linker
, table_data
,
2378 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2382 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2384 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2385 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2386 unsigned log_addr_offset
=
2387 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2389 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2390 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2391 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2393 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2394 false /* high memory */);
2396 /* log area start address to be filled by Guest linker */
2397 bios_linker_loader_add_pointer(linker
,
2398 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2399 ACPI_BUILD_TPMLOG_FILE
, 0);
2401 build_header(linker
, table_data
,
2402 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2406 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
)
2408 Acpi20TPM2
*tpm2_ptr
;
2410 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2412 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2413 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2414 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2416 build_header(linker
, table_data
,
2417 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2421 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2423 AcpiSystemResourceAffinityTable
*srat
;
2424 AcpiSratMemoryAffinity
*numamem
;
2427 int srat_start
, numa_start
, slots
;
2428 uint64_t mem_len
, mem_base
, next_base
;
2429 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2430 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2431 PCMachineState
*pcms
= PC_MACHINE(machine
);
2432 ram_addr_t hotplugabble_address_space_size
=
2433 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2436 srat_start
= table_data
->len
;
2438 srat
= acpi_data_push(table_data
, sizeof *srat
);
2439 srat
->reserved1
= cpu_to_le32(1);
2441 for (i
= 0; i
< apic_ids
->len
; i
++) {
2442 int j
= numa_get_node_for_cpu(i
);
2443 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
2445 if (apic_id
< 255) {
2446 AcpiSratProcessorAffinity
*core
;
2448 core
= acpi_data_push(table_data
, sizeof *core
);
2449 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2450 core
->length
= sizeof(*core
);
2451 core
->local_apic_id
= apic_id
;
2452 if (j
< nb_numa_nodes
) {
2453 core
->proximity_lo
= j
;
2455 memset(core
->proximity_hi
, 0, 3);
2456 core
->local_sapic_eid
= 0;
2457 core
->flags
= cpu_to_le32(1);
2459 AcpiSratProcessorX2ApicAffinity
*core
;
2461 core
= acpi_data_push(table_data
, sizeof *core
);
2462 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
2463 core
->length
= sizeof(*core
);
2464 core
->x2apic_id
= cpu_to_le32(apic_id
);
2465 if (j
< nb_numa_nodes
) {
2466 core
->proximity_domain
= cpu_to_le32(j
);
2468 core
->flags
= cpu_to_le32(1);
2473 /* the memory map is a bit tricky, it contains at least one hole
2474 * from 640k-1M and possibly another one from 3.5G-4G.
2477 numa_start
= table_data
->len
;
2479 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2480 build_srat_memory(numamem
, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED
);
2481 next_base
= 1024 * 1024;
2482 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2483 mem_base
= next_base
;
2484 mem_len
= pcms
->node_mem
[i
- 1];
2486 mem_len
-= 1024 * 1024;
2488 next_base
= mem_base
+ mem_len
;
2490 /* Cut out the ACPI_PCI hole */
2491 if (mem_base
<= pcms
->below_4g_mem_size
&&
2492 next_base
> pcms
->below_4g_mem_size
) {
2493 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2495 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2496 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2497 MEM_AFFINITY_ENABLED
);
2499 mem_base
= 1ULL << 32;
2500 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2501 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2503 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2504 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2505 MEM_AFFINITY_ENABLED
);
2507 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2508 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2509 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2510 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2514 * Entry is required for Windows to enable memory hotplug in OS.
2515 * Memory devices may override proximity set by this entry,
2516 * providing _PXM method if necessary.
2518 if (hotplugabble_address_space_size
) {
2519 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2520 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2521 hotplugabble_address_space_size
, 0,
2522 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2525 build_header(linker
, table_data
,
2526 (void *)(table_data
->data
+ srat_start
),
2528 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2533 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2535 AcpiTableMcfg
*mcfg
;
2537 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2539 mcfg
= acpi_data_push(table_data
, len
);
2540 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2541 /* Only a single allocation so no need to play with segments */
2542 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2543 mcfg
->allocation
[0].start_bus_number
= 0;
2544 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2546 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2547 * To avoid table size changes (which create migration issues),
2548 * always create the table even if there are no allocations,
2549 * but set the signature to a reserved value in this case.
2550 * ACPI spec requires OSPMs to ignore such tables.
2552 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2553 /* Reserved signature: ignored by OSPM */
2558 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2562 * VT-d spec 8.1 DMA Remapping Reporting Structure
2563 * (version Oct. 2014 or later)
2566 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2568 int dmar_start
= table_data
->len
;
2570 AcpiTableDmar
*dmar
;
2571 AcpiDmarHardwareUnit
*drhd
;
2572 uint8_t dmar_flags
= 0;
2573 X86IOMMUState
*iommu
= x86_iommu_get_default();
2574 AcpiDmarDeviceScope
*scope
= NULL
;
2575 /* Root complex IOAPIC use one path[0] only */
2576 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2579 if (iommu
->intr_supported
) {
2580 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2583 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2584 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2585 dmar
->flags
= dmar_flags
;
2587 /* DMAR Remapping Hardware Unit Definition structure */
2588 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2589 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2590 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2591 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2592 drhd
->pci_segment
= cpu_to_le16(0);
2593 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2595 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2596 * 8.3.1 (version Oct. 2014 or later). */
2597 scope
= &drhd
->scope
[0];
2598 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2599 scope
->length
= ioapic_scope_size
;
2600 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2601 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2602 scope
->path
[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC
);
2604 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2605 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2608 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2609 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2612 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2614 int iommu_start
= table_data
->len
;
2615 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2618 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2619 /* IVinfo - IO virtualization information common to all
2620 * IOMMU units in a system
2622 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2624 build_append_int_noprefix(table_data
, 0, 8);
2626 /* IVHD definition - type 10h */
2627 build_append_int_noprefix(table_data
, 0x10, 1);
2628 /* virtualization flags */
2629 build_append_int_noprefix(table_data
,
2630 (1UL << 0) | /* HtTunEn */
2631 (1UL << 4) | /* iotblSup */
2632 (1UL << 6) | /* PrefSup */
2633 (1UL << 7), /* PPRSup */
2636 build_append_int_noprefix(table_data
, 0x24, 2);
2638 build_append_int_noprefix(table_data
, s
->devid
, 2);
2639 /* Capability offset */
2640 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2641 /* IOMMU base address */
2642 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2643 /* PCI Segment Group */
2644 build_append_int_noprefix(table_data
, 0, 2);
2646 build_append_int_noprefix(table_data
, 0, 2);
2647 /* IOMMU Feature Reporting */
2648 build_append_int_noprefix(table_data
,
2649 (48UL << 30) | /* HATS */
2650 (48UL << 28) | /* GATS */
2651 (1UL << 2), /* GTSup */
2654 * Type 1 device entry reporting all devices
2655 * These are 4-byte device entries currently reporting the range of
2656 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2658 build_append_int_noprefix(table_data
, 0x0000001, 4);
2660 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2661 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2665 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2667 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2668 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2669 unsigned rsdt_pa_offset
=
2670 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2672 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2673 true /* fseg memory */);
2675 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2676 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2677 /* Address to be filled by Guest linker */
2678 bios_linker_loader_add_pointer(linker
,
2679 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2680 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2682 /* Checksum to be filled by Guest linker */
2683 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2684 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2685 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2691 struct AcpiBuildState
{
2692 /* Copy of table in RAM (for patching). */
2693 MemoryRegion
*table_mr
;
2694 /* Is table patched? */
2697 MemoryRegion
*rsdp_mr
;
2698 MemoryRegion
*linker_mr
;
2701 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2706 pci_host
= acpi_get_i386_pci_host();
2709 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2713 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2716 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2718 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2724 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2726 PCMachineState
*pcms
= PC_MACHINE(machine
);
2727 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2728 GArray
*table_offsets
;
2729 unsigned facs
, dsdt
, rsdt
, fadt
;
2733 Range pci_hole
, pci_hole64
;
2736 GArray
*tables_blob
= tables
->table_data
;
2737 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2739 acpi_get_pm_info(&pm
);
2740 acpi_get_misc_info(&misc
);
2741 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2742 acpi_get_slic_oem(&slic_oem
);
2744 table_offsets
= g_array_new(false, true /* clear */,
2746 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2748 bios_linker_loader_alloc(tables
->linker
,
2749 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2750 64 /* Ensure FACS is aligned */,
2751 false /* high memory */);
2754 * FACS is pointed to by FADT.
2755 * We place it first since it's the only table that has alignment
2758 facs
= tables_blob
->len
;
2759 build_facs(tables_blob
, tables
->linker
);
2761 /* DSDT is pointed to by FADT */
2762 dsdt
= tables_blob
->len
;
2763 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2764 &pci_hole
, &pci_hole64
, machine
);
2766 /* Count the size of the DSDT and SSDT, we will need it for legacy
2767 * sizing of ACPI tables.
2769 aml_len
+= tables_blob
->len
- dsdt
;
2771 /* ACPI tables pointed to by RSDT */
2772 fadt
= tables_blob
->len
;
2773 acpi_add_table(table_offsets
, tables_blob
);
2774 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2775 slic_oem
.id
, slic_oem
.table_id
);
2776 aml_len
+= tables_blob
->len
- fadt
;
2778 acpi_add_table(table_offsets
, tables_blob
);
2779 build_madt(tables_blob
, tables
->linker
, pcms
);
2781 if (misc
.has_hpet
) {
2782 acpi_add_table(table_offsets
, tables_blob
);
2783 build_hpet(tables_blob
, tables
->linker
);
2785 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2786 acpi_add_table(table_offsets
, tables_blob
);
2787 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2789 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2790 acpi_add_table(table_offsets
, tables_blob
);
2791 build_tpm2(tables_blob
, tables
->linker
);
2794 if (pcms
->numa_nodes
) {
2795 acpi_add_table(table_offsets
, tables_blob
);
2796 build_srat(tables_blob
, tables
->linker
, machine
);
2798 if (acpi_get_mcfg(&mcfg
)) {
2799 acpi_add_table(table_offsets
, tables_blob
);
2800 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2802 if (x86_iommu_get_default()) {
2803 IommuType IOMMUType
= x86_iommu_get_type();
2804 if (IOMMUType
== TYPE_AMD
) {
2805 acpi_add_table(table_offsets
, tables_blob
);
2806 build_amd_iommu(tables_blob
, tables
->linker
);
2807 } else if (IOMMUType
== TYPE_INTEL
) {
2808 acpi_add_table(table_offsets
, tables_blob
);
2809 build_dmar_q35(tables_blob
, tables
->linker
);
2812 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2813 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2814 &pcms
->acpi_nvdimm_state
, machine
->ram_slots
);
2817 /* Add tables supplied by user (if any) */
2818 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2819 unsigned len
= acpi_table_len(u
);
2821 acpi_add_table(table_offsets
, tables_blob
);
2822 g_array_append_vals(tables_blob
, u
, len
);
2825 /* RSDT is pointed to by RSDP */
2826 rsdt
= tables_blob
->len
;
2827 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2828 slic_oem
.id
, slic_oem
.table_id
);
2830 /* RSDP is in FSEG memory, so allocate it separately */
2831 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2833 /* We'll expose it all to Guest so we want to reduce
2834 * chance of size changes.
2836 * We used to align the tables to 4k, but of course this would
2837 * too simple to be enough. 4k turned out to be too small an
2838 * alignment very soon, and in fact it is almost impossible to
2839 * keep the table size stable for all (max_cpus, max_memory_slots)
2840 * combinations. So the table size is always 64k for pc-i440fx-2.1
2841 * and we give an error if the table grows beyond that limit.
2843 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2844 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2845 * than 2.0 and we can always pad the smaller tables with zeros. We can
2846 * then use the exact size of the 2.0 tables.
2848 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2850 if (pcmc
->legacy_acpi_table_size
) {
2851 /* Subtracting aml_len gives the size of fixed tables. Then add the
2852 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2854 int legacy_aml_len
=
2855 pcmc
->legacy_acpi_table_size
+
2856 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
2857 int legacy_table_size
=
2858 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2859 ACPI_BUILD_ALIGN_SIZE
);
2860 if (tables_blob
->len
> legacy_table_size
) {
2861 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2862 error_report("Warning: migration may not work.");
2864 g_array_set_size(tables_blob
, legacy_table_size
);
2866 /* Make sure we have a buffer in case we need to resize the tables. */
2867 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2868 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2869 error_report("Warning: ACPI tables are larger than 64k.");
2870 error_report("Warning: migration may not work.");
2871 error_report("Warning: please remove CPUs, NUMA nodes, "
2872 "memory slots or PCI bridges.");
2874 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2877 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2879 /* Cleanup memory that's no longer used. */
2880 g_array_free(table_offsets
, true);
2883 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2885 uint32_t size
= acpi_data_len(data
);
2887 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2888 memory_region_ram_resize(mr
, size
, &error_abort
);
2890 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2891 memory_region_set_dirty(mr
, 0, size
);
2894 static void acpi_build_update(void *build_opaque
)
2896 AcpiBuildState
*build_state
= build_opaque
;
2897 AcpiBuildTables tables
;
2899 /* No state to update or already patched? Nothing to do. */
2900 if (!build_state
|| build_state
->patched
) {
2903 build_state
->patched
= 1;
2905 acpi_build_tables_init(&tables
);
2907 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2909 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2911 if (build_state
->rsdp
) {
2912 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2914 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2917 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2918 acpi_build_tables_cleanup(&tables
, true);
2921 static void acpi_build_reset(void *build_opaque
)
2923 AcpiBuildState
*build_state
= build_opaque
;
2924 build_state
->patched
= 0;
2927 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2928 GArray
*blob
, const char *name
,
2931 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2932 name
, acpi_build_update
, build_state
);
2935 static const VMStateDescription vmstate_acpi_build
= {
2936 .name
= "acpi_build",
2938 .minimum_version_id
= 1,
2939 .fields
= (VMStateField
[]) {
2940 VMSTATE_UINT8(patched
, AcpiBuildState
),
2941 VMSTATE_END_OF_LIST()
2945 void acpi_setup(void)
2947 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2948 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2949 AcpiBuildTables tables
;
2950 AcpiBuildState
*build_state
;
2952 if (!pcms
->fw_cfg
) {
2953 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2957 if (!pcmc
->has_acpi_build
) {
2958 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2962 if (!acpi_enabled
) {
2963 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2967 build_state
= g_malloc0(sizeof *build_state
);
2969 acpi_set_pci_info();
2971 acpi_build_tables_init(&tables
);
2972 acpi_build(&tables
, MACHINE(pcms
));
2974 /* Now expose it all to Guest */
2975 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2976 ACPI_BUILD_TABLE_FILE
,
2977 ACPI_BUILD_TABLE_MAX_SIZE
);
2978 assert(build_state
->table_mr
!= NULL
);
2980 build_state
->linker_mr
=
2981 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2982 "etc/table-loader", 0);
2984 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2985 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2987 if (!pcmc
->rsdp_in_ram
) {
2989 * Keep for compatibility with old machine types.
2990 * Though RSDP is small, its contents isn't immutable, so
2991 * we'll update it along with the rest of tables on guest access.
2993 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2995 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2996 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2997 acpi_build_update
, build_state
,
2998 build_state
->rsdp
, rsdp_size
);
2999 build_state
->rsdp_mr
= NULL
;
3001 build_state
->rsdp
= NULL
;
3002 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
3003 ACPI_BUILD_RSDP_FILE
, 0);
3006 qemu_register_reset(acpi_build_reset
, build_state
);
3007 acpi_build_reset(build_state
);
3008 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
3010 /* Cleanup tables but don't free the memory: we track it
3013 acpi_build_tables_cleanup(&tables
, false);