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Merge tag 'pull-lu-20241122' of https://gitlab.com/rth7680/qemu into staging
[qemu/kevin.git] / hw / i386 / acpi-build.c
blob9fcc2897b84a07fd7d49fab02def91ee6505e7ab
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/erst.h"
47 #include "hw/acpi/piix4.h"
48 #include "sysemu/tpm_backend.h"
49 #include "hw/rtc/mc146818rtc_regs.h"
50 #include "migration/vmstate.h"
51 #include "hw/mem/memory-device.h"
52 #include "hw/mem/nvdimm.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "hw/hyperv/vmbus-bridge.h"
56
57 /* Supported chipsets: */
58 #include "hw/southbridge/ich9.h"
59 #include "hw/acpi/pcihp.h"
60 #include "hw/i386/fw_cfg.h"
61 #include "hw/i386/pc.h"
62 #include "hw/pci/pci_bus.h"
63 #include "hw/pci-host/i440fx.h"
64 #include "hw/pci-host/q35.h"
65 #include "hw/i386/x86-iommu.h"
66
67 #include "hw/acpi/aml-build.h"
68 #include "hw/acpi/utils.h"
69 #include "hw/acpi/pci.h"
70 #include "hw/acpi/cxl.h"
71
72 #include "qom/qom-qobject.h"
73 #include "hw/i386/amd_iommu.h"
74 #include "hw/i386/intel_iommu.h"
75 #include "hw/virtio/virtio-iommu.h"
76
77 #include "hw/acpi/hmat.h"
78 #include "hw/acpi/viot.h"
79
80 #include CONFIG_DEVICES
81
82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
84 * a little bit, there should be plenty of free space since the DSDT
85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
86 */
87 #define ACPI_BUILD_ALIGN_SIZE 0x1000
88
89 #define ACPI_BUILD_TABLE_SIZE 0x20000
90
91 /* #define DEBUG_ACPI_BUILD */
92 #ifdef DEBUG_ACPI_BUILD
93 #define ACPI_BUILD_DPRINTF(fmt, ...) \
94 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
95 #else
96 #define ACPI_BUILD_DPRINTF(fmt, ...)
97 #endif
98
99 typedef struct AcpiPmInfo {
100 bool s3_disabled;
101 bool s4_disabled;
102 bool pcihp_bridge_en;
103 bool smi_on_cpuhp;
104 bool smi_on_cpu_unplug;
105 bool pcihp_root_en;
106 uint8_t s4_val;
107 AcpiFadtData fadt;
108 uint16_t cpu_hp_io_base;
109 uint16_t pcihp_io_base;
110 uint16_t pcihp_io_len;
111 } AcpiPmInfo;
112
113 typedef struct AcpiMiscInfo {
114 bool has_hpet;
115 #ifdef CONFIG_TPM
116 TPMVersion tpm_version;
117 #endif
118 } AcpiMiscInfo;
119
120 typedef struct FwCfgTPMConfig {
121 uint32_t tpmppi_address;
122 uint8_t tpm_version;
123 uint8_t tpmppi_version;
124 } QEMU_PACKED FwCfgTPMConfig;
125
126 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
127
128 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
129 .space_id = AML_AS_SYSTEM_IO,
130 .address = NVDIMM_ACPI_IO_BASE,
131 .bit_width = NVDIMM_ACPI_IO_LEN << 3
132 };
133
134 static void init_common_fadt_data(MachineState *ms, Object *o,
135 AcpiFadtData *data)
136 {
137 X86MachineState *x86ms = X86_MACHINE(ms);
138 /*
139 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
140 * behavior for compatibility irrelevant to smm_enabled, which doesn't
141 * comforms to ACPI spec.
142 */
143 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
144 true : x86_machine_is_smm_enabled(x86ms);
145 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
146 AmlAddressSpace as = AML_AS_SYSTEM_IO;
147 AcpiFadtData fadt = {
148 .rev = 3,
149 .flags =
150 (1 << ACPI_FADT_F_WBINVD) |
151 (1 << ACPI_FADT_F_PROC_C1) |
152 (1 << ACPI_FADT_F_SLP_BUTTON) |
153 (1 << ACPI_FADT_F_RTC_S4) |
154 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
155 /* APIC destination mode ("Flat Logical") has an upper limit of 8
156 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
157 * used
158 */
159 ((ms->smp.max_cpus > 8) ?
160 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
161 .int_model = 1 /* Multiple APIC */,
162 .rtc_century = RTC_CENTURY,
163 .plvl2_lat = 0xfff /* C2 state not supported */,
164 .plvl3_lat = 0xfff /* C3 state not supported */,
165 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
166 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
167 .acpi_enable_cmd =
168 smm_enabled ?
169 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
170 0,
171 .acpi_disable_cmd =
172 smm_enabled ?
173 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
174 0,
175 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
176 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
177 .address = io + 0x04 },
178 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
179 .gpe0_blk = { .space_id = as, .bit_width =
180 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
181 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
182 },
183 };
184
185 /*
186 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
187 * Flags, bit offset 1 - 8042.
188 */
189 fadt.iapc_boot_arch = iapc_boot_arch_8042();
190
191 *data = fadt;
192 }
193
194 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
195 {
196 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL);
197 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL);
198 Object *obj = piix ? piix : lpc;
199 QObject *o;
200 pm->cpu_hp_io_base = 0;
201 pm->pcihp_io_base = 0;
202 pm->pcihp_io_len = 0;
203 pm->smi_on_cpuhp = false;
204 pm->smi_on_cpu_unplug = false;
205
206 assert(obj);
207 init_common_fadt_data(machine, obj, &pm->fadt);
208 if (piix) {
209 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
210 pm->fadt.rev = 1;
211 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
212 }
213 if (lpc) {
214 uint64_t smi_features = object_property_get_uint(lpc,
215 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
216 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
217 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
218 pm->fadt.reset_reg = r;
219 pm->fadt.reset_val = 0xf;
220 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
221 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
222 pm->smi_on_cpuhp =
223 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
224 pm->smi_on_cpu_unplug =
225 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
226 }
227 pm->pcihp_io_base =
228 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
229 pm->pcihp_io_len =
230 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
231
232 /* Fill in optional s3/s4 related properties */
233 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
234 if (o) {
235 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
236 } else {
237 pm->s3_disabled = false;
238 }
239 qobject_unref(o);
240 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
241 if (o) {
242 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
243 } else {
244 pm->s4_disabled = false;
245 }
246 qobject_unref(o);
247 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
248 if (o) {
249 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
250 } else {
251 pm->s4_val = false;
252 }
253 qobject_unref(o);
254
255 pm->pcihp_bridge_en =
256 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
257 NULL);
258 pm->pcihp_root_en =
259 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
260 NULL);
261 }
262
263 static void acpi_get_misc_info(AcpiMiscInfo *info)
264 {
265 info->has_hpet = hpet_find();
266 #ifdef CONFIG_TPM
267 info->tpm_version = tpm_get_version(tpm_find());
268 #endif
269 }
270
271 /*
272 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
273 * On i386 arch we only have two pci hosts, so we can look only for them.
274 */
275 Object *acpi_get_i386_pci_host(void)
276 {
277 PCIHostState *host;
278
279 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
280 if (!host) {
281 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
282 }
283
284 return OBJECT(host);
285 }
286
287 static void acpi_get_pci_holes(Range *hole, Range *hole64)
288 {
289 Object *pci_host;
290
291 pci_host = acpi_get_i386_pci_host();
292
293 if (!pci_host) {
294 return;
295 }
296
297 range_set_bounds1(hole,
298 object_property_get_uint(pci_host,
299 PCI_HOST_PROP_PCI_HOLE_START,
300 NULL),
301 object_property_get_uint(pci_host,
302 PCI_HOST_PROP_PCI_HOLE_END,
303 NULL));
304 range_set_bounds1(hole64,
305 object_property_get_uint(pci_host,
306 PCI_HOST_PROP_PCI_HOLE64_START,
307 NULL),
308 object_property_get_uint(pci_host,
309 PCI_HOST_PROP_PCI_HOLE64_END,
310 NULL));
311 }
312
313 static void acpi_align_size(GArray *blob, unsigned align)
314 {
315 /* Align size to multiple of given size. This reduces the chance
316 * we need to change size in the future (breaking cross version migration).
317 */
318 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
319 }
320
321 /*
322 * ACPI spec 1.0b,
323 * 5.2.6 Firmware ACPI Control Structure
324 */
325 static void
326 build_facs(GArray *table_data)
327 {
328 const char *sig = "FACS";
329 const uint8_t reserved[40] = {};
330
331 g_array_append_vals(table_data, sig, 4); /* Signature */
332 build_append_int_noprefix(table_data, 64, 4); /* Length */
333 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
334 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
335 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
336 build_append_int_noprefix(table_data, 0, 4); /* Flags */
337 g_array_append_vals(table_data, reserved, 40); /* Reserved */
338 }
339
340 Aml *aml_pci_device_dsm(void)
341 {
342 Aml *method;
343
344 method = aml_method("_DSM", 4, AML_SERIALIZED);
345 {
346 Aml *params = aml_local(0);
347 Aml *pkg = aml_package(2);
348 aml_append(pkg, aml_int(0));
349 aml_append(pkg, aml_int(0));
350 aml_append(method, aml_store(pkg, params));
351 aml_append(method,
352 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0))));
353 aml_append(method,
354 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1))));
355 aml_append(method,
356 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
357 aml_arg(2), aml_arg(3), params))
358 );
359 }
360 return method;
361 }
362
363 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar)
364 {
365 Aml *UUID, *ifctx1;
366 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
367
368 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar));
369 /*
370 * PCI Firmware Specification 3.1
371 * 4.6. _DSM Definitions for PCI
372 */
373 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
374 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
375 {
376 /* call is for unsupported UUID, bail out */
377 aml_append(ifctx1, aml_return(retvar));
378 }
379 aml_append(ctx, ifctx1);
380
381 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2)));
382 {
383 /* call is for unsupported REV, bail out */
384 aml_append(ifctx1, aml_return(retvar));
385 }
386 aml_append(ctx, ifctx1);
387 }
388
389 static Aml *aml_pci_edsm(void)
390 {
391 Aml *method, *ifctx;
392 Aml *zero = aml_int(0);
393 Aml *func = aml_arg(2);
394 Aml *ret = aml_local(0);
395 Aml *aidx = aml_local(1);
396 Aml *params = aml_arg(4);
397
398 method = aml_method("EDSM", 5, AML_SERIALIZED);
399
400 /* get supported functions */
401 ifctx = aml_if(aml_equal(func, zero));
402 {
403 /* 1: have supported functions */
404 /* 7: support for function 7 */
405 const uint8_t caps = 1 | BIT(7);
406 build_append_pci_dsm_func0_common(ifctx, ret);
407 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero)));
408 aml_append(ifctx, aml_return(ret));
409 }
410 aml_append(method, ifctx);
411
412 /* handle specific functions requests */
413 /*
414 * PCI Firmware Specification 3.1
415 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
416 * Operating Systems
417 */
418 ifctx = aml_if(aml_equal(func, aml_int(7)));
419 {
420 Aml *pkg = aml_package(2);
421 aml_append(pkg, zero);
422 /* optional, if not impl. should return null string */
423 aml_append(pkg, aml_string("%s", ""));
424 aml_append(ifctx, aml_store(pkg, ret));
425
426 /*
427 * IASL is fine when initializing Package with computational data,
428 * however it makes guest unhappy /it fails to process such AML/.
429 * So use runtime assignment to set acpi-index after initializer
430 * to make OSPM happy.
431 */
432 aml_append(ifctx,
433 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx));
434 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero)));
435 aml_append(ifctx, aml_return(ret));
436 }
437 aml_append(method, ifctx);
438
439 return method;
440 }
441
442 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev)
443 {
444 Aml *method;
445
446 g_assert(pdev->acpi_index != 0);
447 method = aml_method("_DSM", 4, AML_SERIALIZED);
448 {
449 Aml *params = aml_local(0);
450 Aml *pkg = aml_package(1);
451 aml_append(pkg, aml_int(pdev->acpi_index));
452 aml_append(method, aml_store(pkg, params));
453 aml_append(method,
454 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
455 aml_arg(2), aml_arg(3), params))
456 );
457 }
458 return method;
459 }
460
461 static void build_append_pcihp_notify_entry(Aml *method, int slot)
462 {
463 Aml *if_ctx;
464 int32_t devfn = PCI_DEVFN(slot, 0);
465
466 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
467 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
468 aml_append(method, if_ctx);
469 }
470
471 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
472 {
473 const PCIDevice *pdev = bus->devices[devfn];
474
475 if (PCI_FUNC(devfn)) {
476 if (IS_PCI_BRIDGE(pdev)) {
477 /*
478 * Ignore only hotplugged PCI bridges on !0 functions, but
479 * allow describing cold plugged bridges on all functions
480 */
481 if (DEVICE(pdev)->hotplugged) {
482 return true;
483 }
484 }
485 }
486 return false;
487 }
488
489 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
490 {
491 PCIDevice *pdev = bus->devices[devfn];
492 if (pdev) {
493 return is_devfn_ignored_generic(devfn, bus) ||
494 !DEVICE_GET_CLASS(pdev)->hotpluggable ||
495 /* Cold plugged bridges aren't themselves hot-pluggable */
496 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
497 } else { /* non populated slots */
498 /*
499 * hotplug is supported only for non-multifunction device
500 * so generate device description only for function 0
501 */
502 if (PCI_FUNC(devfn) ||
503 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
504 return true;
505 }
506 }
507 return false;
508 }
509
510 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus)
511 {
512 int devfn;
513 Aml *dev, *notify_method = NULL, *method;
514 QObject *bsel = object_property_get_qobject(OBJECT(bus),
515 ACPI_PCIHP_PROP_BSEL, NULL);
516 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
517 qobject_unref(bsel);
518
519 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
520 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
521
522 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
523 int slot = PCI_SLOT(devfn);
524 int adr = slot << 16 | PCI_FUNC(devfn);
525
526 if (is_devfn_ignored_hotplug(devfn, bus)) {
527 continue;
528 }
529
530 if (bus->devices[devfn]) {
531 dev = aml_scope("S%.02X", devfn);
532 } else {
533 dev = aml_device("S%.02X", devfn);
534 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
535 }
536
537 /*
538 * Can't declare _SUN here for every device as it changes 'slot'
539 * enumeration order in linux kernel, so use another variable for it
540 */
541 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
542 aml_append(dev, aml_pci_device_dsm());
543
544 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
545 /* add _EJ0 to make slot hotpluggable */
546 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
547 aml_append(method,
548 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
549 );
550 aml_append(dev, method);
551
552 build_append_pcihp_notify_entry(notify_method, slot);
553
554 /* device descriptor has been composed, add it into parent context */
555 aml_append(parent_scope, dev);
556 }
557 aml_append(parent_scope, notify_method);
558 }
559
560 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
561 {
562 int devfn;
563 Aml *dev;
564
565 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
566 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
567 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
568 PCIDevice *pdev = bus->devices[devfn];
569
570 if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
571 continue;
572 }
573
574 /* start to compose PCI device descriptor */
575 dev = aml_device("S%.02X", devfn);
576 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
577
578 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
579 /* add _DSM if device has acpi-index set */
580 if (pdev->acpi_index &&
581 !object_property_get_bool(OBJECT(pdev), "hotpluggable",
582 &error_abort)) {
583 aml_append(dev, aml_pci_static_endpoint_dsm(pdev));
584 }
585
586 /* device descriptor has been composed, add it into parent context */
587 aml_append(parent_scope, dev);
588 }
589 }
590
591 static bool build_append_notfication_callback(Aml *parent_scope,
592 const PCIBus *bus)
593 {
594 Aml *method;
595 PCIBus *sec;
596 QObject *bsel;
597 int nr_notifiers = 0;
598 GQueue *pcnt_bus_list = g_queue_new();
599
600 QLIST_FOREACH(sec, &bus->child, sibling) {
601 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
602 if (pci_bus_is_root(sec)) {
603 continue;
604 }
605 nr_notifiers = nr_notifiers +
606 build_append_notfication_callback(br_scope, sec);
607 /*
608 * add new child scope to parent
609 * and keep track of bus that have PCNT,
610 * bus list is used later to call children PCNTs from this level PCNT
611 */
612 if (nr_notifiers) {
613 g_queue_push_tail(pcnt_bus_list, sec);
614 aml_append(parent_scope, br_scope);
615 }
616 }
617
618 /*
619 * Append PCNT method to notify about events on local and child buses.
620 * ps: hostbridge might not have hotplug (bsel) enabled but might have
621 * child bridges that do have bsel.
622 */
623 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
624
625 /* If bus supports hotplug select it and notify about local events */
626 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
627 if (bsel) {
628 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
629
630 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
631 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
632 aml_int(1))); /* Device Check */
633 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
634 aml_int(3))); /* Eject Request */
635 nr_notifiers++;
636 }
637
638 /* Notify about child bus events in any case */
639 while ((sec = g_queue_pop_head(pcnt_bus_list))) {
640 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
641 }
642
643 aml_append(parent_scope, method);
644 qobject_unref(bsel);
645 g_queue_free(pcnt_bus_list);
646 return !!nr_notifiers;
647 }
648
649 static Aml *aml_pci_pdsm(void)
650 {
651 Aml *method, *ifctx, *ifctx1;
652 Aml *ret = aml_local(0);
653 Aml *caps = aml_local(1);
654 Aml *acpi_index = aml_local(2);
655 Aml *zero = aml_int(0);
656 Aml *one = aml_int(1);
657 Aml *func = aml_arg(2);
658 Aml *params = aml_arg(4);
659 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
660 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
661
662 method = aml_method("PDSM", 5, AML_SERIALIZED);
663
664 /* get supported functions */
665 ifctx = aml_if(aml_equal(func, zero));
666 {
667 build_append_pci_dsm_func0_common(ifctx, ret);
668
669 aml_append(ifctx, aml_store(zero, caps));
670 aml_append(ifctx,
671 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
672 /*
673 * advertise function 7 if device has acpi-index
674 * acpi_index values:
675 * 0: not present (default value)
676 * FFFFFFFF: not supported (old QEMU without PIDX reg)
677 * other: device's acpi-index
678 */
679 ifctx1 = aml_if(aml_lnot(
680 aml_or(aml_equal(acpi_index, zero),
681 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
682 ));
683 {
684 /* have supported functions */
685 aml_append(ifctx1, aml_or(caps, one, caps));
686 /* support for function 7 */
687 aml_append(ifctx1,
688 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
689 }
690 aml_append(ifctx, ifctx1);
691
692 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
693 aml_append(ifctx, aml_return(ret));
694 }
695 aml_append(method, ifctx);
696
697 /* handle specific functions requests */
698 /*
699 * PCI Firmware Specification 3.1
700 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
701 * Operating Systems
702 */
703 ifctx = aml_if(aml_equal(func, aml_int(7)));
704 {
705 Aml *pkg = aml_package(2);
706
707 aml_append(pkg, zero);
708 /*
709 * optional, if not impl. should return null string
710 */
711 aml_append(pkg, aml_string("%s", ""));
712 aml_append(ifctx, aml_store(pkg, ret));
713
714 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
715 /*
716 * update acpi-index to actual value
717 */
718 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
719 aml_append(ifctx, aml_return(ret));
720 }
721
722 aml_append(method, ifctx);
723 return method;
724 }
725
726 /*
727 * build_prt - Define interrupt routing rules
728 *
729 * Returns an array of 128 routes, one for each device,
730 * based on device location.
731 * The main goal is to equally distribute the interrupts
732 * over the 4 existing ACPI links (works only for i440fx).
733 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]".
734 *
735 */
736 static Aml *build_prt(bool is_pci0_prt)
737 {
738 const int nroutes = 128;
739 Aml *rt_pkg, *method;
740 int pin;
741
742 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
743 assert(nroutes < 256);
744 rt_pkg = aml_package(nroutes);
745
746 for (pin = 0; pin < nroutes; pin++) {
747 Aml *pkg = aml_package(4);
748 int slot = pin >> 2;
749
750 aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
751 aml_append(pkg, aml_int(pin & 3));
752 /* device 1 is the power-management device, needs SCI */
753 if (is_pci0_prt && pin == 4) {
754 aml_append(pkg, aml_name("%s", "LNKS"));
755 } else {
756 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"};
757 int hash = (slot + pin) & 3;
758 aml_append(pkg, aml_name("%s", link_name[hash]));
759 }
760 aml_append(pkg, aml_int(0));
761 aml_append(rt_pkg, pkg);
762 }
763
764 aml_append(method, aml_return(rt_pkg));
765
766 return method;
767 }
768
769 static void build_hpet_aml(Aml *table)
770 {
771 Aml *crs;
772 Aml *field;
773 Aml *method;
774 Aml *if_ctx;
775 Aml *scope = aml_scope("_SB");
776 Aml *dev = aml_device("HPET");
777 Aml *zero = aml_int(0);
778 Aml *id = aml_local(0);
779 Aml *period = aml_local(1);
780
781 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
782 aml_append(dev, aml_name_decl("_UID", zero));
783
784 aml_append(dev,
785 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
786 HPET_LEN));
787 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
788 aml_append(field, aml_named_field("VEND", 32));
789 aml_append(field, aml_named_field("PRD", 32));
790 aml_append(dev, field);
791
792 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
793 aml_append(method, aml_store(aml_name("VEND"), id));
794 aml_append(method, aml_store(aml_name("PRD"), period));
795 aml_append(method, aml_shiftright(id, aml_int(16), id));
796 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
797 aml_equal(id, aml_int(0xffff))));
798 {
799 aml_append(if_ctx, aml_return(zero));
800 }
801 aml_append(method, if_ctx);
802
803 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
804 aml_lgreater(period, aml_int(100000000))));
805 {
806 aml_append(if_ctx, aml_return(zero));
807 }
808 aml_append(method, if_ctx);
809
810 aml_append(method, aml_return(aml_int(0x0F)));
811 aml_append(dev, method);
812
813 crs = aml_resource_template();
814 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
815 aml_append(dev, aml_name_decl("_CRS", crs));
816
817 aml_append(scope, dev);
818 aml_append(table, scope);
819 }
820
821 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
822 {
823 Aml *dev;
824 Aml *method;
825 Aml *crs;
826
827 dev = aml_device("VMBS");
828 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
829 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
830 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
831 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
832
833 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
834 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
835 aml_name("STA")));
836 aml_append(dev, method);
837
838 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
839 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
840 aml_name("STA")));
841 aml_append(dev, method);
842
843 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
844 aml_append(method, aml_return(aml_name("STA")));
845 aml_append(dev, method);
846
847 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
848
849 crs = aml_resource_template();
850 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
851 aml_append(dev, aml_name_decl("_CRS", crs));
852
853 return dev;
854 }
855
856 static void build_dbg_aml(Aml *table)
857 {
858 Aml *field;
859 Aml *method;
860 Aml *while_ctx;
861 Aml *scope = aml_scope("\\");
862 Aml *buf = aml_local(0);
863 Aml *len = aml_local(1);
864 Aml *idx = aml_local(2);
865
866 aml_append(scope,
867 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
868 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
869 aml_append(field, aml_named_field("DBGB", 8));
870 aml_append(scope, field);
871
872 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
873
874 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
875 aml_append(method, aml_to_buffer(buf, buf));
876 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
877 aml_append(method, aml_store(aml_int(0), idx));
878
879 while_ctx = aml_while(aml_lless(idx, len));
880 aml_append(while_ctx,
881 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
882 aml_append(while_ctx, aml_increment(idx));
883 aml_append(method, while_ctx);
884
885 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
886 aml_append(scope, method);
887
888 aml_append(table, scope);
889 }
890
891 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
892 {
893 Aml *dev;
894 Aml *crs;
895 Aml *method;
896 uint32_t irqs[] = {5, 10, 11};
897
898 dev = aml_device("%s", name);
899 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
900 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
901
902 crs = aml_resource_template();
903 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
904 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
905 aml_append(dev, aml_name_decl("_PRS", crs));
906
907 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
908 aml_append(method, aml_return(aml_call1("IQST", reg)));
909 aml_append(dev, method);
910
911 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
912 aml_append(method, aml_or(reg, aml_int(0x80), reg));
913 aml_append(dev, method);
914
915 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
916 aml_append(method, aml_return(aml_call1("IQCR", reg)));
917 aml_append(dev, method);
918
919 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
920 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
921 aml_append(method, aml_store(aml_name("PRRI"), reg));
922 aml_append(dev, method);
923
924 return dev;
925 }
926
927 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
928 {
929 Aml *dev;
930 Aml *crs;
931 Aml *method;
932 uint32_t irqs;
933
934 dev = aml_device("%s", name);
935 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
936 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
937
938 crs = aml_resource_template();
939 irqs = gsi;
940 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
941 AML_SHARED, &irqs, 1));
942 aml_append(dev, aml_name_decl("_PRS", crs));
943
944 aml_append(dev, aml_name_decl("_CRS", crs));
945
946 /*
947 * _DIS can be no-op because the interrupt cannot be disabled.
948 */
949 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
950 aml_append(dev, method);
951
952 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
953 aml_append(dev, method);
954
955 return dev;
956 }
957
958 /* _CRS method - get current settings */
959 static Aml *build_iqcr_method(bool is_piix4)
960 {
961 Aml *if_ctx;
962 uint32_t irqs;
963 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
964 Aml *crs = aml_resource_template();
965
966 irqs = 0;
967 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
968 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
969 aml_append(method, aml_name_decl("PRR0", crs));
970
971 aml_append(method,
972 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
973
974 if (is_piix4) {
975 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
976 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
977 aml_append(method, if_ctx);
978 } else {
979 aml_append(method,
980 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
981 aml_name("PRRI")));
982 }
983
984 aml_append(method, aml_return(aml_name("PRR0")));
985 return method;
986 }
987
988 /* _STA method - get status */
989 static Aml *build_irq_status_method(void)
990 {
991 Aml *if_ctx;
992 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
993
994 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
995 aml_append(if_ctx, aml_return(aml_int(0x09)));
996 aml_append(method, if_ctx);
997 aml_append(method, aml_return(aml_int(0x0B)));
998 return method;
999 }
1000
1001 static void build_piix4_pci0_int(Aml *table)
1002 {
1003 Aml *dev;
1004 Aml *crs;
1005 Aml *method;
1006 uint32_t irqs;
1007 Aml *sb_scope = aml_scope("_SB");
1008 Aml *pci0_scope = aml_scope("PCI0");
1009
1010 aml_append(pci0_scope, build_prt(true));
1011 aml_append(sb_scope, pci0_scope);
1012
1013 aml_append(sb_scope, build_irq_status_method());
1014 aml_append(sb_scope, build_iqcr_method(true));
1015
1016 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1017 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1018 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1019 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1020
1021 dev = aml_device("LNKS");
1022 {
1023 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1024 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1025
1026 crs = aml_resource_template();
1027 irqs = 9;
1028 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1029 AML_ACTIVE_HIGH, AML_SHARED,
1030 &irqs, 1));
1031 aml_append(dev, aml_name_decl("_PRS", crs));
1032
1033 /* The SCI cannot be disabled and is always attached to GSI 9,
1034 * so these are no-ops. We only need this link to override the
1035 * polarity to active high and match the content of the MADT.
1036 */
1037 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1038 aml_append(method, aml_return(aml_int(0x0b)));
1039 aml_append(dev, method);
1040
1041 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1042 aml_append(dev, method);
1043
1044 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1045 aml_append(method, aml_return(aml_name("_PRS")));
1046 aml_append(dev, method);
1047
1048 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1049 aml_append(dev, method);
1050 }
1051 aml_append(sb_scope, dev);
1052
1053 aml_append(table, sb_scope);
1054 }
1055
1056 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1057 {
1058 int i;
1059 int head;
1060 Aml *pkg;
1061 char base = name[3] < 'E' ? 'A' : 'E';
1062 char *s = g_strdup(name);
1063 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1064
1065 assert(strlen(s) == 4);
1066
1067 head = name[3] - base;
1068 for (i = 0; i < 4; i++) {
1069 if (head + i > 3) {
1070 head = i * -1;
1071 }
1072 s[3] = base + head + i;
1073 pkg = aml_package(4);
1074 aml_append(pkg, a_nr);
1075 aml_append(pkg, aml_int(i));
1076 aml_append(pkg, aml_name("%s", s));
1077 aml_append(pkg, aml_int(0));
1078 aml_append(ctx, pkg);
1079 }
1080 g_free(s);
1081 }
1082
1083 static Aml *build_q35_routing_table(const char *str)
1084 {
1085 int i;
1086 Aml *pkg;
1087 char *name = g_strdup_printf("%s ", str);
1088
1089 pkg = aml_package(128);
1090 for (i = 0; i < 0x18; i++) {
1091 name[3] = 'E' + (i & 0x3);
1092 append_q35_prt_entry(pkg, i, name);
1093 }
1094
1095 name[3] = 'E';
1096 append_q35_prt_entry(pkg, 0x18, name);
1097
1098 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1099 for (i = 0x0019; i < 0x1e; i++) {
1100 name[3] = 'A';
1101 append_q35_prt_entry(pkg, i, name);
1102 }
1103
1104 /* PCIe->PCI bridge. use PIRQ[E-H] */
1105 name[3] = 'E';
1106 append_q35_prt_entry(pkg, 0x1e, name);
1107 name[3] = 'A';
1108 append_q35_prt_entry(pkg, 0x1f, name);
1109
1110 g_free(name);
1111 return pkg;
1112 }
1113
1114 static void build_q35_pci0_int(Aml *table)
1115 {
1116 Aml *method;
1117 Aml *sb_scope = aml_scope("_SB");
1118 Aml *pci0_scope = aml_scope("PCI0");
1119
1120 /* Zero => PIC mode, One => APIC Mode */
1121 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1122 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1123 {
1124 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1125 }
1126 aml_append(table, method);
1127
1128 aml_append(pci0_scope,
1129 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1130 aml_append(pci0_scope,
1131 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1132
1133 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1134 {
1135 Aml *if_ctx;
1136 Aml *else_ctx;
1137
1138 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1139 section 6.2.8.1 */
1140 /* Note: we provide the same info as the PCI routing
1141 table of the Bochs BIOS */
1142 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1143 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1144 aml_append(method, if_ctx);
1145 else_ctx = aml_else();
1146 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1147 aml_append(method, else_ctx);
1148 }
1149 aml_append(pci0_scope, method);
1150 aml_append(sb_scope, pci0_scope);
1151
1152 aml_append(sb_scope, build_irq_status_method());
1153 aml_append(sb_scope, build_iqcr_method(false));
1154
1155 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1156 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1157 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1158 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1159 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1160 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1161 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1162 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1163
1164 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1165 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1166 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1167 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1168 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1169 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1170 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1171 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1172
1173 aml_append(table, sb_scope);
1174 }
1175
1176 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1177 {
1178 Aml *dev;
1179 Aml *resource_template;
1180
1181 /* DRAM controller */
1182 dev = aml_device("DRAC");
1183 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1184
1185 resource_template = aml_resource_template();
1186 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1187 aml_append(resource_template,
1188 aml_qword_memory(AML_POS_DECODE,
1189 AML_MIN_FIXED,
1190 AML_MAX_FIXED,
1191 AML_NON_CACHEABLE,
1192 AML_READ_WRITE,
1193 0x0000000000000000,
1194 mcfg->base,
1195 mcfg->base + mcfg->size - 1,
1196 0x0000000000000000,
1197 mcfg->size));
1198 } else {
1199 aml_append(resource_template,
1200 aml_dword_memory(AML_POS_DECODE,
1201 AML_MIN_FIXED,
1202 AML_MAX_FIXED,
1203 AML_NON_CACHEABLE,
1204 AML_READ_WRITE,
1205 0x0000000000000000,
1206 mcfg->base,
1207 mcfg->base + mcfg->size - 1,
1208 0x0000000000000000,
1209 mcfg->size));
1210 }
1211 aml_append(dev, aml_name_decl("_CRS", resource_template));
1212
1213 return dev;
1214 }
1215
1216 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1217 {
1218 Aml *scope;
1219 Aml *field;
1220 Aml *method;
1221
1222 scope = aml_scope("_SB.PCI0");
1223
1224 aml_append(scope,
1225 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1226 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1227 aml_append(field, aml_named_field("PCIU", 32));
1228 aml_append(field, aml_named_field("PCID", 32));
1229 aml_append(scope, field);
1230
1231 aml_append(scope,
1232 aml_operation_region("SEJ", AML_SYSTEM_IO,
1233 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1234 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1235 aml_append(field, aml_named_field("B0EJ", 32));
1236 aml_append(scope, field);
1237
1238 aml_append(scope,
1239 aml_operation_region("BNMR", AML_SYSTEM_IO,
1240 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1241 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1242 aml_append(field, aml_named_field("BNUM", 32));
1243 aml_append(field, aml_named_field("PIDX", 32));
1244 aml_append(scope, field);
1245
1246 aml_append(scope, aml_mutex("BLCK", 0));
1247
1248 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1249 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1250 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1251 aml_append(method,
1252 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1253 aml_append(method, aml_release(aml_name("BLCK")));
1254 aml_append(method, aml_return(aml_int(0)));
1255 aml_append(scope, method);
1256
1257 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1258 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1259 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1260 aml_append(method,
1261 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1262 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1263 aml_append(method, aml_release(aml_name("BLCK")));
1264 aml_append(method, aml_return(aml_local(0)));
1265 aml_append(scope, method);
1266
1267 aml_append(scope, aml_pci_pdsm());
1268
1269 aml_append(table, scope);
1270 }
1271
1272 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1273 {
1274 Aml *if_ctx;
1275 Aml *if_ctx2;
1276 Aml *else_ctx;
1277 Aml *method;
1278 Aml *a_cwd1 = aml_name("CDW1");
1279 Aml *a_ctrl = aml_local(0);
1280
1281 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1282 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1283
1284 if_ctx = aml_if(aml_equal(
1285 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1286 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1287 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1288
1289 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1290
1291 /*
1292 * Always allow native PME, AER (no dependencies)
1293 * Allow SHPC (PCI bridges can have SHPC controller)
1294 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1295 */
1296 aml_append(if_ctx, aml_and(a_ctrl,
1297 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1298
1299 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1300 /* Unknown revision */
1301 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1302 aml_append(if_ctx, if_ctx2);
1303
1304 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1305 /* Capabilities bits were masked */
1306 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1307 aml_append(if_ctx, if_ctx2);
1308
1309 /* Update DWORD3 in the buffer */
1310 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1311 aml_append(method, if_ctx);
1312
1313 else_ctx = aml_else();
1314 /* Unrecognized UUID */
1315 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1316 aml_append(method, else_ctx);
1317
1318 aml_append(method, aml_return(aml_arg(3)));
1319 return method;
1320 }
1321
1322 static void build_acpi0017(Aml *table)
1323 {
1324 Aml *dev, *scope, *method;
1325
1326 scope = aml_scope("_SB");
1327 dev = aml_device("CXLM");
1328 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1329
1330 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1331 aml_append(method, aml_return(aml_int(0x0B)));
1332 aml_append(dev, method);
1333 build_cxl_dsm_method(dev);
1334
1335 aml_append(scope, dev);
1336 aml_append(table, scope);
1337 }
1338
1339 static void
1340 build_dsdt(GArray *table_data, BIOSLinker *linker,
1341 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1342 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1343 {
1344 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE,
1345 NULL);
1346 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL);
1347 CrsRangeEntry *entry;
1348 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1349 CrsRangeSet crs_range_set;
1350 PCMachineState *pcms = PC_MACHINE(machine);
1351 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1352 X86MachineState *x86ms = X86_MACHINE(machine);
1353 AcpiMcfgInfo mcfg;
1354 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1355 uint32_t nr_mem = machine->ram_slots;
1356 int root_bus_limit = 0xFF;
1357 PCIBus *bus = NULL;
1358 #ifdef CONFIG_TPM
1359 TPMIf *tpm = tpm_find();
1360 #endif
1361 bool cxl_present = false;
1362 int i;
1363 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1364 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1365 .oem_table_id = x86ms->oem_table_id };
1366
1367 assert(!!i440fx != !!q35);
1368
1369 acpi_table_begin(&table, table_data);
1370 dsdt = init_aml_allocator();
1371
1372 build_dbg_aml(dsdt);
1373 if (i440fx) {
1374 sb_scope = aml_scope("_SB");
1375 dev = aml_device("PCI0");
1376 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1377 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1378 aml_append(dev, aml_pci_edsm());
1379 aml_append(sb_scope, dev);
1380 aml_append(dsdt, sb_scope);
1381
1382 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1383 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1384 }
1385 build_piix4_pci0_int(dsdt);
1386 } else if (q35) {
1387 sb_scope = aml_scope("_SB");
1388 dev = aml_device("PCI0");
1389 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1390 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1391 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1392 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1393 aml_append(dev, aml_pci_edsm());
1394 aml_append(sb_scope, dev);
1395 if (mcfg_valid) {
1396 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1397 }
1398
1399 if (pm->smi_on_cpuhp) {
1400 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1401 dev = aml_device("PCI0.SMI0");
1402 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1403 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1404 crs = aml_resource_template();
1405 aml_append(crs,
1406 aml_io(
1407 AML_DECODE16,
1408 pm->fadt.smi_cmd,
1409 pm->fadt.smi_cmd,
1410 1,
1411 2)
1412 );
1413 aml_append(dev, aml_name_decl("_CRS", crs));
1414 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1415 aml_int(pm->fadt.smi_cmd), 2));
1416 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1417 AML_WRITE_AS_ZEROS);
1418 aml_append(field, aml_named_field("SMIC", 8));
1419 aml_append(field, aml_reserved_field(8));
1420 aml_append(dev, field);
1421 aml_append(sb_scope, dev);
1422 }
1423
1424 aml_append(dsdt, sb_scope);
1425
1426 if (pm->pcihp_bridge_en) {
1427 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1428 }
1429 build_q35_pci0_int(dsdt);
1430 }
1431
1432 if (misc->has_hpet) {
1433 build_hpet_aml(dsdt);
1434 }
1435
1436 if (vmbus_bridge) {
1437 sb_scope = aml_scope("_SB");
1438 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1439 aml_append(dsdt, sb_scope);
1440 }
1441
1442 scope = aml_scope("_GPE");
1443 {
1444 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1445 if (machine->nvdimms_state->is_enabled) {
1446 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1447 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1448 aml_int(0x80)));
1449 aml_append(scope, method);
1450 }
1451 }
1452 aml_append(dsdt, scope);
1453
1454 if (pcmc->legacy_cpu_hotplug) {
1455 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1456 } else {
1457 CPUHotplugFeatures opts = {
1458 .acpi_1_compatible = true, .has_legacy_cphp = true,
1459 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1460 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1461 };
1462 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
1463 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
1464 AML_SYSTEM_IO);
1465 }
1466
1467 if (pcms->memhp_io_base && nr_mem) {
1468 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1469 "\\_GPE._E03", AML_SYSTEM_IO,
1470 pcms->memhp_io_base);
1471 }
1472
1473 crs_range_set_init(&crs_range_set);
1474 bus = PC_MACHINE(machine)->pcibus;
1475 if (bus) {
1476 QLIST_FOREACH(bus, &bus->child, sibling) {
1477 uint8_t bus_num = pci_bus_num(bus);
1478 uint8_t numa_node = pci_bus_numa_node(bus);
1479 uint32_t uid;
1480
1481 /* look only for expander root buses */
1482 if (!pci_bus_is_root(bus)) {
1483 continue;
1484 }
1485
1486 if (bus_num < root_bus_limit) {
1487 root_bus_limit = bus_num - 1;
1488 }
1489
1490 uid = object_property_get_uint(OBJECT(bus), "acpi_uid",
1491 &error_fatal);
1492 scope = aml_scope("\\_SB");
1493
1494 if (pci_bus_is_cxl(bus)) {
1495 dev = aml_device("CL%.02X", bus_num);
1496 } else {
1497 dev = aml_device("PC%.02X", bus_num);
1498 }
1499 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1500 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1501 if (pci_bus_is_cxl(bus)) {
1502 struct Aml *aml_pkg = aml_package(2);
1503
1504 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1505 aml_append(aml_pkg, aml_eisaid("PNP0A08"));
1506 aml_append(aml_pkg, aml_eisaid("PNP0A03"));
1507 aml_append(dev, aml_name_decl("_CID", aml_pkg));
1508 build_cxl_osc_method(dev);
1509 } else if (pci_bus_is_express(bus)) {
1510 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1511 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1512
1513 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1514 aml_append(dev, build_q35_osc_method(true));
1515 } else {
1516 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1517 }
1518
1519 if (numa_node != NUMA_NODE_UNASSIGNED) {
1520 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1521 }
1522
1523 aml_append(dev, build_prt(false));
1524 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1525 0, 0, 0, 0);
1526 aml_append(dev, aml_name_decl("_CRS", crs));
1527 aml_append(scope, dev);
1528 aml_append(dsdt, scope);
1529
1530 /* Handle the ranges for the PXB expanders */
1531 if (pci_bus_is_cxl(bus)) {
1532 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1533 uint64_t base = mr->addr;
1534
1535 cxl_present = true;
1536 crs_range_insert(crs_range_set.mem_ranges, base,
1537 base + memory_region_size(mr) - 1);
1538 }
1539 }
1540 }
1541
1542 if (cxl_present) {
1543 build_acpi0017(dsdt);
1544 }
1545
1546 /*
1547 * At this point crs_range_set has all the ranges used by pci
1548 * busses *other* than PCI0. These ranges will be excluded from
1549 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1550 * too.
1551 */
1552 if (mcfg_valid) {
1553 crs_range_insert(crs_range_set.mem_ranges,
1554 mcfg.base, mcfg.base + mcfg.size - 1);
1555 }
1556
1557 scope = aml_scope("\\_SB.PCI0");
1558 /* build PCI0._CRS */
1559 crs = aml_resource_template();
1560 aml_append(crs,
1561 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1562 0x0000, 0x0, root_bus_limit,
1563 0x0000, root_bus_limit + 1));
1564 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1565
1566 aml_append(crs,
1567 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1568 AML_POS_DECODE, AML_ENTIRE_RANGE,
1569 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1570
1571 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1572 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1573 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1574 aml_append(crs,
1575 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1576 AML_POS_DECODE, AML_ENTIRE_RANGE,
1577 0x0000, entry->base, entry->limit,
1578 0x0000, entry->limit - entry->base + 1));
1579 }
1580
1581 aml_append(crs,
1582 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1583 AML_CACHEABLE, AML_READ_WRITE,
1584 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1585
1586 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1587 range_lob(pci_hole),
1588 range_upb(pci_hole));
1589 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1590 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1591 aml_append(crs,
1592 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1593 AML_NON_CACHEABLE, AML_READ_WRITE,
1594 0, entry->base, entry->limit,
1595 0, entry->limit - entry->base + 1));
1596 }
1597
1598 if (!range_is_empty(pci_hole64)) {
1599 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1600 range_lob(pci_hole64),
1601 range_upb(pci_hole64));
1602 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1603 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1604 aml_append(crs,
1605 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1606 AML_MAX_FIXED,
1607 AML_CACHEABLE, AML_READ_WRITE,
1608 0, entry->base, entry->limit,
1609 0, entry->limit - entry->base + 1));
1610 }
1611 }
1612
1613 #ifdef CONFIG_TPM
1614 if (TPM_IS_TIS_ISA(tpm_find())) {
1615 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1616 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1617 }
1618 #endif
1619 aml_append(scope, aml_name_decl("_CRS", crs));
1620
1621 /* reserve GPE0 block resources */
1622 dev = aml_device("GPE0");
1623 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1624 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1625 /* device present, functioning, decoding, not shown in UI */
1626 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1627 crs = aml_resource_template();
1628 aml_append(crs,
1629 aml_io(
1630 AML_DECODE16,
1631 pm->fadt.gpe0_blk.address,
1632 pm->fadt.gpe0_blk.address,
1633 1,
1634 pm->fadt.gpe0_blk.bit_width / 8)
1635 );
1636 aml_append(dev, aml_name_decl("_CRS", crs));
1637 aml_append(scope, dev);
1638
1639 crs_range_set_free(&crs_range_set);
1640
1641 /* reserve PCIHP resources */
1642 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1643 dev = aml_device("PHPR");
1644 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1645 aml_append(dev,
1646 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1647 /* device present, functioning, decoding, not shown in UI */
1648 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1649 crs = aml_resource_template();
1650 aml_append(crs,
1651 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1652 pm->pcihp_io_len)
1653 );
1654 aml_append(dev, aml_name_decl("_CRS", crs));
1655 aml_append(scope, dev);
1656 }
1657 aml_append(dsdt, scope);
1658
1659 /* create S3_ / S4_ / S5_ packages if necessary */
1660 scope = aml_scope("\\");
1661 if (!pm->s3_disabled) {
1662 pkg = aml_package(4);
1663 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1664 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1665 aml_append(pkg, aml_int(0)); /* reserved */
1666 aml_append(pkg, aml_int(0)); /* reserved */
1667 aml_append(scope, aml_name_decl("_S3", pkg));
1668 }
1669
1670 if (!pm->s4_disabled) {
1671 pkg = aml_package(4);
1672 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1673 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1674 aml_append(pkg, aml_int(pm->s4_val));
1675 aml_append(pkg, aml_int(0)); /* reserved */
1676 aml_append(pkg, aml_int(0)); /* reserved */
1677 aml_append(scope, aml_name_decl("_S4", pkg));
1678 }
1679
1680 pkg = aml_package(4);
1681 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1682 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1683 aml_append(pkg, aml_int(0)); /* reserved */
1684 aml_append(pkg, aml_int(0)); /* reserved */
1685 aml_append(scope, aml_name_decl("_S5", pkg));
1686 aml_append(dsdt, scope);
1687
1688 /* create fw_cfg node, unconditionally */
1689 {
1690 scope = aml_scope("\\_SB.PCI0");
1691 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1692 aml_append(dsdt, scope);
1693 }
1694
1695 sb_scope = aml_scope("\\_SB");
1696 {
1697 Object *pci_host = acpi_get_i386_pci_host();
1698
1699 if (pci_host) {
1700 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus;
1701 Aml *ascope = aml_scope("PCI0");
1702 /* Scan all PCI buses. Generate tables to support hotplug. */
1703 build_append_pci_bus_devices(ascope, pbus);
1704 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) {
1705 build_append_pcihp_slots(ascope, pbus);
1706 }
1707 aml_append(sb_scope, ascope);
1708 }
1709 }
1710
1711 #ifdef CONFIG_TPM
1712 if (TPM_IS_CRB(tpm)) {
1713 dev = aml_device("TPM");
1714 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1715 aml_append(dev, aml_name_decl("_STR",
1716 aml_string("TPM 2.0 Device")));
1717 crs = aml_resource_template();
1718 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1719 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1720 aml_append(dev, aml_name_decl("_CRS", crs));
1721
1722 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1723 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1724
1725 tpm_build_ppi_acpi(tpm, dev);
1726
1727 aml_append(sb_scope, dev);
1728 }
1729 #endif
1730
1731 if (pcms->sgx_epc.size != 0) {
1732 uint64_t epc_base = pcms->sgx_epc.base;
1733 uint64_t epc_size = pcms->sgx_epc.size;
1734
1735 dev = aml_device("EPC");
1736 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1737 aml_append(dev, aml_name_decl("_STR",
1738 aml_unicode("Enclave Page Cache 1.0")));
1739 crs = aml_resource_template();
1740 aml_append(crs,
1741 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1742 AML_MAX_FIXED, AML_NON_CACHEABLE,
1743 AML_READ_WRITE, 0, epc_base,
1744 epc_base + epc_size - 1, 0, epc_size));
1745 aml_append(dev, aml_name_decl("_CRS", crs));
1746
1747 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1748 aml_append(method, aml_return(aml_int(0x0f)));
1749 aml_append(dev, method);
1750
1751 aml_append(sb_scope, dev);
1752 }
1753 aml_append(dsdt, sb_scope);
1754
1755 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1756 bool has_pcnt;
1757
1758 Object *pci_host = acpi_get_i386_pci_host();
1759 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus;
1760
1761 scope = aml_scope("\\_SB.PCI0");
1762 has_pcnt = build_append_notfication_callback(scope, b);
1763 if (has_pcnt) {
1764 aml_append(dsdt, scope);
1765 }
1766
1767 scope = aml_scope("_GPE");
1768 {
1769 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1770 if (has_pcnt) {
1771 aml_append(method,
1772 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1773 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1774 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1775 }
1776 aml_append(scope, method);
1777 }
1778 aml_append(dsdt, scope);
1779 }
1780
1781 /* copy AML table into ACPI tables blob and patch header there */
1782 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1783 acpi_table_end(linker, &table);
1784 free_aml_allocator();
1785 }
1786
1787 /*
1788 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1789 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1790 */
1791 static void
1792 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1793 const char *oem_table_id)
1794 {
1795 AcpiTable table = { .sig = "HPET", .rev = 1,
1796 .oem_id = oem_id, .oem_table_id = oem_table_id };
1797
1798 acpi_table_begin(&table, table_data);
1799 /* Note timer_block_id value must be kept in sync with value advertised by
1800 * emulated hpet
1801 */
1802 /* Event Timer Block ID */
1803 build_append_int_noprefix(table_data, 0x8086a201, 4);
1804 /* BASE_ADDRESS */
1805 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1806 /* HPET Number */
1807 build_append_int_noprefix(table_data, 0, 1);
1808 /* Main Counter Minimum Clock_tick in Periodic Mode */
1809 build_append_int_noprefix(table_data, 0, 2);
1810 /* Page Protection And OEM Attribute */
1811 build_append_int_noprefix(table_data, 0, 1);
1812 acpi_table_end(linker, &table);
1813 }
1814
1815 #ifdef CONFIG_TPM
1816 /*
1817 * TCPA Description Table
1818 *
1819 * Following Level 00, Rev 00.37 of specs:
1820 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1821 * 7.1.2 ACPI Table Layout
1822 */
1823 static void
1824 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1825 const char *oem_id, const char *oem_table_id)
1826 {
1827 unsigned log_addr_offset;
1828 AcpiTable table = { .sig = "TCPA", .rev = 2,
1829 .oem_id = oem_id, .oem_table_id = oem_table_id };
1830
1831 acpi_table_begin(&table, table_data);
1832 /* Platform Class */
1833 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1834 /* Log Area Minimum Length (LAML) */
1835 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1836 /* Log Area Start Address (LASA) */
1837 log_addr_offset = table_data->len;
1838 build_append_int_noprefix(table_data, 0, 8);
1839
1840 /* allocate/reserve space for TPM log area */
1841 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1842 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1843 false /* high memory */);
1844 /* log area start address to be filled by Guest linker */
1845 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1846 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1847
1848 acpi_table_end(linker, &table);
1849 }
1850 #endif
1851
1852 #define HOLE_640K_START (640 * KiB)
1853 #define HOLE_640K_END (1 * MiB)
1854
1855 /*
1856 * ACPI spec, Revision 3.0
1857 * 5.2.15 System Resource Affinity Table (SRAT)
1858 */
1859 static void
1860 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1861 {
1862 int i;
1863 int numa_mem_start, slots;
1864 uint64_t mem_len, mem_base, next_base;
1865 MachineClass *mc = MACHINE_GET_CLASS(machine);
1866 X86MachineState *x86ms = X86_MACHINE(machine);
1867 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1868 int nb_numa_nodes = machine->numa_state->num_nodes;
1869 NodeInfo *numa_info = machine->numa_state->nodes;
1870 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1871 .oem_table_id = x86ms->oem_table_id };
1872
1873 acpi_table_begin(&table, table_data);
1874 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1875 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1876
1877 for (i = 0; i < apic_ids->len; i++) {
1878 int node_id = apic_ids->cpus[i].props.node_id;
1879 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1880
1881 if (apic_id < 255) {
1882 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1883 build_append_int_noprefix(table_data, 0, 1); /* Type */
1884 build_append_int_noprefix(table_data, 16, 1); /* Length */
1885 /* Proximity Domain [7:0] */
1886 build_append_int_noprefix(table_data, node_id, 1);
1887 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1888 /* Flags, Table 5-36 */
1889 build_append_int_noprefix(table_data, 1, 4);
1890 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1891 /* Proximity Domain [31:8] */
1892 build_append_int_noprefix(table_data, 0, 3);
1893 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1894 } else {
1895 /*
1896 * ACPI spec, Revision 4.0
1897 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1898 */
1899 build_append_int_noprefix(table_data, 2, 1); /* Type */
1900 build_append_int_noprefix(table_data, 24, 1); /* Length */
1901 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1902 /* Proximity Domain */
1903 build_append_int_noprefix(table_data, node_id, 4);
1904 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1905 /* Flags, Table 5-39 */
1906 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1907 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1908 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1909 }
1910 }
1911
1912 /* the memory map is a bit tricky, it contains at least one hole
1913 * from 640k-1M and possibly another one from 3.5G-4G.
1914 */
1915 next_base = 0;
1916 numa_mem_start = table_data->len;
1917
1918 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1919 mem_base = next_base;
1920 mem_len = numa_info[i - 1].node_mem;
1921 next_base = mem_base + mem_len;
1922
1923 /* Cut out the 640K hole */
1924 if (mem_base <= HOLE_640K_START &&
1925 next_base > HOLE_640K_START) {
1926 mem_len -= next_base - HOLE_640K_START;
1927 if (mem_len > 0) {
1928 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1929 MEM_AFFINITY_ENABLED);
1930 }
1931
1932 /* Check for the rare case: 640K < RAM < 1M */
1933 if (next_base <= HOLE_640K_END) {
1934 next_base = HOLE_640K_END;
1935 continue;
1936 }
1937 mem_base = HOLE_640K_END;
1938 mem_len = next_base - HOLE_640K_END;
1939 }
1940
1941 /* Cut out the ACPI_PCI hole */
1942 if (mem_base <= x86ms->below_4g_mem_size &&
1943 next_base > x86ms->below_4g_mem_size) {
1944 mem_len -= next_base - x86ms->below_4g_mem_size;
1945 if (mem_len > 0) {
1946 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1947 MEM_AFFINITY_ENABLED);
1948 }
1949 mem_base = x86ms->above_4g_mem_start;
1950 mem_len = next_base - x86ms->below_4g_mem_size;
1951 next_base = mem_base + mem_len;
1952 }
1953
1954 if (mem_len > 0) {
1955 build_srat_memory(table_data, mem_base, mem_len, i - 1,
1956 MEM_AFFINITY_ENABLED);
1957 }
1958 }
1959
1960 if (machine->nvdimms_state->is_enabled) {
1961 nvdimm_build_srat(table_data);
1962 }
1963
1964 sgx_epc_build_srat(table_data);
1965
1966 /*
1967 * TODO: this part is not in ACPI spec and current linux kernel boots fine
1968 * without these entries. But I recall there were issues the last time I
1969 * tried to remove it with some ancient guest OS, however I can't remember
1970 * what that was so keep this around for now
1971 */
1972 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
1973 for (; slots < nb_numa_nodes + 2; slots++) {
1974 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1975 }
1976
1977 build_srat_generic_affinity_structures(table_data);
1978
1979 /*
1980 * Entry is required for Windows to enable memory hotplug in OS
1981 * and for Linux to enable SWIOTLB when booted with less than
1982 * 4G of RAM. Windows works better if the entry sets proximity
1983 * to the highest NUMA node in the machine.
1984 * Memory devices may override proximity set by this entry,
1985 * providing _PXM method if necessary.
1986 */
1987 if (machine->device_memory) {
1988 build_srat_memory(table_data, machine->device_memory->base,
1989 memory_region_size(&machine->device_memory->mr),
1990 nb_numa_nodes - 1,
1991 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
1992 }
1993
1994 acpi_table_end(linker, &table);
1995 }
1996
1997 /*
1998 * Insert DMAR scope for PCI bridges and endpoint devices
1999 */
2000 static void
2001 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2002 {
2003 const size_t device_scope_size = 6 /* device scope structure */ +
2004 2 /* 1 path entry */;
2005 GArray *scope_blob = opaque;
2006
2007 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2008 /* Dmar Scope Type: 0x02 for PCI Bridge */
2009 build_append_int_noprefix(scope_blob, 0x02, 1);
2010 } else {
2011 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2012 build_append_int_noprefix(scope_blob, 0x01, 1);
2013 }
2014
2015 /* length */
2016 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2017 /* reserved */
2018 build_append_int_noprefix(scope_blob, 0, 2);
2019 /* enumeration_id */
2020 build_append_int_noprefix(scope_blob, 0, 1);
2021 /* bus */
2022 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2023 /* device */
2024 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2025 /* function */
2026 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2027 }
2028
2029 /* For a given PCI host bridge, walk and insert DMAR scope */
2030 static int
2031 dmar_host_bridges(Object *obj, void *opaque)
2032 {
2033 GArray *scope_blob = opaque;
2034
2035 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2036 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2037
2038 if (bus && !pci_bus_bypass_iommu(bus)) {
2039 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2040 }
2041 }
2042
2043 return 0;
2044 }
2045
2046 /*
2047 * Intel ® Virtualization Technology for Directed I/O
2048 * Architecture Specification. Revision 3.3
2049 * 8.1 DMA Remapping Reporting Structure
2050 */
2051 static void
2052 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2053 const char *oem_table_id)
2054 {
2055 uint8_t dmar_flags = 0;
2056 uint8_t rsvd10[10] = {};
2057 /* Root complex IOAPIC uses one path only */
2058 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2059 2 /* 1 path entry */;
2060 X86IOMMUState *iommu = x86_iommu_get_default();
2061 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2062 GArray *scope_blob = g_array_new(false, true, 1);
2063
2064 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2065 .oem_table_id = oem_table_id };
2066
2067 /*
2068 * A PCI bus walk, for each PCI host bridge.
2069 * Insert scope for each PCI bridge and endpoint device which
2070 * is attached to a bus with iommu enabled.
2071 */
2072 object_child_foreach_recursive(object_get_root(),
2073 dmar_host_bridges, scope_blob);
2074
2075 assert(iommu);
2076 if (x86_iommu_ir_supported(iommu)) {
2077 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2078 }
2079
2080 acpi_table_begin(&table, table_data);
2081 /* Host Address Width */
2082 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2083 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2084 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2085
2086 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2087 build_append_int_noprefix(table_data, 0, 2); /* Type */
2088 /* Length */
2089 build_append_int_noprefix(table_data,
2090 16 + ioapic_scope_size + scope_blob->len, 2);
2091 /* Flags */
2092 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2093 1);
2094 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2095 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2096 /* Register Base Address */
2097 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2098
2099 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2100 * 8.3.1 (version Oct. 2014 or later). */
2101 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2102 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2103 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2104 /* Enumeration ID */
2105 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2106 /* Start Bus Number */
2107 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2108 /* Path, {Device, Function} pair */
2109 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2110 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2111
2112 /* Add scope found above */
2113 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2114 g_array_free(scope_blob, true);
2115
2116 if (iommu->dt_supported) {
2117 /* 8.5 Root Port ATS Capability Reporting Structure */
2118 build_append_int_noprefix(table_data, 2, 2); /* Type */
2119 build_append_int_noprefix(table_data, 8, 2); /* Length */
2120 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2121 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2122 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2123 }
2124
2125 acpi_table_end(linker, &table);
2126 }
2127
2128 /*
2129 * Windows ACPI Emulated Devices Table
2130 * (Version 1.0 - April 6, 2009)
2131 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2132 *
2133 * Helpful to speedup Windows guests and ignored by others.
2134 */
2135 static void
2136 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2137 const char *oem_table_id)
2138 {
2139 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2140 .oem_table_id = oem_table_id };
2141
2142 acpi_table_begin(&table, table_data);
2143 /*
2144 * Set "ACPI PM timer good" flag.
2145 *
2146 * Tells Windows guests that our ACPI PM timer is reliable in the
2147 * sense that guest can read it only once to obtain a reliable value.
2148 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2149 */
2150 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2151 acpi_table_end(linker, &table);
2152 }
2153
2154 /*
2155 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2156 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2157 */
2158 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2159
2160 /*
2161 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2162 * necessary for the PCI topology.
2163 */
2164 static void
2165 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2166 {
2167 GArray *table_data = opaque;
2168 uint32_t entry;
2169
2170 /* "Select" IVHD entry, type 0x2 */
2171 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2172 build_append_int_noprefix(table_data, entry, 4);
2173
2174 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2175 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2176 uint8_t sec = pci_bus_num(sec_bus);
2177 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2178
2179 if (pci_bus_is_express(sec_bus)) {
2180 /*
2181 * Walk the bus if there are subordinates, otherwise use a range
2182 * to cover an entire leaf bus. We could potentially also use a
2183 * range for traversed buses, but we'd need to take care not to
2184 * create both Select and Range entries covering the same device.
2185 * This is easier and potentially more compact.
2186 *
2187 * An example bare metal system seems to use Select entries for
2188 * root ports without a slot (ie. built-ins) and Range entries
2189 * when there is a slot. The same system also only hard-codes
2190 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2191 * making no effort to support nested bridges. We attempt to
2192 * be more thorough here.
2193 */
2194 if (sec == sub) { /* leaf bus */
2195 /* "Start of Range" IVHD entry, type 0x3 */
2196 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2197 build_append_int_noprefix(table_data, entry, 4);
2198 /* "End of Range" IVHD entry, type 0x4 */
2199 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2200 build_append_int_noprefix(table_data, entry, 4);
2201 } else {
2202 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2203 }
2204 } else {
2205 /*
2206 * If the secondary bus is conventional, then we need to create an
2207 * Alias range for everything downstream. The range covers the
2208 * first devfn on the secondary bus to the last devfn on the
2209 * subordinate bus. The alias target depends on legacy versus
2210 * express bridges, just as in pci_device_iommu_address_space().
2211 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2212 */
2213 uint16_t dev_id_a, dev_id_b;
2214
2215 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2216
2217 if (pci_is_express(dev) &&
2218 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2219 dev_id_b = dev_id_a;
2220 } else {
2221 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2222 }
2223
2224 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2225 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2226 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2227
2228 /* "End of Range" IVHD entry, type 0x4 */
2229 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2230 build_append_int_noprefix(table_data, entry, 4);
2231 }
2232 }
2233 }
2234
2235 /* For all PCI host bridges, walk and insert IVHD entries */
2236 static int
2237 ivrs_host_bridges(Object *obj, void *opaque)
2238 {
2239 GArray *ivhd_blob = opaque;
2240
2241 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2242 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2243
2244 if (bus && !pci_bus_bypass_iommu(bus)) {
2245 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2246 }
2247 }
2248
2249 return 0;
2250 }
2251
2252 static void
2253 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2254 const char *oem_table_id)
2255 {
2256 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2257 GArray *ivhd_blob = g_array_new(false, true, 1);
2258 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2259 .oem_table_id = oem_table_id };
2260 uint64_t feature_report;
2261
2262 acpi_table_begin(&table, table_data);
2263 /* IVinfo - IO virtualization information common to all
2264 * IOMMU units in a system
2265 */
2266 build_append_int_noprefix(table_data,
2267 (1UL << 0) | /* EFRSup */
2268 (40UL << 8), /* PASize */
2269 4);
2270 /* reserved */
2271 build_append_int_noprefix(table_data, 0, 8);
2272
2273 /*
2274 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2275 * complete set of IVHD entries. Do this into a separate blob so that we
2276 * can calculate the total IVRS table length here and then append the new
2277 * blob further below. Fall back to an entry covering all devices, which
2278 * is sufficient when no aliases are present.
2279 */
2280 object_child_foreach_recursive(object_get_root(),
2281 ivrs_host_bridges, ivhd_blob);
2282
2283 if (!ivhd_blob->len) {
2284 /*
2285 * Type 1 device entry reporting all devices
2286 * These are 4-byte device entries currently reporting the range of
2287 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2288 */
2289 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2290 }
2291
2292 /*
2293 * When interrupt remapping is supported, we add a special IVHD device
2294 * for type IO-APIC
2295 * Refer to spec - Table 95: IVHD device entry type codes
2296 *
2297 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2298 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2299 */
2300 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2301 build_append_int_noprefix(ivhd_blob,
2302 (0x1ull << 56) | /* type IOAPIC */
2303 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2304 0x48, /* special device */
2305 8);
2306 }
2307
2308 /* IVHD definition - type 10h */
2309 build_append_int_noprefix(table_data, 0x10, 1);
2310 /* virtualization flags */
2311 build_append_int_noprefix(table_data,
2312 (1UL << 0) | /* HtTunEn */
2313 (1UL << 4) | /* iotblSup */
2314 (1UL << 6) | /* PrefSup */
2315 (1UL << 7), /* PPRSup */
2316 1);
2317
2318 /* IVHD length */
2319 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2);
2320 /* DeviceID */
2321 build_append_int_noprefix(table_data,
2322 object_property_get_int(OBJECT(&s->pci), "addr",
2323 &error_abort), 2);
2324 /* Capability offset */
2325 build_append_int_noprefix(table_data, s->pci.capab_offset, 2);
2326 /* IOMMU base address */
2327 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
2328 /* PCI Segment Group */
2329 build_append_int_noprefix(table_data, 0, 2);
2330 /* IOMMU info */
2331 build_append_int_noprefix(table_data, 0, 2);
2332 /* IOMMU Feature Reporting */
2333 feature_report = (48UL << 30) | /* HATS */
2334 (48UL << 28) | /* GATS */
2335 (1UL << 2) | /* GTSup */
2336 (1UL << 6); /* GASup */
2337 if (s->xtsup) {
2338 feature_report |= (1UL << 0); /* XTSup */
2339 }
2340 build_append_int_noprefix(table_data, feature_report, 4);
2341
2342 /* IVHD entries as found above */
2343 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2344
2345 /* IVHD definition - type 11h */
2346 build_append_int_noprefix(table_data, 0x11, 1);
2347 /* virtualization flags */
2348 build_append_int_noprefix(table_data,
2349 (1UL << 0) | /* HtTunEn */
2350 (1UL << 4), /* iotblSup */
2351 1);
2352
2353 /* IVHD length */
2354 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2);
2355 /* DeviceID */
2356 build_append_int_noprefix(table_data,
2357 object_property_get_int(OBJECT(&s->pci), "addr",
2358 &error_abort), 2);
2359 /* Capability offset */
2360 build_append_int_noprefix(table_data, s->pci.capab_offset, 2);
2361 /* IOMMU base address */
2362 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8);
2363 /* PCI Segment Group */
2364 build_append_int_noprefix(table_data, 0, 2);
2365 /* IOMMU info */
2366 build_append_int_noprefix(table_data, 0, 2);
2367 /* IOMMU Attributes */
2368 build_append_int_noprefix(table_data, 0, 4);
2369 /* EFR Register Image */
2370 build_append_int_noprefix(table_data,
2371 amdvi_extended_feature_register(s),
2372 8);
2373 /* EFR Register Image 2 */
2374 build_append_int_noprefix(table_data, 0, 8);
2375
2376 /* IVHD entries as found above */
2377 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2378
2379 g_array_free(ivhd_blob, TRUE);
2380 acpi_table_end(linker, &table);
2381 }
2382
2383 typedef
2384 struct AcpiBuildState {
2385 /* Copy of table in RAM (for patching). */
2386 MemoryRegion *table_mr;
2387 /* Is table patched? */
2388 uint8_t patched;
2389 MemoryRegion *rsdp_mr;
2390 MemoryRegion *linker_mr;
2391 } AcpiBuildState;
2392
2393 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2394 {
2395 Object *pci_host;
2396 QObject *o;
2397
2398 pci_host = acpi_get_i386_pci_host();
2399 if (!pci_host) {
2400 return false;
2401 }
2402
2403 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2404 if (!o) {
2405 return false;
2406 }
2407 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2408 qobject_unref(o);
2409 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2410 return false;
2411 }
2412
2413 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2414 assert(o);
2415 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2416 qobject_unref(o);
2417 return true;
2418 }
2419
2420 static
2421 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2422 {
2423 PCMachineState *pcms = PC_MACHINE(machine);
2424 X86MachineState *x86ms = X86_MACHINE(machine);
2425 DeviceState *iommu = pcms->iommu;
2426 GArray *table_offsets;
2427 unsigned facs, dsdt, rsdt;
2428 AcpiPmInfo pm;
2429 AcpiMiscInfo misc;
2430 AcpiMcfgInfo mcfg;
2431 Range pci_hole = {}, pci_hole64 = {};
2432 uint8_t *u;
2433 GArray *tables_blob = tables->table_data;
2434 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2435 Object *vmgenid_dev;
2436 char *oem_id;
2437 char *oem_table_id;
2438
2439 acpi_get_pm_info(machine, &pm);
2440 acpi_get_misc_info(&misc);
2441 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2442 acpi_get_slic_oem(&slic_oem);
2443
2444 if (slic_oem.id) {
2445 oem_id = slic_oem.id;
2446 } else {
2447 oem_id = x86ms->oem_id;
2448 }
2449
2450 if (slic_oem.table_id) {
2451 oem_table_id = slic_oem.table_id;
2452 } else {
2453 oem_table_id = x86ms->oem_table_id;
2454 }
2455
2456 table_offsets = g_array_new(false, true /* clear */,
2457 sizeof(uint32_t));
2458 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2459
2460 bios_linker_loader_alloc(tables->linker,
2461 ACPI_BUILD_TABLE_FILE, tables_blob,
2462 64 /* Ensure FACS is aligned */,
2463 false /* high memory */);
2464
2465 /*
2466 * FACS is pointed to by FADT.
2467 * We place it first since it's the only table that has alignment
2468 * requirements.
2469 */
2470 facs = tables_blob->len;
2471 build_facs(tables_blob);
2472
2473 /* DSDT is pointed to by FADT */
2474 dsdt = tables_blob->len;
2475 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2476 &pci_hole, &pci_hole64, machine);
2477
2478 /* ACPI tables pointed to by RSDT */
2479 acpi_add_table(table_offsets, tables_blob);
2480 pm.fadt.facs_tbl_offset = &facs;
2481 pm.fadt.dsdt_tbl_offset = &dsdt;
2482 pm.fadt.xdsdt_tbl_offset = &dsdt;
2483 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2484
2485 acpi_add_table(table_offsets, tables_blob);
2486 acpi_build_madt(tables_blob, tables->linker, x86ms,
2487 x86ms->oem_id, x86ms->oem_table_id);
2488
2489 #ifdef CONFIG_ACPI_ERST
2490 {
2491 Object *erst_dev;
2492 erst_dev = find_erst_dev();
2493 if (erst_dev) {
2494 acpi_add_table(table_offsets, tables_blob);
2495 build_erst(tables_blob, tables->linker, erst_dev,
2496 x86ms->oem_id, x86ms->oem_table_id);
2497 }
2498 }
2499 #endif
2500
2501 vmgenid_dev = find_vmgenid_dev();
2502 if (vmgenid_dev) {
2503 acpi_add_table(table_offsets, tables_blob);
2504 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2505 tables->vmgenid, tables->linker, x86ms->oem_id);
2506 }
2507
2508 if (misc.has_hpet) {
2509 acpi_add_table(table_offsets, tables_blob);
2510 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2511 x86ms->oem_table_id);
2512 }
2513 #ifdef CONFIG_TPM
2514 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2515 if (misc.tpm_version == TPM_VERSION_1_2) {
2516 acpi_add_table(table_offsets, tables_blob);
2517 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2518 x86ms->oem_id, x86ms->oem_table_id);
2519 } else { /* TPM_VERSION_2_0 */
2520 acpi_add_table(table_offsets, tables_blob);
2521 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2522 x86ms->oem_id, x86ms->oem_table_id);
2523 }
2524 }
2525 #endif
2526 if (machine->numa_state->num_nodes) {
2527 acpi_add_table(table_offsets, tables_blob);
2528 build_srat(tables_blob, tables->linker, machine);
2529 if (machine->numa_state->have_numa_distance) {
2530 acpi_add_table(table_offsets, tables_blob);
2531 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2532 x86ms->oem_table_id);
2533 }
2534 if (machine->numa_state->hmat_enabled) {
2535 acpi_add_table(table_offsets, tables_blob);
2536 build_hmat(tables_blob, tables->linker, machine->numa_state,
2537 x86ms->oem_id, x86ms->oem_table_id);
2538 }
2539 }
2540 if (acpi_get_mcfg(&mcfg)) {
2541 acpi_add_table(table_offsets, tables_blob);
2542 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2543 x86ms->oem_table_id);
2544 }
2545 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2546 acpi_add_table(table_offsets, tables_blob);
2547 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2548 x86ms->oem_table_id);
2549 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2550 acpi_add_table(table_offsets, tables_blob);
2551 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2552 x86ms->oem_table_id);
2553 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2554 PCIDevice *pdev = PCI_DEVICE(iommu);
2555
2556 acpi_add_table(table_offsets, tables_blob);
2557 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2558 x86ms->oem_id, x86ms->oem_table_id);
2559 }
2560 if (machine->nvdimms_state->is_enabled) {
2561 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2562 machine->nvdimms_state, machine->ram_slots,
2563 x86ms->oem_id, x86ms->oem_table_id);
2564 }
2565 if (pcms->cxl_devices_state.is_enabled) {
2566 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2567 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2568 }
2569
2570 acpi_add_table(table_offsets, tables_blob);
2571 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2572
2573 /* Add tables supplied by user (if any) */
2574 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2575 unsigned len = acpi_table_len(u);
2576
2577 acpi_add_table(table_offsets, tables_blob);
2578 g_array_append_vals(tables_blob, u, len);
2579 }
2580
2581 /* RSDT is pointed to by RSDP */
2582 rsdt = tables_blob->len;
2583 build_rsdt(tables_blob, tables->linker, table_offsets,
2584 oem_id, oem_table_id);
2585
2586 /* RSDP is in FSEG memory, so allocate it separately */
2587 {
2588 AcpiRsdpData rsdp_data = {
2589 .revision = 0,
2590 .oem_id = x86ms->oem_id,
2591 .xsdt_tbl_offset = NULL,
2592 .rsdt_tbl_offset = &rsdt,
2593 };
2594 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2595 }
2596
2597 /* We'll expose it all to Guest so we want to reduce
2598 * chance of size changes.
2599 *
2600 * We used to align the tables to 4k, but of course this would
2601 * too simple to be enough. 4k turned out to be too small an
2602 * alignment very soon, and in fact it is almost impossible to
2603 * keep the table size stable for all (max_cpus, max_memory_slots)
2604 * combinations.
2605 */
2606 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2607
2608 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2609
2610 /* Cleanup memory that's no longer used. */
2611 g_array_free(table_offsets, true);
2612 g_free(slic_oem.id);
2613 g_free(slic_oem.table_id);
2614 }
2615
2616 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2617 {
2618 uint32_t size = acpi_data_len(data);
2619
2620 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2621 memory_region_ram_resize(mr, size, &error_abort);
2622
2623 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2624 memory_region_set_dirty(mr, 0, size);
2625 }
2626
2627 static void acpi_build_update(void *build_opaque)
2628 {
2629 AcpiBuildState *build_state = build_opaque;
2630 AcpiBuildTables tables;
2631
2632 /* No state to update or already patched? Nothing to do. */
2633 if (!build_state || build_state->patched) {
2634 return;
2635 }
2636 build_state->patched = 1;
2637
2638 acpi_build_tables_init(&tables);
2639
2640 acpi_build(&tables, MACHINE(qdev_get_machine()));
2641
2642 acpi_ram_update(build_state->table_mr, tables.table_data);
2643
2644 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2645
2646 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2647 acpi_build_tables_cleanup(&tables, true);
2648 }
2649
2650 static void acpi_build_reset(void *build_opaque)
2651 {
2652 AcpiBuildState *build_state = build_opaque;
2653 build_state->patched = 0;
2654 }
2655
2656 static const VMStateDescription vmstate_acpi_build = {
2657 .name = "acpi_build",
2658 .version_id = 1,
2659 .minimum_version_id = 1,
2660 .fields = (const VMStateField[]) {
2661 VMSTATE_UINT8(patched, AcpiBuildState),
2662 VMSTATE_END_OF_LIST()
2663 },
2664 };
2665
2666 void acpi_setup(void)
2667 {
2668 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2669 X86MachineState *x86ms = X86_MACHINE(pcms);
2670 AcpiBuildTables tables;
2671 AcpiBuildState *build_state;
2672 Object *vmgenid_dev;
2673 #ifdef CONFIG_TPM
2674 TPMIf *tpm;
2675 static FwCfgTPMConfig tpm_config;
2676 #endif
2677
2678 if (!x86ms->fw_cfg) {
2679 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2680 return;
2681 }
2682
2683 if (!pcms->acpi_build_enabled) {
2684 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2685 return;
2686 }
2687
2688 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2689 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2690 return;
2691 }
2692
2693 build_state = g_malloc0(sizeof *build_state);
2694
2695 acpi_build_tables_init(&tables);
2696 acpi_build(&tables, MACHINE(pcms));
2697
2698 /* Now expose it all to Guest */
2699 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2700 build_state, tables.table_data,
2701 ACPI_BUILD_TABLE_FILE);
2702 assert(build_state->table_mr != NULL);
2703
2704 build_state->linker_mr =
2705 acpi_add_rom_blob(acpi_build_update, build_state,
2706 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2707
2708 #ifdef CONFIG_TPM
2709 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2710 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2711
2712 tpm = tpm_find();
2713 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2714 tpm_config = (FwCfgTPMConfig) {
2715 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2716 .tpm_version = tpm_get_version(tpm),
2717 .tpmppi_version = TPM_PPI_VERSION_1_30
2718 };
2719 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2720 &tpm_config, sizeof tpm_config);
2721 }
2722 #endif
2723
2724 vmgenid_dev = find_vmgenid_dev();
2725 if (vmgenid_dev) {
2726 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2727 tables.vmgenid);
2728 }
2729
2730 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2731 build_state, tables.rsdp,
2732 ACPI_BUILD_RSDP_FILE);
2733
2734 qemu_register_reset(acpi_build_reset, build_state);
2735 acpi_build_reset(build_state);
2736 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2737
2738 /* Cleanup tables but don't free the memory: we track it
2739 * in build_state.
2740 */
2741 acpi_build_tables_cleanup(&tables, false);
2742 }
Random patches