hw/core/machine.c

   1 /*
   2  * QEMU Machine
   3  *
   4  * Copyright (C) 2014 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel.a@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/option.h"
  15 #include "qapi/qmp/qerror.h"
  16 #include "sysemu/replay.h"
  17 #include "qemu/units.h"
  18 #include "hw/boards.h"
  19 #include "hw/loader.h"
  20 #include "qapi/error.h"
  21 #include "qapi/qapi-visit-common.h"
  22 #include "qapi/qapi-visit-machine.h"
  23 #include "qapi/visitor.h"
  24 #include "qom/object_interfaces.h"
  25 #include "hw/sysbus.h"
  26 #include "sysemu/cpus.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/reset.h"
  29 #include "sysemu/runstate.h"
  30 #include "sysemu/numa.h"
  31 #include "sysemu/xen.h"
  32 #include "qemu/error-report.h"
  33 #include "sysemu/qtest.h"
  34 #include "hw/pci/pci.h"
  35 #include "hw/mem/nvdimm.h"
  36 #include "migration/global_state.h"
  37 #include "migration/vmstate.h"
  38 #include "exec/confidential-guest-support.h"
  39 #include "hw/virtio/virtio.h"
  40 #include "hw/virtio/virtio-pci.h"
  41 #include "qom/object_interfaces.h"
  42
  43 GlobalProperty hw_compat_7_1[] = {
  44     { "virtio-device", "queue_reset", "false" },
  45 };
  46 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1);
  47
  48 GlobalProperty hw_compat_7_0[] = {
  49     { "arm-gicv3-common", "force-8-bit-prio", "on" },
  50     { "nvme-ns", "eui64-default", "on"},
  51 };
  52 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
  53
  54 GlobalProperty hw_compat_6_2[] = {
  55     { "PIIX4_PM", "x-not-migrate-acpi-index", "on"},
  56 };
  57 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2);
  58
  59 GlobalProperty hw_compat_6_1[] = {
  60     { "vhost-user-vsock-device", "seqpacket", "off" },
  61     { "nvme-ns", "shared", "off" },
  62 };
  63 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
  64
  65 GlobalProperty hw_compat_6_0[] = {
  66     { "gpex-pcihost", "allow-unmapped-accesses", "false" },
  67     { "i8042", "extended-state", "false"},
  68     { "nvme-ns", "eui64-default", "off"},
  69     { "e1000", "init-vet", "off" },
  70     { "e1000e", "init-vet", "off" },
  71     { "vhost-vsock-device", "seqpacket", "off" },
  72 };
  73 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
  74
  75 GlobalProperty hw_compat_5_2[] = {
  76     { "ICH9-LPC", "smm-compat", "on"},
  77     { "PIIX4_PM", "smm-compat", "on"},
  78     { "virtio-blk-device", "report-discard-granularity", "off" },
  79     { "virtio-net-pci-base", "vectors", "3"},
  80 };
  81 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
  82
  83 GlobalProperty hw_compat_5_1[] = {
  84     { "vhost-scsi", "num_queues", "1"},
  85     { "vhost-user-blk", "num-queues", "1"},
  86     { "vhost-user-scsi", "num_queues", "1"},
  87     { "virtio-blk-device", "num-queues", "1"},
  88     { "virtio-scsi-device", "num_queues", "1"},
  89     { "nvme", "use-intel-id", "on"},
  90     { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
  91     { "pl011", "migrate-clk", "off" },
  92     { "virtio-pci", "x-ats-page-aligned", "off"},
  93 };
  94 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
  95
  96 GlobalProperty hw_compat_5_0[] = {
  97     { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
  98     { "virtio-balloon-device", "page-poison", "false" },
  99     { "vmport", "x-read-set-eax", "off" },
 100     { "vmport", "x-signal-unsupported-cmd", "off" },
 101     { "vmport", "x-report-vmx-type", "off" },
 102     { "vmport", "x-cmds-v2", "off" },
 103     { "virtio-device", "x-disable-legacy-check", "true" },
 104 };
 105 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
 106
 107 GlobalProperty hw_compat_4_2[] = {
 108     { "virtio-blk-device", "queue-size", "128"},
 109     { "virtio-scsi-device", "virtqueue_size", "128"},
 110     { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
 111     { "virtio-blk-device", "seg-max-adjust", "off"},
 112     { "virtio-scsi-device", "seg_max_adjust", "off"},
 113     { "vhost-blk-device", "seg_max_adjust", "off"},
 114     { "usb-host", "suppress-remote-wake", "off" },
 115     { "usb-redir", "suppress-remote-wake", "off" },
 116     { "qxl", "revision", "4" },
 117     { "qxl-vga", "revision", "4" },
 118     { "fw_cfg", "acpi-mr-restore", "false" },
 119     { "virtio-device", "use-disabled-flag", "false" },
 120 };
 121 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
 122
 123 GlobalProperty hw_compat_4_1[] = {
 124     { "virtio-pci", "x-pcie-flr-init", "off" },
 125 };
 126 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
 127
 128 GlobalProperty hw_compat_4_0[] = {
 129     { "VGA",            "edid", "false" },
 130     { "secondary-vga",  "edid", "false" },
 131     { "bochs-display",  "edid", "false" },
 132     { "virtio-vga",     "edid", "false" },
 133     { "virtio-gpu-device", "edid", "false" },
 134     { "virtio-device", "use-started", "false" },
 135     { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
 136     { "pl031", "migrate-tick-offset", "false" },
 137 };
 138 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
 139
 140 GlobalProperty hw_compat_3_1[] = {
 141     { "pcie-root-port", "x-speed", "2_5" },
 142     { "pcie-root-port", "x-width", "1" },
 143     { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
 144     { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
 145     { "tpm-crb", "ppi", "false" },
 146     { "tpm-tis", "ppi", "false" },
 147     { "usb-kbd", "serial", "42" },
 148     { "usb-mouse", "serial", "42" },
 149     { "usb-tablet", "serial", "42" },
 150     { "virtio-blk-device", "discard", "false" },
 151     { "virtio-blk-device", "write-zeroes", "false" },
 152     { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
 153     { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
 154 };
 155 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
 156
 157 GlobalProperty hw_compat_3_0[] = {};
 158 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
 159
 160 GlobalProperty hw_compat_2_12[] = {
 161     { "migration", "decompress-error-check", "off" },
 162     { "hda-audio", "use-timer", "false" },
 163     { "cirrus-vga", "global-vmstate", "true" },
 164     { "VGA", "global-vmstate", "true" },
 165     { "vmware-svga", "global-vmstate", "true" },
 166     { "qxl-vga", "global-vmstate", "true" },
 167 };
 168 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
 169
 170 GlobalProperty hw_compat_2_11[] = {
 171     { "hpet", "hpet-offset-saved", "false" },
 172     { "virtio-blk-pci", "vectors", "2" },
 173     { "vhost-user-blk-pci", "vectors", "2" },
 174     { "e1000", "migrate_tso_props", "off" },
 175 };
 176 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
 177
 178 GlobalProperty hw_compat_2_10[] = {
 179     { "virtio-mouse-device", "wheel-axis", "false" },
 180     { "virtio-tablet-device", "wheel-axis", "false" },
 181 };
 182 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
 183
 184 GlobalProperty hw_compat_2_9[] = {
 185     { "pci-bridge", "shpc", "off" },
 186     { "intel-iommu", "pt", "off" },
 187     { "virtio-net-device", "x-mtu-bypass-backend", "off" },
 188     { "pcie-root-port", "x-migrate-msix", "false" },
 189 };
 190 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
 191
 192 GlobalProperty hw_compat_2_8[] = {
 193     { "fw_cfg_mem", "x-file-slots", "0x10" },
 194     { "fw_cfg_io", "x-file-slots", "0x10" },
 195     { "pflash_cfi01", "old-multiple-chip-handling", "on" },
 196     { "pci-bridge", "shpc", "on" },
 197     { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
 198     { "virtio-pci", "x-pcie-deverr-init", "off" },
 199     { "virtio-pci", "x-pcie-lnkctl-init", "off" },
 200     { "virtio-pci", "x-pcie-pm-init", "off" },
 201     { "cirrus-vga", "vgamem_mb", "8" },
 202     { "isa-cirrus-vga", "vgamem_mb", "8" },
 203 };
 204 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
 205
 206 GlobalProperty hw_compat_2_7[] = {
 207     { "virtio-pci", "page-per-vq", "on" },
 208     { "virtio-serial-device", "emergency-write", "off" },
 209     { "ioapic", "version", "0x11" },
 210     { "intel-iommu", "x-buggy-eim", "true" },
 211     { "virtio-pci", "x-ignore-backend-features", "on" },
 212 };
 213 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
 214
 215 GlobalProperty hw_compat_2_6[] = {
 216     { "virtio-mmio", "format_transport_address", "off" },
 217     /* Optional because not all virtio-pci devices support legacy mode */
 218     { "virtio-pci", "disable-modern", "on",  .optional = true },
 219     { "virtio-pci", "disable-legacy", "off", .optional = true },
 220 };
 221 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
 222
 223 GlobalProperty hw_compat_2_5[] = {
 224     { "isa-fdc", "fallback", "144" },
 225     { "pvscsi", "x-old-pci-configuration", "on" },
 226     { "pvscsi", "x-disable-pcie", "on" },
 227     { "vmxnet3", "x-old-msi-offsets", "on" },
 228     { "vmxnet3", "x-disable-pcie", "on" },
 229 };
 230 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
 231
 232 GlobalProperty hw_compat_2_4[] = {
 233     /* Optional because the 'scsi' property is Linux-only */
 234     { "virtio-blk-device", "scsi", "true", .optional = true },
 235     { "e1000", "extra_mac_registers", "off" },
 236     { "virtio-pci", "x-disable-pcie", "on" },
 237     { "virtio-pci", "migrate-extra", "off" },
 238     { "fw_cfg_mem", "dma_enabled", "off" },
 239     { "fw_cfg_io", "dma_enabled", "off" }
 240 };
 241 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
 242
 243 GlobalProperty hw_compat_2_3[] = {
 244     { "virtio-blk-pci", "any_layout", "off" },
 245     { "virtio-balloon-pci", "any_layout", "off" },
 246     { "virtio-serial-pci", "any_layout", "off" },
 247     { "virtio-9p-pci", "any_layout", "off" },
 248     { "virtio-rng-pci", "any_layout", "off" },
 249     { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
 250     { "migration", "send-configuration", "off" },
 251     { "migration", "send-section-footer", "off" },
 252     { "migration", "store-global-state", "off" },
 253 };
 254 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
 255
 256 GlobalProperty hw_compat_2_2[] = {};
 257 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
 258
 259 GlobalProperty hw_compat_2_1[] = {
 260     { "intel-hda", "old_msi_addr", "on" },
 261     { "VGA", "qemu-extended-regs", "off" },
 262     { "secondary-vga", "qemu-extended-regs", "off" },
 263     { "virtio-scsi-pci", "any_layout", "off" },
 264     { "usb-mouse", "usb_version", "1" },
 265     { "usb-kbd", "usb_version", "1" },
 266     { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
 267 };
 268 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
 269
 270 MachineState *current_machine;
 271
 272 static char *machine_get_kernel(Object *obj, Error **errp)
 273 {
 274     MachineState *ms = MACHINE(obj);
 275
 276     return g_strdup(ms->kernel_filename);
 277 }
 278
 279 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
 280 {
 281     MachineState *ms = MACHINE(obj);
 282
 283     g_free(ms->kernel_filename);
 284     ms->kernel_filename = g_strdup(value);
 285 }
 286
 287 static char *machine_get_initrd(Object *obj, Error **errp)
 288 {
 289     MachineState *ms = MACHINE(obj);
 290
 291     return g_strdup(ms->initrd_filename);
 292 }
 293
 294 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
 295 {
 296     MachineState *ms = MACHINE(obj);
 297
 298     g_free(ms->initrd_filename);
 299     ms->initrd_filename = g_strdup(value);
 300 }
 301
 302 static char *machine_get_append(Object *obj, Error **errp)
 303 {
 304     MachineState *ms = MACHINE(obj);
 305
 306     return g_strdup(ms->kernel_cmdline);
 307 }
 308
 309 static void machine_set_append(Object *obj, const char *value, Error **errp)
 310 {
 311     MachineState *ms = MACHINE(obj);
 312
 313     g_free(ms->kernel_cmdline);
 314     ms->kernel_cmdline = g_strdup(value);
 315 }
 316
 317 static char *machine_get_dtb(Object *obj, Error **errp)
 318 {
 319     MachineState *ms = MACHINE(obj);
 320
 321     return g_strdup(ms->dtb);
 322 }
 323
 324 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
 325 {
 326     MachineState *ms = MACHINE(obj);
 327
 328     g_free(ms->dtb);
 329     ms->dtb = g_strdup(value);
 330 }
 331
 332 static char *machine_get_dumpdtb(Object *obj, Error **errp)
 333 {
 334     MachineState *ms = MACHINE(obj);
 335
 336     return g_strdup(ms->dumpdtb);
 337 }
 338
 339 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
 340 {
 341     MachineState *ms = MACHINE(obj);
 342
 343     g_free(ms->dumpdtb);
 344     ms->dumpdtb = g_strdup(value);
 345 }
 346
 347 static void machine_get_phandle_start(Object *obj, Visitor *v,
 348                                       const char *name, void *opaque,
 349                                       Error **errp)
 350 {
 351     MachineState *ms = MACHINE(obj);
 352     int64_t value = ms->phandle_start;
 353
 354     visit_type_int(v, name, &value, errp);
 355 }
 356
 357 static void machine_set_phandle_start(Object *obj, Visitor *v,
 358                                       const char *name, void *opaque,
 359                                       Error **errp)
 360 {
 361     MachineState *ms = MACHINE(obj);
 362     int64_t value;
 363
 364     if (!visit_type_int(v, name, &value, errp)) {
 365         return;
 366     }
 367
 368     ms->phandle_start = value;
 369 }
 370
 371 static char *machine_get_dt_compatible(Object *obj, Error **errp)
 372 {
 373     MachineState *ms = MACHINE(obj);
 374
 375     return g_strdup(ms->dt_compatible);
 376 }
 377
 378 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
 379 {
 380     MachineState *ms = MACHINE(obj);
 381
 382     g_free(ms->dt_compatible);
 383     ms->dt_compatible = g_strdup(value);
 384 }
 385
 386 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
 387 {
 388     MachineState *ms = MACHINE(obj);
 389
 390     return ms->dump_guest_core;
 391 }
 392
 393 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
 394 {
 395     MachineState *ms = MACHINE(obj);
 396
 397     ms->dump_guest_core = value;
 398 }
 399
 400 static bool machine_get_mem_merge(Object *obj, Error **errp)
 401 {
 402     MachineState *ms = MACHINE(obj);
 403
 404     return ms->mem_merge;
 405 }
 406
 407 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
 408 {
 409     MachineState *ms = MACHINE(obj);
 410
 411     ms->mem_merge = value;
 412 }
 413
 414 static bool machine_get_usb(Object *obj, Error **errp)
 415 {
 416     MachineState *ms = MACHINE(obj);
 417
 418     return ms->usb;
 419 }
 420
 421 static void machine_set_usb(Object *obj, bool value, Error **errp)
 422 {
 423     MachineState *ms = MACHINE(obj);
 424
 425     ms->usb = value;
 426     ms->usb_disabled = !value;
 427 }
 428
 429 static bool machine_get_graphics(Object *obj, Error **errp)
 430 {
 431     MachineState *ms = MACHINE(obj);
 432
 433     return ms->enable_graphics;
 434 }
 435
 436 static void machine_set_graphics(Object *obj, bool value, Error **errp)
 437 {
 438     MachineState *ms = MACHINE(obj);
 439
 440     ms->enable_graphics = value;
 441 }
 442
 443 static char *machine_get_firmware(Object *obj, Error **errp)
 444 {
 445     MachineState *ms = MACHINE(obj);
 446
 447     return g_strdup(ms->firmware);
 448 }
 449
 450 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
 451 {
 452     MachineState *ms = MACHINE(obj);
 453
 454     g_free(ms->firmware);
 455     ms->firmware = g_strdup(value);
 456 }
 457
 458 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
 459 {
 460     MachineState *ms = MACHINE(obj);
 461
 462     ms->suppress_vmdesc = value;
 463 }
 464
 465 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
 466 {
 467     MachineState *ms = MACHINE(obj);
 468
 469     return ms->suppress_vmdesc;
 470 }
 471
 472 static char *machine_get_memory_encryption(Object *obj, Error **errp)
 473 {
 474     MachineState *ms = MACHINE(obj);
 475
 476     if (ms->cgs) {
 477         return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
 478     }
 479
 480     return NULL;
 481 }
 482
 483 static void machine_set_memory_encryption(Object *obj, const char *value,
 484                                         Error **errp)
 485 {
 486     Object *cgs =
 487         object_resolve_path_component(object_get_objects_root(), value);
 488
 489     if (!cgs) {
 490         error_setg(errp, "No such memory encryption object '%s'", value);
 491         return;
 492     }
 493
 494     object_property_set_link(obj, "confidential-guest-support", cgs, errp);
 495 }
 496
 497 static void machine_check_confidential_guest_support(const Object *obj,
 498                                                      const char *name,
 499                                                      Object *new_target,
 500                                                      Error **errp)
 501 {
 502     /*
 503      * So far the only constraint is that the target has the
 504      * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
 505      * by the QOM core
 506      */
 507 }
 508
 509 static bool machine_get_nvdimm(Object *obj, Error **errp)
 510 {
 511     MachineState *ms = MACHINE(obj);
 512
 513     return ms->nvdimms_state->is_enabled;
 514 }
 515
 516 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
 517 {
 518     MachineState *ms = MACHINE(obj);
 519
 520     ms->nvdimms_state->is_enabled = value;
 521 }
 522
 523 static bool machine_get_hmat(Object *obj, Error **errp)
 524 {
 525     MachineState *ms = MACHINE(obj);
 526
 527     return ms->numa_state->hmat_enabled;
 528 }
 529
 530 static void machine_set_hmat(Object *obj, bool value, Error **errp)
 531 {
 532     MachineState *ms = MACHINE(obj);
 533
 534     ms->numa_state->hmat_enabled = value;
 535 }
 536
 537 static void machine_get_mem(Object *obj, Visitor *v, const char *name,
 538                             void *opaque, Error **errp)
 539 {
 540     MachineState *ms = MACHINE(obj);
 541     MemorySizeConfiguration mem = {
 542         .has_size = true,
 543         .size = ms->ram_size,
 544         .has_max_size = !!ms->ram_slots,
 545         .max_size = ms->maxram_size,
 546         .has_slots = !!ms->ram_slots,
 547         .slots = ms->ram_slots,
 548     };
 549     MemorySizeConfiguration *p_mem = &mem;
 550
 551     visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort);
 552 }
 553
 554 static void machine_set_mem(Object *obj, Visitor *v, const char *name,
 555                             void *opaque, Error **errp)
 556 {
 557     MachineState *ms = MACHINE(obj);
 558     MachineClass *mc = MACHINE_GET_CLASS(obj);
 559     MemorySizeConfiguration *mem;
 560
 561     ERRP_GUARD();
 562
 563     if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) {
 564         return;
 565     }
 566
 567     if (!mem->has_size) {
 568         mem->has_size = true;
 569         mem->size = mc->default_ram_size;
 570     }
 571     mem->size = QEMU_ALIGN_UP(mem->size, 8192);
 572     if (mc->fixup_ram_size) {
 573         mem->size = mc->fixup_ram_size(mem->size);
 574     }
 575     if ((ram_addr_t)mem->size != mem->size) {
 576         error_setg(errp, "ram size too large");
 577         goto out_free;
 578     }
 579
 580     if (mem->has_max_size) {
 581         if (mem->max_size < mem->size) {
 582             error_setg(errp, "invalid value of maxmem: "
 583                        "maximum memory size (0x%" PRIx64 ") must be at least "
 584                        "the initial memory size (0x%" PRIx64 ")",
 585                        mem->max_size, mem->size);
 586             goto out_free;
 587         }
 588         if (mem->has_slots && mem->slots && mem->max_size == mem->size) {
 589             error_setg(errp, "invalid value of maxmem: "
 590                        "memory slots were specified but maximum memory size "
 591                        "(0x%" PRIx64 ") is equal to the initial memory size "
 592                        "(0x%" PRIx64 ")", mem->max_size, mem->size);
 593             goto out_free;
 594         }
 595         ms->maxram_size = mem->max_size;
 596     } else {
 597         if (mem->has_slots) {
 598             error_setg(errp, "slots specified but no max-size");
 599             goto out_free;
 600         }
 601         ms->maxram_size = mem->size;
 602     }
 603     ms->ram_size = mem->size;
 604     ms->ram_slots = mem->has_slots ? mem->slots : 0;
 605 out_free:
 606     qapi_free_MemorySizeConfiguration(mem);
 607 }
 608
 609 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
 610 {
 611     MachineState *ms = MACHINE(obj);
 612
 613     return g_strdup(ms->nvdimms_state->persistence_string);
 614 }
 615
 616 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
 617                                            Error **errp)
 618 {
 619     MachineState *ms = MACHINE(obj);
 620     NVDIMMState *nvdimms_state = ms->nvdimms_state;
 621
 622     if (strcmp(value, "cpu") == 0) {
 623         nvdimms_state->persistence = 3;
 624     } else if (strcmp(value, "mem-ctrl") == 0) {
 625         nvdimms_state->persistence = 2;
 626     } else {
 627         error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
 628                    value);
 629         return;
 630     }
 631
 632     g_free(nvdimms_state->persistence_string);
 633     nvdimms_state->persistence_string = g_strdup(value);
 634 }
 635
 636 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
 637 {
 638     QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
 639 }
 640
 641 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
 642 {
 643     Object *obj = OBJECT(dev);
 644
 645     if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
 646         return false;
 647     }
 648
 649     return device_type_is_dynamic_sysbus(mc, object_get_typename(obj));
 650 }
 651
 652 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type)
 653 {
 654     bool allowed = false;
 655     strList *wl;
 656     ObjectClass *klass = object_class_by_name(type);
 657
 658     for (wl = mc->allowed_dynamic_sysbus_devices;
 659          !allowed && wl;
 660          wl = wl->next) {
 661         allowed |= !!object_class_dynamic_cast(klass, wl->value);
 662     }
 663
 664     return allowed;
 665 }
 666
 667 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
 668 {
 669     int i;
 670     HotpluggableCPUList *head = NULL;
 671     MachineClass *mc = MACHINE_GET_CLASS(machine);
 672
 673     /* force board to initialize possible_cpus if it hasn't been done yet */
 674     mc->possible_cpu_arch_ids(machine);
 675
 676     for (i = 0; i < machine->possible_cpus->len; i++) {
 677         Object *cpu;
 678         HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
 679
 680         cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
 681         cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
 682         cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
 683                                    sizeof(*cpu_item->props));
 684
 685         cpu = machine->possible_cpus->cpus[i].cpu;
 686         if (cpu) {
 687             cpu_item->has_qom_path = true;
 688             cpu_item->qom_path = object_get_canonical_path(cpu);
 689         }
 690         QAPI_LIST_PREPEND(head, cpu_item);
 691     }
 692     return head;
 693 }
 694
 695 /**
 696  * machine_set_cpu_numa_node:
 697  * @machine: machine object to modify
 698  * @props: specifies which cpu objects to assign to
 699  *         numa node specified by @props.node_id
 700  * @errp: if an error occurs, a pointer to an area to store the error
 701  *
 702  * Associate NUMA node specified by @props.node_id with cpu slots that
 703  * match socket/core/thread-ids specified by @props. It's recommended to use
 704  * query-hotpluggable-cpus.props values to specify affected cpu slots,
 705  * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
 706  *
 707  * However for CLI convenience it's possible to pass in subset of properties,
 708  * which would affect all cpu slots that match it.
 709  * Ex for pc machine:
 710  *    -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
 711  *    -numa cpu,node-id=0,socket_id=0 \
 712  *    -numa cpu,node-id=1,socket_id=1
 713  * will assign all child cores of socket 0 to node 0 and
 714  * of socket 1 to node 1.
 715  *
 716  * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
 717  * return error.
 718  * Empty subset is disallowed and function will return with error in this case.
 719  */
 720 void machine_set_cpu_numa_node(MachineState *machine,
 721                                const CpuInstanceProperties *props, Error **errp)
 722 {
 723     MachineClass *mc = MACHINE_GET_CLASS(machine);
 724     NodeInfo *numa_info = machine->numa_state->nodes;
 725     bool match = false;
 726     int i;
 727
 728     if (!mc->possible_cpu_arch_ids) {
 729         error_setg(errp, "mapping of CPUs to NUMA node is not supported");
 730         return;
 731     }
 732
 733     /* disabling node mapping is not supported, forbid it */
 734     assert(props->has_node_id);
 735
 736     /* force board to initialize possible_cpus if it hasn't been done yet */
 737     mc->possible_cpu_arch_ids(machine);
 738
 739     for (i = 0; i < machine->possible_cpus->len; i++) {
 740         CPUArchId *slot = &machine->possible_cpus->cpus[i];
 741
 742         /* reject unsupported by board properties */
 743         if (props->has_thread_id && !slot->props.has_thread_id) {
 744             error_setg(errp, "thread-id is not supported");
 745             return;
 746         }
 747
 748         if (props->has_core_id && !slot->props.has_core_id) {
 749             error_setg(errp, "core-id is not supported");
 750             return;
 751         }
 752
 753         if (props->has_cluster_id && !slot->props.has_cluster_id) {
 754             error_setg(errp, "cluster-id is not supported");
 755             return;
 756         }
 757
 758         if (props->has_socket_id && !slot->props.has_socket_id) {
 759             error_setg(errp, "socket-id is not supported");
 760             return;
 761         }
 762
 763         if (props->has_die_id && !slot->props.has_die_id) {
 764             error_setg(errp, "die-id is not supported");
 765             return;
 766         }
 767
 768         /* skip slots with explicit mismatch */
 769         if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
 770                 continue;
 771         }
 772
 773         if (props->has_core_id && props->core_id != slot->props.core_id) {
 774                 continue;
 775         }
 776
 777         if (props->has_cluster_id &&
 778             props->cluster_id != slot->props.cluster_id) {
 779                 continue;
 780         }
 781
 782         if (props->has_die_id && props->die_id != slot->props.die_id) {
 783                 continue;
 784         }
 785
 786         if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
 787                 continue;
 788         }
 789
 790         /* reject assignment if slot is already assigned, for compatibility
 791          * of legacy cpu_index mapping with SPAPR core based mapping do not
 792          * error out if cpu thread and matched core have the same node-id */
 793         if (slot->props.has_node_id &&
 794             slot->props.node_id != props->node_id) {
 795             error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
 796                        slot->props.node_id);
 797             return;
 798         }
 799
 800         /* assign slot to node as it's matched '-numa cpu' key */
 801         match = true;
 802         slot->props.node_id = props->node_id;
 803         slot->props.has_node_id = props->has_node_id;
 804
 805         if (machine->numa_state->hmat_enabled) {
 806             if ((numa_info[props->node_id].initiator < MAX_NODES) &&
 807                 (props->node_id != numa_info[props->node_id].initiator)) {
 808                 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
 809                            " should be itself (got %" PRIu16 ")",
 810                            props->node_id, numa_info[props->node_id].initiator);
 811                 return;
 812             }
 813             numa_info[props->node_id].has_cpu = true;
 814             numa_info[props->node_id].initiator = props->node_id;
 815         }
 816     }
 817
 818     if (!match) {
 819         error_setg(errp, "no match found");
 820     }
 821 }
 822
 823 static void machine_get_smp(Object *obj, Visitor *v, const char *name,
 824                             void *opaque, Error **errp)
 825 {
 826     MachineState *ms = MACHINE(obj);
 827     SMPConfiguration *config = &(SMPConfiguration){
 828         .has_cpus = true, .cpus = ms->smp.cpus,
 829         .has_sockets = true, .sockets = ms->smp.sockets,
 830         .has_dies = true, .dies = ms->smp.dies,
 831         .has_clusters = true, .clusters = ms->smp.clusters,
 832         .has_cores = true, .cores = ms->smp.cores,
 833         .has_threads = true, .threads = ms->smp.threads,
 834         .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
 835     };
 836
 837     if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
 838         return;
 839     }
 840 }
 841
 842 static void machine_set_smp(Object *obj, Visitor *v, const char *name,
 843                             void *opaque, Error **errp)
 844 {
 845     MachineState *ms = MACHINE(obj);
 846     g_autoptr(SMPConfiguration) config = NULL;
 847
 848     if (!visit_type_SMPConfiguration(v, name, &config, errp)) {
 849         return;
 850     }
 851
 852     machine_parse_smp_config(ms, config, errp);
 853 }
 854
 855 static void machine_get_boot(Object *obj, Visitor *v, const char *name,
 856                             void *opaque, Error **errp)
 857 {
 858     MachineState *ms = MACHINE(obj);
 859     BootConfiguration *config = &ms->boot_config;
 860     visit_type_BootConfiguration(v, name, &config, &error_abort);
 861 }
 862
 863 static void machine_free_boot_config(MachineState *ms)
 864 {
 865     g_free(ms->boot_config.order);
 866     g_free(ms->boot_config.once);
 867     g_free(ms->boot_config.splash);
 868 }
 869
 870 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config)
 871 {
 872     MachineClass *machine_class = MACHINE_GET_CLASS(ms);
 873
 874     machine_free_boot_config(ms);
 875     ms->boot_config = *config;
 876     if (!config->has_order) {
 877         ms->boot_config.has_order = true;
 878         ms->boot_config.order = g_strdup(machine_class->default_boot_order);
 879     }
 880 }
 881
 882 static void machine_set_boot(Object *obj, Visitor *v, const char *name,
 883                             void *opaque, Error **errp)
 884 {
 885     ERRP_GUARD();
 886     MachineState *ms = MACHINE(obj);
 887     BootConfiguration *config = NULL;
 888
 889     if (!visit_type_BootConfiguration(v, name, &config, errp)) {
 890         return;
 891     }
 892     if (config->has_order) {
 893         validate_bootdevices(config->order, errp);
 894         if (*errp) {
 895             goto out_free;
 896         }
 897     }
 898     if (config->has_once) {
 899         validate_bootdevices(config->once, errp);
 900         if (*errp) {
 901             goto out_free;
 902         }
 903     }
 904
 905     machine_copy_boot_config(ms, config);
 906     /* Strings live in ms->boot_config.  */
 907     free(config);
 908     return;
 909
 910 out_free:
 911     qapi_free_BootConfiguration(config);
 912 }
 913
 914 static void machine_class_init(ObjectClass *oc, void *data)
 915 {
 916     MachineClass *mc = MACHINE_CLASS(oc);
 917
 918     /* Default 128 MB as guest ram size */
 919     mc->default_ram_size = 128 * MiB;
 920     mc->rom_file_has_mr = true;
 921
 922     /* numa node memory size aligned on 8MB by default.
 923      * On Linux, each node's border has to be 8MB aligned
 924      */
 925     mc->numa_mem_align_shift = 23;
 926
 927     object_class_property_add_str(oc, "kernel",
 928         machine_get_kernel, machine_set_kernel);
 929     object_class_property_set_description(oc, "kernel",
 930         "Linux kernel image file");
 931
 932     object_class_property_add_str(oc, "initrd",
 933         machine_get_initrd, machine_set_initrd);
 934     object_class_property_set_description(oc, "initrd",
 935         "Linux initial ramdisk file");
 936
 937     object_class_property_add_str(oc, "append",
 938         machine_get_append, machine_set_append);
 939     object_class_property_set_description(oc, "append",
 940         "Linux kernel command line");
 941
 942     object_class_property_add_str(oc, "dtb",
 943         machine_get_dtb, machine_set_dtb);
 944     object_class_property_set_description(oc, "dtb",
 945         "Linux kernel device tree file");
 946
 947     object_class_property_add_str(oc, "dumpdtb",
 948         machine_get_dumpdtb, machine_set_dumpdtb);
 949     object_class_property_set_description(oc, "dumpdtb",
 950         "Dump current dtb to a file and quit");
 951
 952     object_class_property_add(oc, "boot", "BootConfiguration",
 953         machine_get_boot, machine_set_boot,
 954         NULL, NULL);
 955     object_class_property_set_description(oc, "boot",
 956         "Boot configuration");
 957
 958     object_class_property_add(oc, "smp", "SMPConfiguration",
 959         machine_get_smp, machine_set_smp,
 960         NULL, NULL);
 961     object_class_property_set_description(oc, "smp",
 962         "CPU topology");
 963
 964     object_class_property_add(oc, "phandle-start", "int",
 965         machine_get_phandle_start, machine_set_phandle_start,
 966         NULL, NULL);
 967     object_class_property_set_description(oc, "phandle-start",
 968         "The first phandle ID we may generate dynamically");
 969
 970     object_class_property_add_str(oc, "dt-compatible",
 971         machine_get_dt_compatible, machine_set_dt_compatible);
 972     object_class_property_set_description(oc, "dt-compatible",
 973         "Overrides the \"compatible\" property of the dt root node");
 974
 975     object_class_property_add_bool(oc, "dump-guest-core",
 976         machine_get_dump_guest_core, machine_set_dump_guest_core);
 977     object_class_property_set_description(oc, "dump-guest-core",
 978         "Include guest memory in a core dump");
 979
 980     object_class_property_add_bool(oc, "mem-merge",
 981         machine_get_mem_merge, machine_set_mem_merge);
 982     object_class_property_set_description(oc, "mem-merge",
 983         "Enable/disable memory merge support");
 984
 985     object_class_property_add_bool(oc, "usb",
 986         machine_get_usb, machine_set_usb);
 987     object_class_property_set_description(oc, "usb",
 988         "Set on/off to enable/disable usb");
 989
 990     object_class_property_add_bool(oc, "graphics",
 991         machine_get_graphics, machine_set_graphics);
 992     object_class_property_set_description(oc, "graphics",
 993         "Set on/off to enable/disable graphics emulation");
 994
 995     object_class_property_add_str(oc, "firmware",
 996         machine_get_firmware, machine_set_firmware);
 997     object_class_property_set_description(oc, "firmware",
 998         "Firmware image");
 999
1000     object_class_property_add_bool(oc, "suppress-vmdesc",
1001         machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
1002     object_class_property_set_description(oc, "suppress-vmdesc",
1003         "Set on to disable self-describing migration");
1004
1005     object_class_property_add_link(oc, "confidential-guest-support",
1006                                    TYPE_CONFIDENTIAL_GUEST_SUPPORT,
1007                                    offsetof(MachineState, cgs),
1008                                    machine_check_confidential_guest_support,
1009                                    OBJ_PROP_LINK_STRONG);
1010     object_class_property_set_description(oc, "confidential-guest-support",
1011                                           "Set confidential guest scheme to support");
1012
1013     /* For compatibility */
1014     object_class_property_add_str(oc, "memory-encryption",
1015         machine_get_memory_encryption, machine_set_memory_encryption);
1016     object_class_property_set_description(oc, "memory-encryption",
1017         "Set memory encryption object to use");
1018
1019     object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND,
1020                                    offsetof(MachineState, memdev), object_property_allow_set_link,
1021                                    OBJ_PROP_LINK_STRONG);
1022     object_class_property_set_description(oc, "memory-backend",
1023                                           "Set RAM backend"
1024                                           "Valid value is ID of hostmem based backend");
1025
1026     object_class_property_add(oc, "memory", "MemorySizeConfiguration",
1027         machine_get_mem, machine_set_mem,
1028         NULL, NULL);
1029     object_class_property_set_description(oc, "memory",
1030         "Memory size configuration");
1031 }
1032
1033 static void machine_class_base_init(ObjectClass *oc, void *data)
1034 {
1035     MachineClass *mc = MACHINE_CLASS(oc);
1036     mc->max_cpus = mc->max_cpus ?: 1;
1037     mc->min_cpus = mc->min_cpus ?: 1;
1038     mc->default_cpus = mc->default_cpus ?: 1;
1039
1040     if (!object_class_is_abstract(oc)) {
1041         const char *cname = object_class_get_name(oc);
1042         assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
1043         mc->name = g_strndup(cname,
1044                             strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
1045         mc->compat_props = g_ptr_array_new();
1046     }
1047 }
1048
1049 static void machine_initfn(Object *obj)
1050 {
1051     MachineState *ms = MACHINE(obj);
1052     MachineClass *mc = MACHINE_GET_CLASS(obj);
1053
1054     container_get(obj, "/peripheral");
1055     container_get(obj, "/peripheral-anon");
1056
1057     ms->dump_guest_core = true;
1058     ms->mem_merge = true;
1059     ms->enable_graphics = true;
1060     ms->kernel_cmdline = g_strdup("");
1061     ms->ram_size = mc->default_ram_size;
1062     ms->maxram_size = mc->default_ram_size;
1063
1064     if (mc->nvdimm_supported) {
1065         Object *obj = OBJECT(ms);
1066
1067         ms->nvdimms_state = g_new0(NVDIMMState, 1);
1068         object_property_add_bool(obj, "nvdimm",
1069                                  machine_get_nvdimm, machine_set_nvdimm);
1070         object_property_set_description(obj, "nvdimm",
1071                                         "Set on/off to enable/disable "
1072                                         "NVDIMM instantiation");
1073
1074         object_property_add_str(obj, "nvdimm-persistence",
1075                                 machine_get_nvdimm_persistence,
1076                                 machine_set_nvdimm_persistence);
1077         object_property_set_description(obj, "nvdimm-persistence",
1078                                         "Set NVDIMM persistence"
1079                                         "Valid values are cpu, mem-ctrl");
1080     }
1081
1082     if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
1083         ms->numa_state = g_new0(NumaState, 1);
1084         object_property_add_bool(obj, "hmat",
1085                                  machine_get_hmat, machine_set_hmat);
1086         object_property_set_description(obj, "hmat",
1087                                         "Set on/off to enable/disable "
1088                                         "ACPI Heterogeneous Memory Attribute "
1089                                         "Table (HMAT)");
1090     }
1091
1092     /* default to mc->default_cpus */
1093     ms->smp.cpus = mc->default_cpus;
1094     ms->smp.max_cpus = mc->default_cpus;
1095     ms->smp.sockets = 1;
1096     ms->smp.dies = 1;
1097     ms->smp.clusters = 1;
1098     ms->smp.cores = 1;
1099     ms->smp.threads = 1;
1100
1101     machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
1102 }
1103
1104 static void machine_finalize(Object *obj)
1105 {
1106     MachineState *ms = MACHINE(obj);
1107
1108     machine_free_boot_config(ms);
1109     g_free(ms->kernel_filename);
1110     g_free(ms->initrd_filename);
1111     g_free(ms->kernel_cmdline);
1112     g_free(ms->dtb);
1113     g_free(ms->dumpdtb);
1114     g_free(ms->dt_compatible);
1115     g_free(ms->firmware);
1116     g_free(ms->device_memory);
1117     g_free(ms->nvdimms_state);
1118     g_free(ms->numa_state);
1119 }
1120
1121 bool machine_usb(MachineState *machine)
1122 {
1123     return machine->usb;
1124 }
1125
1126 int machine_phandle_start(MachineState *machine)
1127 {
1128     return machine->phandle_start;
1129 }
1130
1131 bool machine_dump_guest_core(MachineState *machine)
1132 {
1133     return machine->dump_guest_core;
1134 }
1135
1136 bool machine_mem_merge(MachineState *machine)
1137 {
1138     return machine->mem_merge;
1139 }
1140
1141 static char *cpu_slot_to_string(const CPUArchId *cpu)
1142 {
1143     GString *s = g_string_new(NULL);
1144     if (cpu->props.has_socket_id) {
1145         g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
1146     }
1147     if (cpu->props.has_die_id) {
1148         if (s->len) {
1149             g_string_append_printf(s, ", ");
1150         }
1151         g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
1152     }
1153     if (cpu->props.has_cluster_id) {
1154         if (s->len) {
1155             g_string_append_printf(s, ", ");
1156         }
1157         g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
1158     }
1159     if (cpu->props.has_core_id) {
1160         if (s->len) {
1161             g_string_append_printf(s, ", ");
1162         }
1163         g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
1164     }
1165     if (cpu->props.has_thread_id) {
1166         if (s->len) {
1167             g_string_append_printf(s, ", ");
1168         }
1169         g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1170     }
1171     return g_string_free(s, false);
1172 }
1173
1174 static void numa_validate_initiator(NumaState *numa_state)
1175 {
1176     int i;
1177     NodeInfo *numa_info = numa_state->nodes;
1178
1179     for (i = 0; i < numa_state->num_nodes; i++) {
1180         if (numa_info[i].initiator == MAX_NODES) {
1181             error_report("The initiator of NUMA node %d is missing, use "
1182                          "'-numa node,initiator' option to declare it", i);
1183             exit(1);
1184         }
1185
1186         if (!numa_info[numa_info[i].initiator].present) {
1187             error_report("NUMA node %" PRIu16 " is missing, use "
1188                          "'-numa node' option to declare it first",
1189                          numa_info[i].initiator);
1190             exit(1);
1191         }
1192
1193         if (!numa_info[numa_info[i].initiator].has_cpu) {
1194             error_report("The initiator of NUMA node %d is invalid", i);
1195             exit(1);
1196         }
1197     }
1198 }
1199
1200 static void machine_numa_finish_cpu_init(MachineState *machine)
1201 {
1202     int i;
1203     bool default_mapping;
1204     GString *s = g_string_new(NULL);
1205     MachineClass *mc = MACHINE_GET_CLASS(machine);
1206     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1207
1208     assert(machine->numa_state->num_nodes);
1209     for (i = 0; i < possible_cpus->len; i++) {
1210         if (possible_cpus->cpus[i].props.has_node_id) {
1211             break;
1212         }
1213     }
1214     default_mapping = (i == possible_cpus->len);
1215
1216     for (i = 0; i < possible_cpus->len; i++) {
1217         const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1218
1219         if (!cpu_slot->props.has_node_id) {
1220             /* fetch default mapping from board and enable it */
1221             CpuInstanceProperties props = cpu_slot->props;
1222
1223             props.node_id = mc->get_default_cpu_node_id(machine, i);
1224             if (!default_mapping) {
1225                 /* record slots with not set mapping,
1226                  * TODO: make it hard error in future */
1227                 char *cpu_str = cpu_slot_to_string(cpu_slot);
1228                 g_string_append_printf(s, "%sCPU %d [%s]",
1229                                        s->len ? ", " : "", i, cpu_str);
1230                 g_free(cpu_str);
1231
1232                 /* non mapped cpus used to fallback to node 0 */
1233                 props.node_id = 0;
1234             }
1235
1236             props.has_node_id = true;
1237             machine_set_cpu_numa_node(machine, &props, &error_fatal);
1238         }
1239     }
1240
1241     if (machine->numa_state->hmat_enabled) {
1242         numa_validate_initiator(machine->numa_state);
1243     }
1244
1245     if (s->len && !qtest_enabled()) {
1246         warn_report("CPU(s) not present in any NUMA nodes: %s",
1247                     s->str);
1248         warn_report("All CPU(s) up to maxcpus should be described "
1249                     "in NUMA config, ability to start up with partial NUMA "
1250                     "mappings is obsoleted and will be removed in future");
1251     }
1252     g_string_free(s, true);
1253 }
1254
1255 MemoryRegion *machine_consume_memdev(MachineState *machine,
1256                                      HostMemoryBackend *backend)
1257 {
1258     MemoryRegion *ret = host_memory_backend_get_memory(backend);
1259
1260     if (host_memory_backend_is_mapped(backend)) {
1261         error_report("memory backend %s can't be used multiple times.",
1262                      object_get_canonical_path_component(OBJECT(backend)));
1263         exit(EXIT_FAILURE);
1264     }
1265     host_memory_backend_set_mapped(backend, true);
1266     vmstate_register_ram_global(ret);
1267     return ret;
1268 }
1269
1270 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp)
1271 {
1272     Object *obj;
1273     MachineClass *mc = MACHINE_GET_CLASS(ms);
1274     bool r = false;
1275
1276     obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM);
1277     if (path) {
1278         if (!object_property_set_str(obj, "mem-path", path, errp)) {
1279             goto out;
1280         }
1281     }
1282     if (!object_property_set_int(obj, "size", ms->ram_size, errp)) {
1283         goto out;
1284     }
1285     object_property_add_child(object_get_objects_root(), mc->default_ram_id,
1286                               obj);
1287     /* Ensure backend's memory region name is equal to mc->default_ram_id */
1288     if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id",
1289                              false, errp)) {
1290         goto out;
1291     }
1292     if (!user_creatable_complete(USER_CREATABLE(obj), errp)) {
1293         goto out;
1294     }
1295     r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp);
1296
1297 out:
1298     object_unref(obj);
1299     return r;
1300 }
1301
1302
1303 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp)
1304 {
1305     MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1306     ObjectClass *oc = object_class_by_name(machine->cpu_type);
1307     CPUClass *cc;
1308
1309     /* This checkpoint is required by replay to separate prior clock
1310        reading from the other reads, because timer polling functions query
1311        clock values from the log. */
1312     replay_checkpoint(CHECKPOINT_INIT);
1313
1314     if (!xen_enabled()) {
1315         /* On 32-bit hosts, QEMU is limited by virtual address space */
1316         if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) {
1317             error_setg(errp, "at most 2047 MB RAM can be simulated");
1318             return;
1319         }
1320     }
1321
1322     if (machine->memdev) {
1323         ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev),
1324                                                            "size",  &error_abort);
1325         if (backend_size != machine->ram_size) {
1326             error_setg(errp, "Machine memory size does not match the size of the memory backend");
1327             return;
1328         }
1329     } else if (machine_class->default_ram_id && machine->ram_size &&
1330                numa_uses_legacy_mem()) {
1331         if (!create_default_memdev(current_machine, mem_path, errp)) {
1332             return;
1333         }
1334     }
1335
1336     if (machine->numa_state) {
1337         numa_complete_configuration(machine);
1338         if (machine->numa_state->num_nodes) {
1339             machine_numa_finish_cpu_init(machine);
1340         }
1341     }
1342
1343     if (!machine->ram && machine->memdev) {
1344         machine->ram = machine_consume_memdev(machine, machine->memdev);
1345     }
1346
1347     /* If the machine supports the valid_cpu_types check and the user
1348      * specified a CPU with -cpu check here that the user CPU is supported.
1349      */
1350     if (machine_class->valid_cpu_types && machine->cpu_type) {
1351         int i;
1352
1353         for (i = 0; machine_class->valid_cpu_types[i]; i++) {
1354             if (object_class_dynamic_cast(oc,
1355                                           machine_class->valid_cpu_types[i])) {
1356                 /* The user specificed CPU is in the valid field, we are
1357                  * good to go.
1358                  */
1359                 break;
1360             }
1361         }
1362
1363         if (!machine_class->valid_cpu_types[i]) {
1364             /* The user specified CPU is not valid */
1365             error_report("Invalid CPU type: %s", machine->cpu_type);
1366             error_printf("The valid types are: %s",
1367                          machine_class->valid_cpu_types[0]);
1368             for (i = 1; machine_class->valid_cpu_types[i]; i++) {
1369                 error_printf(", %s", machine_class->valid_cpu_types[i]);
1370             }
1371             error_printf("\n");
1372
1373             exit(1);
1374         }
1375     }
1376
1377     /* Check if CPU type is deprecated and warn if so */
1378     cc = CPU_CLASS(oc);
1379     if (cc && cc->deprecation_note) {
1380         warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
1381                     cc->deprecation_note);
1382     }
1383
1384     if (machine->cgs) {
1385         /*
1386          * With confidential guests, the host can't see the real
1387          * contents of RAM, so there's no point in it trying to merge
1388          * areas.
1389          */
1390         machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1391
1392         /*
1393          * Virtio devices can't count on directly accessing guest
1394          * memory, so they need iommu_platform=on to use normal DMA
1395          * mechanisms.  That requires also disabling legacy virtio
1396          * support for those virtio pci devices which allow it.
1397          */
1398         object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1399                                    "on", true);
1400         object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1401                                    "on", false);
1402     }
1403
1404     accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator));
1405     machine_class->init(machine);
1406     phase_advance(PHASE_MACHINE_INITIALIZED);
1407 }
1408
1409 static NotifierList machine_init_done_notifiers =
1410     NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1411
1412 void qemu_add_machine_init_done_notifier(Notifier *notify)
1413 {
1414     notifier_list_add(&machine_init_done_notifiers, notify);
1415     if (phase_check(PHASE_MACHINE_READY)) {
1416         notify->notify(notify, NULL);
1417     }
1418 }
1419
1420 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1421 {
1422     notifier_remove(notify);
1423 }
1424
1425 void qdev_machine_creation_done(void)
1426 {
1427     cpu_synchronize_all_post_init();
1428
1429     if (current_machine->boot_config.has_once) {
1430         qemu_boot_set(current_machine->boot_config.once, &error_fatal);
1431         qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order));
1432     }
1433
1434     /*
1435      * ok, initial machine setup is done, starting from now we can
1436      * only create hotpluggable devices
1437      */
1438     phase_advance(PHASE_MACHINE_READY);
1439     qdev_assert_realized_properly();
1440
1441     /* TODO: once all bus devices are qdevified, this should be done
1442      * when bus is created by qdev.c */
1443     /*
1444      * TODO: If we had a main 'reset container' that the whole system
1445      * lived in, we could reset that using the multi-phase reset
1446      * APIs. For the moment, we just reset the sysbus, which will cause
1447      * all devices hanging off it (and all their child buses, recursively)
1448      * to be reset. Note that this will *not* reset any Device objects
1449      * which are not attached to some part of the qbus tree!
1450      */
1451     qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default());
1452
1453     notifier_list_notify(&machine_init_done_notifiers, NULL);
1454
1455     if (rom_check_and_register_reset() != 0) {
1456         exit(1);
1457     }
1458
1459     replay_start();
1460
1461     /* This checkpoint is required by replay to separate prior clock
1462        reading from the other reads, because timer polling functions query
1463        clock values from the log. */
1464     replay_checkpoint(CHECKPOINT_RESET);
1465     qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1466     register_global_state();
1467 }
1468
1469 static const TypeInfo machine_info = {
1470     .name = TYPE_MACHINE,
1471     .parent = TYPE_OBJECT,
1472     .abstract = true,
1473     .class_size = sizeof(MachineClass),
1474     .class_init    = machine_class_init,
1475     .class_base_init = machine_class_base_init,
1476     .instance_size = sizeof(MachineState),
1477     .instance_init = machine_initfn,
1478     .instance_finalize = machine_finalize,
1479 };
1480
1481 static void machine_register_types(void)
1482 {
1483     type_register_static(&machine_info);
1484 }
1485
1486 type_init(machine_register_types)