| blob | 2f251dac1bb2d74e41e9a5528929bff1c56b2eb5 |
1 #
2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 #
4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5 # Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6 #
7 # This program is free software; you can redistribute it and/or modify it
8 # under the terms and conditions of the GNU General Public License,
9 # version 2 or later, as published by the Free Software Foundation.
10 #
11 # This program is distributed in the hope it will be useful, but WITHOUT
12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 # more details.
15 #
16 # You should have received a copy of the GNU General Public License along with
17 # this program. If not, see <http://www.gnu.org/licenses/>.
19 # Fields:
20 %rs3 27:5
21 %rs2 20:5
22 %rs1 15:5
23 %rd 7:5
24 %sh5 20:5
26 %sh7 20:7
27 %csr 20:12
28 %rm 12:3
29 %nf 29:3 !function=ex_plus_1
31 # immediates:
32 %imm_i 20:s12
33 %imm_s 25:s7 7:5
34 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
35 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
36 %imm_u 12:s20 !function=ex_shift_12
38 # Argument sets:
39 &empty
40 &b imm rs2 rs1
41 &i imm rs1 rd
42 &j imm rd
43 &r rd rs1 rs2
44 &r2 rd rs1
45 &r2_s rs1 rs2
46 &s imm rs1 rs2
47 &u imm rd
48 &shift shamt rs1 rd
49 &atomic aq rl rs2 rs1 rd
50 &rmrr vm rd rs1 rs2
51 &rmr vm rd rs2
52 &rwdvm vm wd rd rs1 rs2
53 &r2nfvm vm rd rs1 nf
54 &rnfvm vm rd rs1 rs2 nf
56 # Formats 32:
57 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
58 @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
59 @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
60 @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
61 @u .................... ..... ....... &u imm=%imm_u %rd
62 @j .................... ..... ....... &j imm=%imm_j %rd
64 @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
65 @csr ............ ..... ... ..... ....... %csr %rs1 %rd
67 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
68 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
70 @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
71 @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
72 @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
73 @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
74 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
75 @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
76 @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
77 @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
78 @r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
79 @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
80 @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
81 @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
82 @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
83 @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
84 @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
86 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
87 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
89 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
90 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
92 # Formats 64:
93 @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
95 # *** Privileged Instructions ***
96 ecall 000000000000 00000 000 00000 1110011
97 ebreak 000000000001 00000 000 00000 1110011
98 uret 0000000 00010 00000 000 00000 1110011
99 sret 0001000 00010 00000 000 00000 1110011
100 mret 0011000 00010 00000 000 00000 1110011
101 wfi 0001000 00101 00000 000 00000 1110011
102 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
103 sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
105 # *** RV32I Base Instruction Set ***
106 lui .................... ..... 0110111 @u
107 auipc .................... ..... 0010111 @u
108 jal .................... ..... 1101111 @j
109 jalr ............ ..... 000 ..... 1100111 @i
110 beq ....... ..... ..... 000 ..... 1100011 @b
111 bne ....... ..... ..... 001 ..... 1100011 @b
112 blt ....... ..... ..... 100 ..... 1100011 @b
113 bge ....... ..... ..... 101 ..... 1100011 @b
114 bltu ....... ..... ..... 110 ..... 1100011 @b
115 bgeu ....... ..... ..... 111 ..... 1100011 @b
116 lb ............ ..... 000 ..... 0000011 @i
117 lh ............ ..... 001 ..... 0000011 @i
118 lw ............ ..... 010 ..... 0000011 @i
119 lbu ............ ..... 100 ..... 0000011 @i
120 lhu ............ ..... 101 ..... 0000011 @i
121 sb ....... ..... ..... 000 ..... 0100011 @s
122 sh ....... ..... ..... 001 ..... 0100011 @s
123 sw ....... ..... ..... 010 ..... 0100011 @s
124 addi ............ ..... 000 ..... 0010011 @i
125 slti ............ ..... 010 ..... 0010011 @i
126 sltiu ............ ..... 011 ..... 0010011 @i
127 xori ............ ..... 100 ..... 0010011 @i
128 ori ............ ..... 110 ..... 0010011 @i
129 andi ............ ..... 111 ..... 0010011 @i
130 slli 00000. ...... ..... 001 ..... 0010011 @sh
131 srli 00000. ...... ..... 101 ..... 0010011 @sh
132 srai 01000. ...... ..... 101 ..... 0010011 @sh
133 add 0000000 ..... ..... 000 ..... 0110011 @r
134 sub 0100000 ..... ..... 000 ..... 0110011 @r
135 sll 0000000 ..... ..... 001 ..... 0110011 @r
136 slt 0000000 ..... ..... 010 ..... 0110011 @r
137 sltu 0000000 ..... ..... 011 ..... 0110011 @r
138 xor 0000000 ..... ..... 100 ..... 0110011 @r
139 srl 0000000 ..... ..... 101 ..... 0110011 @r
140 sra 0100000 ..... ..... 101 ..... 0110011 @r
141 or 0000000 ..... ..... 110 ..... 0110011 @r
142 and 0000000 ..... ..... 111 ..... 0110011 @r
143 fence ---- pred:4 succ:4 ----- 000 ----- 0001111
144 fence_i ---- ---- ---- ----- 001 ----- 0001111
145 csrrw ............ ..... 001 ..... 1110011 @csr
146 csrrs ............ ..... 010 ..... 1110011 @csr
147 csrrc ............ ..... 011 ..... 1110011 @csr
148 csrrwi ............ ..... 101 ..... 1110011 @csr
149 csrrsi ............ ..... 110 ..... 1110011 @csr
150 csrrci ............ ..... 111 ..... 1110011 @csr
152 # *** RV64I Base Instruction Set (in addition to RV32I) ***
153 lwu ............ ..... 110 ..... 0000011 @i
154 ld ............ ..... 011 ..... 0000011 @i
155 sd ....... ..... ..... 011 ..... 0100011 @s
156 addiw ............ ..... 000 ..... 0011011 @i
157 slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
158 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
159 sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
160 addw 0000000 ..... ..... 000 ..... 0111011 @r
161 subw 0100000 ..... ..... 000 ..... 0111011 @r
162 sllw 0000000 ..... ..... 001 ..... 0111011 @r
163 srlw 0000000 ..... ..... 101 ..... 0111011 @r
164 sraw 0100000 ..... ..... 101 ..... 0111011 @r
166 # *** RV32M Standard Extension ***
167 mul 0000001 ..... ..... 000 ..... 0110011 @r
168 mulh 0000001 ..... ..... 001 ..... 0110011 @r
169 mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
170 mulhu 0000001 ..... ..... 011 ..... 0110011 @r
171 div 0000001 ..... ..... 100 ..... 0110011 @r
172 divu 0000001 ..... ..... 101 ..... 0110011 @r
173 rem 0000001 ..... ..... 110 ..... 0110011 @r
174 remu 0000001 ..... ..... 111 ..... 0110011 @r
176 # *** RV64M Standard Extension (in addition to RV32M) ***
177 mulw 0000001 ..... ..... 000 ..... 0111011 @r
178 divw 0000001 ..... ..... 100 ..... 0111011 @r
179 divuw 0000001 ..... ..... 101 ..... 0111011 @r
180 remw 0000001 ..... ..... 110 ..... 0111011 @r
181 remuw 0000001 ..... ..... 111 ..... 0111011 @r
183 # *** RV32A Standard Extension ***
184 lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
185 sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
186 amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
187 amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
188 amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
189 amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
190 amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
191 amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
192 amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
193 amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
194 amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
196 # *** RV64A Standard Extension (in addition to RV32A) ***
197 lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
198 sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
199 amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
200 amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
201 amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
202 amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
203 amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
204 amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
205 amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
206 amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
207 amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
209 # *** RV32F Standard Extension ***
210 flw ............ ..... 010 ..... 0000111 @i
211 fsw ....... ..... ..... 010 ..... 0100111 @s
212 fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
213 fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
214 fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
215 fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
216 fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
217 fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
218 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
219 fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
220 fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
221 fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
222 fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
223 fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
224 fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
225 fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
226 fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
227 fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
228 fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
229 feq_s 1010000 ..... ..... 010 ..... 1010011 @r
230 flt_s 1010000 ..... ..... 001 ..... 1010011 @r
231 fle_s 1010000 ..... ..... 000 ..... 1010011 @r
232 fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
233 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
234 fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
235 fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
237 # *** RV64F Standard Extension (in addition to RV32F) ***
238 fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
239 fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
240 fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
241 fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
243 # *** RV32D Standard Extension ***
244 fld ............ ..... 011 ..... 0000111 @i
245 fsd ....... ..... ..... 011 ..... 0100111 @s
246 fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
247 fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
248 fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
249 fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
250 fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
251 fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
252 fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
253 fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
254 fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
255 fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
256 fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
257 fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
258 fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
259 fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
260 fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
261 fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
262 feq_d 1010001 ..... ..... 010 ..... 1010011 @r
263 flt_d 1010001 ..... ..... 001 ..... 1010011 @r
264 fle_d 1010001 ..... ..... 000 ..... 1010011 @r
265 fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
266 fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
267 fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
268 fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
269 fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
271 # *** RV64D Standard Extension (in addition to RV32D) ***
272 fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
273 fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
274 fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
275 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
276 fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
277 fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
279 # *** RV32H Base Instruction Set ***
280 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
281 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
282 hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
283 hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
284 hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
285 hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
286 hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
287 hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
288 hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
289 hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
290 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
291 hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
293 # *** RV64H Base Instruction Set ***
294 hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
295 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
296 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
298 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
299 vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
300 vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
301 vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
302 vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
303 vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
304 vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
305 vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
306 vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
307 vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
308 vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
309 vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
310 vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
311 vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
312 vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
313 vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
314 vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
315 vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
316 vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
318 vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
319 vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
320 vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
321 vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
322 vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
323 vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
324 vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
325 vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
326 vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
327 vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
328 vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
330 vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
331 vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
332 vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
333 vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
334 vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
335 vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
336 vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
337 # Vector ordered-indexed and unordered-indexed store insns.
338 vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
339 vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
340 vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
341 vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
343 #*** Vector AMO operations are encoded under the standard AMO major opcode ***
344 vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
345 vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
346 vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
347 vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
348 vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
349 vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
350 vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
351 vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
352 vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
354 # *** new major opcode OP-V ***
355 vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
356 vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
357 vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
358 vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
359 vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
360 vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
361 vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
362 vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
363 vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
364 vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
365 vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
366 vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
367 vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
368 vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
369 vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
370 vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
371 vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
372 vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
373 vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
374 vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
375 vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
376 vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
377 vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
378 vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
379 vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
380 vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
381 vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
382 vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
383 vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
384 vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
385 vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
386 vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
387 vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
388 vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
389 vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
390 vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
391 vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
392 vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
393 vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
394 vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
395 vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
396 vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
397 vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
398 vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
399 vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
400 vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
401 vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
402 vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
403 vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
404 vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
405 vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
406 vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
407 vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
408 vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
409 vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
410 vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
411 vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
412 vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
413 vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
414 vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
415 vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
416 vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
417 vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
418 vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
419 vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
420 vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
421 vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
422 vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
423 vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
424 vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
425 vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
426 vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
427 vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
428 vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
429 vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
430 vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
431 vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
432 vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
433 vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
434 vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
435 vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
436 vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
437 vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
438 vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
439 vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
440 vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
441 vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
442 vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
443 vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
444 vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
445 vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
446 vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
447 vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
448 vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
449 vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
450 vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
451 vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
452 vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
453 vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
454 vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
455 vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
456 vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
457 vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
458 vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
459 vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
460 vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
461 vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
462 vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
463 vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
464 vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
465 vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
466 vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
467 vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
468 vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
469 vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
470 vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
471 vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
472 vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
473 vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
474 vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm
475 vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
476 vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
477 vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
478 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
479 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
480 vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
481 vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
482 vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
483 vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
484 vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
485 vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
486 vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
487 vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
488 vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
489 vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
490 vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
491 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
492 vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
493 vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
494 vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
495 vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
496 vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
497 vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
498 vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
499 vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
500 vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
501 vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
502 vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
503 vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
504 vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
505 vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
506 vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
507 vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
508 vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
509 vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
510 vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
511 vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
512 vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
513 vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
514 vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
515 vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
516 vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
517 vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
518 vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
519 vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
520 vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
521 vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
522 vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
523 vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
524 vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
525 vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
526 vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
527 vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
528 vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
529 vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
530 vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
531 vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
532 vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
533 vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
534 vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
535 vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
536 vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
537 vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
538 vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
539 vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
540 vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
541 vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
542 vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
543 vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
544 vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
545 vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
546 vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
547 vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
548 vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
549 vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
550 vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
551 vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
552 vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
553 vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
554 vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
555 vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
556 vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
557 vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
558 vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
559 vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
560 vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
561 vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
562 vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
563 vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
564 vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
565 vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
566 vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
567 vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
568 vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
569 vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
570 vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
571 vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
572 vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
573 vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
574 vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
575 vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
576 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
577 vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
578 vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
579 vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
580 vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
581 vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
582 vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
583 vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
584 vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
585 vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
586 vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
587 vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
588 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
589 vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
590 vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
591 vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
592 vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
593 vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
594 vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
595 vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
596 vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
597 vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
598 vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
599 vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
600 vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
601 vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
602 vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
603 vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
604 vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
605 vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
606 vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
607 vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
608 vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
609 vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
610 vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
611 vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
612 vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
613 # Vector ordered and unordered reduction sum
614 vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
615 vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
616 vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
617 # Vector widening ordered and unordered float reduction sum
618 vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
619 vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
620 vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
621 vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
622 vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
623 vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
624 vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
625 vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
626 vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
627 vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
628 vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
629 vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
630 vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
631 vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
632 viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
633 vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
634 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
635 vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
636 vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
637 vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
638 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
639 vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
640 vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
641 vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
642 vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
643 vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
644 vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
645 vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
646 vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
647 vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
649 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
650 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
652 #*** Vector AMO operations (in addition to Zvamo) ***
653 vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
654 vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
655 vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
656 vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
657 vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
658 vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
659 vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
660 vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
661 vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
663 # *** RV32 Zba Standard Extension ***
664 sh1add 0010000 .......... 010 ..... 0110011 @r
665 sh2add 0010000 .......... 100 ..... 0110011 @r
666 sh3add 0010000 .......... 110 ..... 0110011 @r
668 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
669 add_uw 0000100 .......... 000 ..... 0111011 @r
670 sh1add_uw 0010000 .......... 010 ..... 0111011 @r
671 sh2add_uw 0010000 .......... 100 ..... 0111011 @r
672 sh3add_uw 0010000 .......... 110 ..... 0111011 @r
673 slli_uw 00001 ............ 001 ..... 0011011 @sh
675 # *** RV32 Zbb Standard Extension ***
676 andn 0100000 .......... 111 ..... 0110011 @r
677 clz 011000 000000 ..... 001 ..... 0010011 @r2
678 cpop 011000 000010 ..... 001 ..... 0010011 @r2
679 ctz 011000 000001 ..... 001 ..... 0010011 @r2
680 max 0000101 .......... 110 ..... 0110011 @r
681 maxu 0000101 .......... 111 ..... 0110011 @r
682 min 0000101 .......... 100 ..... 0110011 @r
683 minu 0000101 .......... 101 ..... 0110011 @r
684 orc_b 001010 000111 ..... 101 ..... 0010011 @r2
685 orn 0100000 .......... 110 ..... 0110011 @r
686 # The encoding for rev8 differs between RV32 and RV64.
687 # rev8_32 denotes the RV32 variant.
688 rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
689 rol 0110000 .......... 001 ..... 0110011 @r
690 ror 0110000 .......... 101 ..... 0110011 @r
691 rori 01100 ............ 101 ..... 0010011 @sh
692 sext_b 011000 000100 ..... 001 ..... 0010011 @r2
693 sext_h 011000 000101 ..... 001 ..... 0010011 @r2
694 xnor 0100000 .......... 100 ..... 0110011 @r
695 # The encoding for zext.h differs between RV32 and RV64.
696 # zext_h_32 denotes the RV32 variant.
697 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
699 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
700 clzw 0110000 00000 ..... 001 ..... 0011011 @r2
701 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
702 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
703 # The encoding for rev8 differs between RV32 and RV64.
704 # When executing on RV64, the encoding used in RV32 is an illegal
705 # instruction, so we use different handler functions to differentiate.
706 rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
707 rolw 0110000 .......... 001 ..... 0111011 @r
708 roriw 0110000 .......... 101 ..... 0011011 @sh5
709 rorw 0110000 .......... 101 ..... 0111011 @r
710 # The encoding for zext.h differs between RV32 and RV64.
711 # When executing on RV64, the encoding used in RV32 is an illegal
712 # instruction, so we use different handler functions to differentiate.
713 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
715 # *** RV32 Zbc Standard Extension ***
716 clmul 0000101 .......... 001 ..... 0110011 @r
717 clmulh 0000101 .......... 011 ..... 0110011 @r
718 clmulr 0000101 .......... 010 ..... 0110011 @r
720 # *** RV32 Zbs Standard Extension ***
721 bclr 0100100 .......... 001 ..... 0110011 @r
722 bclri 01001. ........... 001 ..... 0010011 @sh
723 bext 0100100 .......... 101 ..... 0110011 @r
724 bexti 01001. ........... 101 ..... 0010011 @sh
725 binv 0110100 .......... 001 ..... 0110011 @r
726 binvi 01101. ........... 001 ..... 0010011 @sh
727 bset 0010100 .......... 001 ..... 0110011 @r
728 bseti 00101. ........... 001 ..... 0010011 @sh