| blob | f22df04cfd1b887e7672509ac81a98e384fe7705 |
1 #
2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 #
4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5 # Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6 #
7 # This program is free software; you can redistribute it and/or modify it
8 # under the terms and conditions of the GNU General Public License,
9 # version 2 or later, as published by the Free Software Foundation.
10 #
11 # This program is distributed in the hope it will be useful, but WITHOUT
12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 # more details.
15 #
16 # You should have received a copy of the GNU General Public License along with
17 # this program. If not, see <http://www.gnu.org/licenses/>.
19 # Fields:
20 %rs3 27:5
21 %rs2 20:5
22 %rs1 15:5
23 %rd 7:5
24 %sh5 20:5
25 %sh6 20:6
27 %sh7 20:7
28 %csr 20:12
29 %rm 12:3
30 %nf 29:3 !function=ex_plus_1
32 # immediates:
33 %imm_i 20:s12
34 %imm_s 25:s7 7:5
35 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
36 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
37 %imm_u 12:s20 !function=ex_shift_12
38 %imm_bs 30:2 !function=ex_shift_3
39 %imm_rnum 20:4
40 %imm_z6 26:1 15:5
42 # Argument sets:
43 &empty
44 &b imm rs2 rs1
45 &i imm rs1 rd
46 &j imm rd
47 &r rd rs1 rs2
48 &r2 rd rs1
49 &r2_s rs1 rs2
50 &s imm rs1 rs2
51 &u imm rd
52 &shift shamt rs1 rd
53 &atomic aq rl rs2 rs1 rd
54 &rmrr vm rd rs1 rs2
55 &rmr vm rd rs2
56 &r2nfvm vm rd rs1 nf
57 &rnfvm vm rd rs1 rs2 nf
58 &k_aes shamt rs2 rs1 rd
60 # Formats 32:
61 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
62 @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
63 @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
64 @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
65 @u .................... ..... ....... &u imm=%imm_u %rd
66 @j .................... ..... ....... &j imm=%imm_j %rd
68 @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
69 @csr ............ ..... ... ..... ....... %csr %rs1 %rd
71 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
72 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
74 @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
75 @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
76 @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
77 @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
78 @r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
79 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
80 @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
81 @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
82 @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
83 @r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
84 @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
85 @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
86 @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
87 @r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd
88 @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
89 @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
90 @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
92 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
93 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
95 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
96 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
98 @k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
99 @i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
101 # Formats 64:
102 @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
104 # Formats 128:
105 @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
107 # *** Privileged Instructions ***
108 ecall 000000000000 00000 000 00000 1110011
109 ebreak 000000000001 00000 000 00000 1110011
110 uret 0000000 00010 00000 000 00000 1110011
111 sret 0001000 00010 00000 000 00000 1110011
112 mret 0011000 00010 00000 000 00000 1110011
113 wfi 0001000 00101 00000 000 00000 1110011
114 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
115 sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
117 # *** RV32I Base Instruction Set ***
118 lui .................... ..... 0110111 @u
119 auipc .................... ..... 0010111 @u
120 jal .................... ..... 1101111 @j
121 jalr ............ ..... 000 ..... 1100111 @i
122 beq ....... ..... ..... 000 ..... 1100011 @b
123 bne ....... ..... ..... 001 ..... 1100011 @b
124 blt ....... ..... ..... 100 ..... 1100011 @b
125 bge ....... ..... ..... 101 ..... 1100011 @b
126 bltu ....... ..... ..... 110 ..... 1100011 @b
127 bgeu ....... ..... ..... 111 ..... 1100011 @b
128 lb ............ ..... 000 ..... 0000011 @i
129 lh ............ ..... 001 ..... 0000011 @i
130 lw ............ ..... 010 ..... 0000011 @i
131 lbu ............ ..... 100 ..... 0000011 @i
132 lhu ............ ..... 101 ..... 0000011 @i
133 sb ....... ..... ..... 000 ..... 0100011 @s
134 sh ....... ..... ..... 001 ..... 0100011 @s
135 sw ....... ..... ..... 010 ..... 0100011 @s
136 addi ............ ..... 000 ..... 0010011 @i
137 slti ............ ..... 010 ..... 0010011 @i
138 sltiu ............ ..... 011 ..... 0010011 @i
139 xori ............ ..... 100 ..... 0010011 @i
140 # cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
141 ori ............ ..... 110 ..... 0010011 @i
142 andi ............ ..... 111 ..... 0010011 @i
143 slli 00000. ...... ..... 001 ..... 0010011 @sh
144 srli 00000. ...... ..... 101 ..... 0010011 @sh
145 srai 01000. ...... ..... 101 ..... 0010011 @sh
146 add 0000000 ..... ..... 000 ..... 0110011 @r
147 sub 0100000 ..... ..... 000 ..... 0110011 @r
148 sll 0000000 ..... ..... 001 ..... 0110011 @r
149 slt 0000000 ..... ..... 010 ..... 0110011 @r
150 sltu 0000000 ..... ..... 011 ..... 0110011 @r
151 xor 0000000 ..... ..... 100 ..... 0110011 @r
152 srl 0000000 ..... ..... 101 ..... 0110011 @r
153 sra 0100000 ..... ..... 101 ..... 0110011 @r
154 or 0000000 ..... ..... 110 ..... 0110011 @r
155 and 0000000 ..... ..... 111 ..... 0110011 @r
157 {
158 pause 0000 0001 0000 00000 000 00000 0001111
159 fence ---- pred:4 succ:4 ----- 000 ----- 0001111
160 }
162 fence_i ---- ---- ---- ----- 001 ----- 0001111
163 csrrw ............ ..... 001 ..... 1110011 @csr
164 csrrs ............ ..... 010 ..... 1110011 @csr
165 csrrc ............ ..... 011 ..... 1110011 @csr
166 csrrwi ............ ..... 101 ..... 1110011 @csr
167 csrrsi ............ ..... 110 ..... 1110011 @csr
168 csrrci ............ ..... 111 ..... 1110011 @csr
170 # *** RV64I Base Instruction Set (in addition to RV32I) ***
171 lwu ............ ..... 110 ..... 0000011 @i
172 ld ............ ..... 011 ..... 0000011 @i
173 sd ....... ..... ..... 011 ..... 0100011 @s
174 addiw ............ ..... 000 ..... 0011011 @i
175 slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
176 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
177 sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
178 addw 0000000 ..... ..... 000 ..... 0111011 @r
179 subw 0100000 ..... ..... 000 ..... 0111011 @r
180 sllw 0000000 ..... ..... 001 ..... 0111011 @r
181 srlw 0000000 ..... ..... 101 ..... 0111011 @r
182 sraw 0100000 ..... ..... 101 ..... 0111011 @r
184 # *** RV128I Base Instruction Set (in addition to RV64I) ***
185 ldu ............ ..... 111 ..... 0000011 @i
186 {
187 [
188 # *** RV32 Zicbom Standard Extension ***
189 cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm
190 cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm
191 cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
193 # *** RV32 Zicboz Standard Extension ***
194 cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm
195 ]
197 # *** RVI128 lq ***
198 lq ............ ..... 010 ..... 0001111 @i
199 }
200 sq ............ ..... 100 ..... 0100011 @s
201 addid ............ ..... 000 ..... 1011011 @i
202 sllid 000000 ...... ..... 001 ..... 1011011 @sh6
203 srlid 000000 ...... ..... 101 ..... 1011011 @sh6
204 sraid 010000 ...... ..... 101 ..... 1011011 @sh6
205 addd 0000000 ..... ..... 000 ..... 1111011 @r
206 subd 0100000 ..... ..... 000 ..... 1111011 @r
207 slld 0000000 ..... ..... 001 ..... 1111011 @r
208 srld 0000000 ..... ..... 101 ..... 1111011 @r
209 srad 0100000 ..... ..... 101 ..... 1111011 @r
211 # *** RV32M Standard Extension ***
212 mul 0000001 ..... ..... 000 ..... 0110011 @r
213 mulh 0000001 ..... ..... 001 ..... 0110011 @r
214 mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
215 mulhu 0000001 ..... ..... 011 ..... 0110011 @r
216 div 0000001 ..... ..... 100 ..... 0110011 @r
217 divu 0000001 ..... ..... 101 ..... 0110011 @r
218 rem 0000001 ..... ..... 110 ..... 0110011 @r
219 remu 0000001 ..... ..... 111 ..... 0110011 @r
221 # *** RV64M Standard Extension (in addition to RV32M) ***
222 mulw 0000001 ..... ..... 000 ..... 0111011 @r
223 divw 0000001 ..... ..... 100 ..... 0111011 @r
224 divuw 0000001 ..... ..... 101 ..... 0111011 @r
225 remw 0000001 ..... ..... 110 ..... 0111011 @r
226 remuw 0000001 ..... ..... 111 ..... 0111011 @r
228 # *** RV128M Standard Extension (in addition to RV64M) ***
229 muld 0000001 ..... ..... 000 ..... 1111011 @r
230 divd 0000001 ..... ..... 100 ..... 1111011 @r
231 divud 0000001 ..... ..... 101 ..... 1111011 @r
232 remd 0000001 ..... ..... 110 ..... 1111011 @r
233 remud 0000001 ..... ..... 111 ..... 1111011 @r
235 # *** RV32A Standard Extension ***
236 lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
237 sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
238 amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
239 amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
240 amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
241 amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
242 amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
243 amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
244 amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
245 amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
246 amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
248 # *** RV64A Standard Extension (in addition to RV32A) ***
249 lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
250 sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
251 amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
252 amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
253 amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
254 amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
255 amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
256 amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
257 amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
258 amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
259 amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
261 # *** RV32F Standard Extension ***
262 flw ............ ..... 010 ..... 0000111 @i
263 fsw ....... ..... ..... 010 ..... 0100111 @s
264 fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
265 fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
266 fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
267 fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
268 fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
269 fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
270 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
271 fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
272 fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
273 fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
274 fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
275 fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
276 fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
277 fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
278 fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
279 fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
280 fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
281 feq_s 1010000 ..... ..... 010 ..... 1010011 @r
282 flt_s 1010000 ..... ..... 001 ..... 1010011 @r
283 fle_s 1010000 ..... ..... 000 ..... 1010011 @r
284 fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
285 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
286 fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
287 fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
289 # *** RV64F Standard Extension (in addition to RV32F) ***
290 fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
291 fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
292 fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
293 fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
295 # *** RV32D Standard Extension ***
296 fld ............ ..... 011 ..... 0000111 @i
297 fsd ....... ..... ..... 011 ..... 0100111 @s
298 fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
299 fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
300 fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
301 fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
302 fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
303 fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
304 fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
305 fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
306 fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
307 fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
308 fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
309 fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
310 fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
311 fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
312 fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
313 fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
314 feq_d 1010001 ..... ..... 010 ..... 1010011 @r
315 flt_d 1010001 ..... ..... 001 ..... 1010011 @r
316 fle_d 1010001 ..... ..... 000 ..... 1010011 @r
317 fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
318 fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
319 fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
320 fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
321 fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
323 # *** RV64D Standard Extension (in addition to RV32D) ***
324 fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
325 fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
326 fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
327 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
328 fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
329 fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
331 # *** RV32H Base Instruction Set ***
332 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
333 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
334 hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
335 hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
336 hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
337 hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
338 hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
339 hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
340 hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
341 hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
342 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
343 hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
345 # *** RV64H Base Instruction Set ***
346 hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
347 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
348 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
350 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
351 # Vector unit-stride load/store insns.
352 vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
353 vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
354 vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
355 vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
356 vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
357 vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
358 vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
359 vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
361 # Vector unit-stride mask load/store insns.
362 vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
363 vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
365 # Vector strided insns.
366 vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
367 vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
368 vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
369 vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
370 vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
371 vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
372 vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
373 vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
375 # Vector ordered-indexed and unordered-indexed load insns.
376 vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
377 vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
378 vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
379 vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
381 # Vector ordered-indexed and unordered-indexed store insns.
382 vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
383 vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
384 vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
385 vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
387 # Vector unit-stride fault-only-first load insns.
388 vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
389 vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
390 vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
391 vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
393 # Vector whole register insns
394 vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
395 vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
396 vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
397 vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
398 vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
399 vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
400 vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
401 vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
402 vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
403 vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
404 vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
405 vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
406 vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
407 vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
408 vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
409 vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
410 vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
411 vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
412 vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
413 vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
415 # *** new major opcode OP-V ***
416 vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
417 vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
418 vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
419 vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
420 vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
421 vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
422 vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
423 vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
424 vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
425 vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
426 vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
427 vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
428 vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
429 vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
430 vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
431 vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
432 vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
433 vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
434 vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
435 vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
436 vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
437 vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
438 vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
439 vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
440 vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
441 vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
442 vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
443 vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
444 vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
445 vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
446 vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
447 vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
448 vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
449 vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
450 vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
451 vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
452 vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
453 vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
454 vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
455 vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
456 vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
457 vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
458 vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
459 vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
460 vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
461 vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
462 vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
463 vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
464 vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
465 vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
466 vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
467 vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
468 vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
469 vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
470 vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
471 vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
472 vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
473 vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
474 vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
475 vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
476 vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
477 vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
478 vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
479 vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
480 vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
481 vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
482 vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
483 vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
484 vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
485 vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
486 vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
487 vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
488 vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
489 vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
490 vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
491 vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
492 vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
493 vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
494 vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
495 vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
496 vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
497 vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
498 vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
499 vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
500 vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
501 vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
502 vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
503 vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
504 vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
505 vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
506 vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
507 vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
508 vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
509 vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
510 vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
511 vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
512 vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
513 vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
514 vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
515 vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
516 vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
517 vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
518 vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
519 vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
520 vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
521 vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
522 vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
523 vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
524 vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
525 vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
526 vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
527 vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
528 vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
529 vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
530 vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
531 vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
532 vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
533 vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
534 vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
535 vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
536 vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
537 vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
538 vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
539 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
540 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
541 vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
542 vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
543 vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
544 vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
545 vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
546 vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
547 vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
548 vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
549 vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
550 vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
551 vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
552 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
553 vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
554 vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
555 vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
556 vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
557 vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
558 vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
559 vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
560 vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
561 vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
562 vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
563 vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
564 vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
565 vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
566 vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
567 vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
568 vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
569 vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
570 vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
571 vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
572 vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
573 vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
574 vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
575 vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
576 vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
577 vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
578 vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
579 vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
580 vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
581 vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
582 vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
583 vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
584 vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
585 vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
586 vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
587 vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
588 vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
589 vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
590 vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
591 vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
592 vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
593 vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
594 vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
595 vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
596 vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
597 vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
598 vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
599 vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
600 vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
601 vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
602 vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
603 vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
604 vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
605 vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
606 vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
607 vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
608 vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
609 vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
610 vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
611 vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
612 vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
613 vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
614 vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
615 vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
616 vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
617 vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
618 vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
619 vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
620 vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
621 vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
622 vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
623 vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
624 vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
625 vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
626 vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
627 vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
628 vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
629 vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
630 vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
631 vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
632 vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
633 vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
634 vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
635 vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
636 vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
637 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
638 vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
639 vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
640 vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
641 vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
642 vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
643 vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
644 vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
645 vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
646 vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
647 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
649 vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
650 vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
651 vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
652 vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
653 vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
654 vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
656 vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
657 vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
658 vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
659 vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
660 vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
661 vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
662 vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
664 vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
665 vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
666 vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
667 vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
668 vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
669 vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
670 vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
671 vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
673 vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
674 vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
675 vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
676 vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
677 vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
678 vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
679 vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
680 vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
681 vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
682 vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
683 # Vector ordered and unordered reduction sum
684 vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
685 vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
686 vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
687 vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
688 # Vector widening ordered and unordered float reduction sum
689 vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
690 vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
691 vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
692 vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
693 vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r
694 vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
695 vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
696 vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
697 vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r
698 vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
699 vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
700 vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
701 vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
702 vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
703 vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
704 viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
705 vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
706 vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
707 vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
708 vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
709 vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
710 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
711 vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
712 vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
713 vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
714 vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
715 vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
716 vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
717 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
718 vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
719 vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
720 vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
721 vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
722 vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
723 vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
724 vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
726 # Vector Integer Extension
727 vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
728 vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
729 vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
730 vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
731 vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
732 vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
734 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
735 vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
736 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
738 # *** Zawrs Standard Extension ***
739 wrs_nto 000000001101 00000 000 00000 1110011
740 wrs_sto 000000011101 00000 000 00000 1110011
742 # *** RV32 Zba Standard Extension ***
743 sh1add 0010000 .......... 010 ..... 0110011 @r
744 sh2add 0010000 .......... 100 ..... 0110011 @r
745 sh3add 0010000 .......... 110 ..... 0110011 @r
747 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
748 add_uw 0000100 .......... 000 ..... 0111011 @r
749 sh1add_uw 0010000 .......... 010 ..... 0111011 @r
750 sh2add_uw 0010000 .......... 100 ..... 0111011 @r
751 sh3add_uw 0010000 .......... 110 ..... 0111011 @r
752 slli_uw 00001 ............ 001 ..... 0011011 @sh
754 # *** RV32 Zbb/Zbkb Standard Extension ***
755 andn 0100000 .......... 111 ..... 0110011 @r
756 rol 0110000 .......... 001 ..... 0110011 @r
757 ror 0110000 .......... 101 ..... 0110011 @r
758 rori 01100 ............ 101 ..... 0010011 @sh
759 # The encoding for rev8 differs between RV32 and RV64.
760 # rev8_32 denotes the RV32 variant.
761 rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
762 # The encoding for zext.h differs between RV32 and RV64.
763 # zext_h_32 denotes the RV32 variant.
764 {
765 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
766 pack 0000100 ..... ..... 100 ..... 0110011 @r
767 }
768 xnor 0100000 .......... 100 ..... 0110011 @r
769 # *** RV32 extra Zbb Standard Extension ***
770 clz 011000 000000 ..... 001 ..... 0010011 @r2
771 cpop 011000 000010 ..... 001 ..... 0010011 @r2
772 ctz 011000 000001 ..... 001 ..... 0010011 @r2
773 max 0000101 .......... 110 ..... 0110011 @r
774 maxu 0000101 .......... 111 ..... 0110011 @r
775 min 0000101 .......... 100 ..... 0110011 @r
776 minu 0000101 .......... 101 ..... 0110011 @r
777 orc_b 001010 000111 ..... 101 ..... 0010011 @r2
778 orn 0100000 .......... 110 ..... 0110011 @r
779 sext_b 011000 000100 ..... 001 ..... 0010011 @r2
780 sext_h 011000 000101 ..... 001 ..... 0010011 @r2
781 # *** RV32 extra Zbkb Standard Extension ***
782 brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
783 packh 0000100 .......... 111 ..... 0110011 @r
784 unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
785 zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
787 # *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
788 # The encoding for rev8 differs between RV32 and RV64.
789 # When executing on RV64, the encoding used in RV32 is an illegal
790 # instruction, so we use different handler functions to differentiate.
791 rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
792 rolw 0110000 .......... 001 ..... 0111011 @r
793 roriw 0110000 .......... 101 ..... 0011011 @sh5
794 rorw 0110000 .......... 101 ..... 0111011 @r
795 # The encoding for zext.h differs between RV32 and RV64.
796 # When executing on RV64, the encoding used in RV32 is an illegal
797 # instruction, so we use different handler functions to differentiate.
798 {
799 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
800 packw 0000100 ..... ..... 100 ..... 0111011 @r
801 }
802 # *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
803 clzw 0110000 00000 ..... 001 ..... 0011011 @r2
804 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
805 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
807 # *** RV32 Zbc/Zbkc Standard Extension ***
808 clmul 0000101 .......... 001 ..... 0110011 @r
809 clmulh 0000101 .......... 011 ..... 0110011 @r
810 # *** RV32 extra Zbc Standard Extension ***
811 clmulr 0000101 .......... 010 ..... 0110011 @r
813 # *** RV32 Zbkx Standard Extension ***
814 xperm4 0010100 .......... 010 ..... 0110011 @r
815 xperm8 0010100 .......... 100 ..... 0110011 @r
817 # *** RV32 Zbs Standard Extension ***
818 bclr 0100100 .......... 001 ..... 0110011 @r
819 bclri 01001. ........... 001 ..... 0010011 @sh
820 bext 0100100 .......... 101 ..... 0110011 @r
821 bexti 01001. ........... 101 ..... 0010011 @sh
822 binv 0110100 .......... 001 ..... 0110011 @r
823 binvi 01101. ........... 001 ..... 0010011 @sh
824 bset 0010100 .......... 001 ..... 0110011 @r
825 bseti 00101. ........... 001 ..... 0010011 @sh
827 # *** Zfa Standard Extension ***
828 fli_s 1111000 00001 ..... 000 ..... 1010011 @r2
829 fli_d 1111001 00001 ..... 000 ..... 1010011 @r2
830 fli_h 1111010 00001 ..... 000 ..... 1010011 @r2
831 fminm_s 0010100 ..... ..... 010 ..... 1010011 @r
832 fmaxm_s 0010100 ..... ..... 011 ..... 1010011 @r
833 fminm_d 0010101 ..... ..... 010 ..... 1010011 @r
834 fmaxm_d 0010101 ..... ..... 011 ..... 1010011 @r
835 fminm_h 0010110 ..... ..... 010 ..... 1010011 @r
836 fmaxm_h 0010110 ..... ..... 011 ..... 1010011 @r
837 fround_s 0100000 00100 ..... ... ..... 1010011 @r2_rm
838 froundnx_s 0100000 00101 ..... ... ..... 1010011 @r2_rm
839 fround_d 0100001 00100 ..... ... ..... 1010011 @r2_rm
840 froundnx_d 0100001 00101 ..... ... ..... 1010011 @r2_rm
841 fround_h 0100010 00100 ..... ... ..... 1010011 @r2_rm
842 froundnx_h 0100010 00101 ..... ... ..... 1010011 @r2_rm
843 fcvtmod_w_d 1100001 01000 ..... 001 ..... 1010011 @r2
844 fmvh_x_d 1110001 00001 ..... 000 ..... 1010011 @r2
845 fmvp_d_x 1011001 ..... ..... 000 ..... 1010011 @r
846 fleq_s 1010000 ..... ..... 100 ..... 1010011 @r
847 fltq_s 1010000 ..... ..... 101 ..... 1010011 @r
848 fleq_d 1010001 ..... ..... 100 ..... 1010011 @r
849 fltq_d 1010001 ..... ..... 101 ..... 1010011 @r
850 fleq_h 1010010 ..... ..... 100 ..... 1010011 @r
851 fltq_h 1010010 ..... ..... 101 ..... 1010011 @r
853 # *** RV32 Zfh Extension ***
854 flh ............ ..... 001 ..... 0000111 @i
855 fsh ....... ..... ..... 001 ..... 0100111 @s
856 fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
857 fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
858 fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
859 fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
860 fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
861 fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
862 fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
863 fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
864 fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
865 fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
866 fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
867 fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
868 fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
869 fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
870 fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
871 fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
872 fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
873 fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
874 fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
875 fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
876 fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
877 feq_h 1010010 ..... ..... 010 ..... 1010011 @r
878 flt_h 1010010 ..... ..... 001 ..... 1010011 @r
879 fle_h 1010010 ..... ..... 000 ..... 1010011 @r
880 fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
881 fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
882 fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
883 fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
885 # *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
886 fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
887 fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
888 fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
889 fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
891 # *** Svinval Standard Extension ***
892 sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
893 sfence_w_inval 0001100 00000 00000 000 00000 1110011
894 sfence_inval_ir 0001100 00001 00000 000 00000 1110011
895 hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
896 hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
898 # *** RV32 Zknd Standard Extension ***
899 aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
900 aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
901 # *** RV64 Zknd Standard Extension ***
902 aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
903 aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
904 aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
905 # *** RV32 Zkne Standard Extension ***
906 aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
907 aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
908 # *** RV64 Zkne Standard Extension ***
909 aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
910 aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
911 # *** RV64 Zkne/zknd Standard Extension ***
912 aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
913 aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
914 # *** RV32 Zknh Standard Extension ***
915 sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
916 sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
917 sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
918 sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
919 sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
920 sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
921 sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
922 sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
923 sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
924 sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
925 # *** RV64 Zknh Standard Extension ***
926 sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
927 sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
928 sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
929 sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
930 # *** RV32 Zksh Standard Extension ***
931 sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
932 sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
933 # *** RV32 Zksed Standard Extension ***
934 sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
935 sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
937 # *** RV32 Zicond Standard Extension ***
938 czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r
939 czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
941 # *** Zfbfmin Standard Extension ***
942 fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm
943 fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
945 # *** Zvfbfmin Standard Extension ***
946 vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
947 vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
949 # *** Zvfbfwma Standard Extension ***
950 vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm
951 vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm
953 # *** Zvbc vector crypto extension ***
954 vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
955 vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
956 vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
957 vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
959 # *** Zvbb vector crypto extension ***
960 vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm
961 vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm
962 vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm
963 vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm
964 vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
965 vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm
966 vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm
967 vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm
968 vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm
969 vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm
970 vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm
971 vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm
972 vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm
973 vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm
974 vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm
975 vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm
977 # *** Zvkned vector crypto extension ***
978 vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
979 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
980 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
981 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
982 vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
983 vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
984 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
985 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
986 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
987 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
988 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
990 # *** Zvknh vector crypto extension ***
991 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
992 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
993 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
995 # *** Zvksh vector crypto extension ***
996 vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
997 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
999 # *** Zvkg vector crypto extension ***
1000 vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
1001 vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
1003 # *** Zvksed vector crypto extension ***
1004 vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1
1005 vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1
1006 vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1
1008 # *** RV32 Zacas Standard Extension ***
1009 amocas_w 00101 . . ..... ..... 010 ..... 0101111 @atom_st
1010 amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st
1011 # *** RV64 Zacas Standard Extension ***
1012 amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st