target/ppc: Add basic support for "new format" HPTE as found on POWER9
[qemu/kevin.git] / target / ppc / mmu-hash64.c
blob3c057a8c704c882fb386f65979ec7d2572e75cf5
1 /*
2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/hw_accel.h"
26 #include "kvm_ppc.h"
27 #include "mmu-hash64.h"
28 #include "exec/log.h"
29 #include "hw/hw.h"
30 #include "mmu-book3s-v3.h"
32 //#define DEBUG_SLB
34 #ifdef DEBUG_SLB
35 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
36 #else
37 # define LOG_SLB(...) do { } while (0)
38 #endif
41 * SLB handling
44 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
46 CPUPPCState *env = &cpu->env;
47 uint64_t esid_256M, esid_1T;
48 int n;
50 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
52 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
53 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
55 for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
56 ppc_slb_t *slb = &env->slb[n];
58 LOG_SLB("%s: slot %d %016" PRIx64 " %016"
59 PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
60 /* We check for 1T matches on all MMUs here - if the MMU
61 * doesn't have 1T segment support, we will have prevented 1T
62 * entries from being inserted in the slbmte code. */
63 if (((slb->esid == esid_256M) &&
64 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
65 || ((slb->esid == esid_1T) &&
66 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
67 return slb;
71 return NULL;
74 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
76 CPUPPCState *env = &cpu->env;
77 int i;
78 uint64_t slbe, slbv;
80 cpu_synchronize_state(CPU(cpu));
82 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
83 for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
84 slbe = env->slb[i].esid;
85 slbv = env->slb[i].vsid;
86 if (slbe == 0 && slbv == 0) {
87 continue;
89 cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
90 i, slbe, slbv);
94 void helper_slbia(CPUPPCState *env)
96 PowerPCCPU *cpu = ppc_env_get_cpu(env);
97 int n;
99 /* XXX: Warning: slbia never invalidates the first segment */
100 for (n = 1; n < cpu->hash64_opts->slb_size; n++) {
101 ppc_slb_t *slb = &env->slb[n];
103 if (slb->esid & SLB_ESID_V) {
104 slb->esid &= ~SLB_ESID_V;
105 /* XXX: given the fact that segment size is 256 MB or 1TB,
106 * and we still don't have a tlb_flush_mask(env, n, mask)
107 * in QEMU, we just invalidate all TLBs
109 env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
114 static void __helper_slbie(CPUPPCState *env, target_ulong addr,
115 target_ulong global)
117 PowerPCCPU *cpu = ppc_env_get_cpu(env);
118 ppc_slb_t *slb;
120 slb = slb_lookup(cpu, addr);
121 if (!slb) {
122 return;
125 if (slb->esid & SLB_ESID_V) {
126 slb->esid &= ~SLB_ESID_V;
128 /* XXX: given the fact that segment size is 256 MB or 1TB,
129 * and we still don't have a tlb_flush_mask(env, n, mask)
130 * in QEMU, we just invalidate all TLBs
132 env->tlb_need_flush |=
133 (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH);
137 void helper_slbie(CPUPPCState *env, target_ulong addr)
139 __helper_slbie(env, addr, false);
142 void helper_slbieg(CPUPPCState *env, target_ulong addr)
144 __helper_slbie(env, addr, true);
147 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
148 target_ulong esid, target_ulong vsid)
150 CPUPPCState *env = &cpu->env;
151 ppc_slb_t *slb = &env->slb[slot];
152 const PPCHash64SegmentPageSizes *sps = NULL;
153 int i;
155 if (slot >= cpu->hash64_opts->slb_size) {
156 return -1; /* Bad slot number */
158 if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
159 return -1; /* Reserved bits set */
161 if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
162 return -1; /* Bad segment size */
164 if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) {
165 return -1; /* 1T segment on MMU that doesn't support it */
168 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
169 const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
171 if (!sps1->page_shift) {
172 break;
175 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
176 sps = sps1;
177 break;
181 if (!sps) {
182 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
183 " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
184 slot, esid, vsid);
185 return -1;
188 slb->esid = esid;
189 slb->vsid = vsid;
190 slb->sps = sps;
192 LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx
193 " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid,
194 slb->esid, slb->vsid);
196 return 0;
199 static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
200 target_ulong *rt)
202 CPUPPCState *env = &cpu->env;
203 int slot = rb & 0xfff;
204 ppc_slb_t *slb = &env->slb[slot];
206 if (slot >= cpu->hash64_opts->slb_size) {
207 return -1;
210 *rt = slb->esid;
211 return 0;
214 static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
215 target_ulong *rt)
217 CPUPPCState *env = &cpu->env;
218 int slot = rb & 0xfff;
219 ppc_slb_t *slb = &env->slb[slot];
221 if (slot >= cpu->hash64_opts->slb_size) {
222 return -1;
225 *rt = slb->vsid;
226 return 0;
229 static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
230 target_ulong *rt)
232 CPUPPCState *env = &cpu->env;
233 ppc_slb_t *slb;
235 if (!msr_is_64bit(env, env->msr)) {
236 rb &= 0xffffffff;
238 slb = slb_lookup(cpu, rb);
239 if (slb == NULL) {
240 *rt = (target_ulong)-1ul;
241 } else {
242 *rt = slb->vsid;
244 return 0;
247 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
249 PowerPCCPU *cpu = ppc_env_get_cpu(env);
251 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
252 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
253 POWERPC_EXCP_INVAL, GETPC());
257 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
259 PowerPCCPU *cpu = ppc_env_get_cpu(env);
260 target_ulong rt = 0;
262 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
263 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
264 POWERPC_EXCP_INVAL, GETPC());
266 return rt;
269 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
271 PowerPCCPU *cpu = ppc_env_get_cpu(env);
272 target_ulong rt = 0;
274 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
275 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
276 POWERPC_EXCP_INVAL, GETPC());
278 return rt;
281 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
283 PowerPCCPU *cpu = ppc_env_get_cpu(env);
284 target_ulong rt = 0;
286 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
287 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
288 POWERPC_EXCP_INVAL, GETPC());
290 return rt;
293 /* Check No-Execute or Guarded Storage */
294 static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
295 ppc_hash_pte64_t pte)
297 /* Exec permissions CANNOT take away read or write permissions */
298 return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ?
299 PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC;
302 /* Check Basic Storage Protection */
303 static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
304 ppc_slb_t *slb, ppc_hash_pte64_t pte)
306 CPUPPCState *env = &cpu->env;
307 unsigned pp, key;
308 /* Some pp bit combinations have undefined behaviour, so default
309 * to no access in those cases */
310 int prot = 0;
312 key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
313 : (slb->vsid & SLB_VSID_KS));
314 pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
316 if (key == 0) {
317 switch (pp) {
318 case 0x0:
319 case 0x1:
320 case 0x2:
321 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
322 break;
324 case 0x3:
325 case 0x6:
326 prot = PAGE_READ | PAGE_EXEC;
327 break;
329 } else {
330 switch (pp) {
331 case 0x0:
332 case 0x6:
333 break;
335 case 0x1:
336 case 0x3:
337 prot = PAGE_READ | PAGE_EXEC;
338 break;
340 case 0x2:
341 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
342 break;
346 return prot;
349 /* Check the instruction access permissions specified in the IAMR */
350 static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key)
352 CPUPPCState *env = &cpu->env;
353 int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3;
356 * An instruction fetch is permitted if the IAMR bit is 0.
357 * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit
358 * can only take away EXEC permissions not READ or WRITE permissions.
359 * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since
360 * EXEC permissions are allowed.
362 return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE :
363 PAGE_READ | PAGE_WRITE | PAGE_EXEC;
366 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
368 CPUPPCState *env = &cpu->env;
369 int key, amrbits;
370 int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
372 /* Only recent MMUs implement Virtual Page Class Key Protection */
373 if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) {
374 return prot;
377 key = HPTE64_R_KEY(pte.pte1);
378 amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
380 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
381 /* env->spr[SPR_AMR]); */
384 * A store is permitted if the AMR bit is 0. Remove write
385 * protection if it is set.
387 if (amrbits & 0x2) {
388 prot &= ~PAGE_WRITE;
391 * A load is permitted if the AMR bit is 0. Remove read
392 * protection if it is set.
394 if (amrbits & 0x1) {
395 prot &= ~PAGE_READ;
398 switch (env->mmu_model) {
400 * MMU version 2.07 and later support IAMR
401 * Check if the IAMR allows the instruction access - it will return
402 * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0
403 * if it does (and prot will be unchanged indicating execution support).
405 case POWERPC_MMU_2_07:
406 case POWERPC_MMU_3_00:
407 prot &= ppc_hash64_iamr_prot(cpu, key);
408 break;
409 default:
410 break;
413 return prot;
416 const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
417 hwaddr ptex, int n)
419 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
420 hwaddr base = ppc_hash64_hpt_base(cpu);
421 hwaddr plen = n * HASH_PTE_SIZE_64;
422 const ppc_hash_pte64_t *hptes;
424 if (cpu->vhyp) {
425 PPCVirtualHypervisorClass *vhc =
426 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
427 return vhc->map_hptes(cpu->vhyp, ptex, n);
430 if (!base) {
431 return NULL;
434 hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
435 MEMTXATTRS_UNSPECIFIED);
436 if (plen < (n * HASH_PTE_SIZE_64)) {
437 hw_error("%s: Unable to map all requested HPTEs\n", __func__);
439 return hptes;
442 void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
443 hwaddr ptex, int n)
445 if (cpu->vhyp) {
446 PPCVirtualHypervisorClass *vhc =
447 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
448 vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n);
449 return;
452 address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64,
453 false, n * HASH_PTE_SIZE_64);
456 static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
457 uint64_t pte0, uint64_t pte1)
459 int i;
461 if (!(pte0 & HPTE64_V_LARGE)) {
462 if (sps->page_shift != 12) {
463 /* 4kiB page in a non 4kiB segment */
464 return 0;
466 /* Normal 4kiB page */
467 return 12;
470 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
471 const PPCHash64PageSize *ps = &sps->enc[i];
472 uint64_t mask;
474 if (!ps->page_shift) {
475 break;
478 if (ps->page_shift == 12) {
479 /* L bit is set so this can't be a 4kiB page */
480 continue;
483 mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
485 if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
486 return ps->page_shift;
490 return 0; /* Bad page size encoding */
493 static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1)
495 /* Insert B into pte0 */
496 *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) |
497 ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) <<
498 (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT));
500 /* Remove B from pte1 */
501 *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK;
505 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
506 const PPCHash64SegmentPageSizes *sps,
507 target_ulong ptem,
508 ppc_hash_pte64_t *pte, unsigned *pshift)
510 int i;
511 const ppc_hash_pte64_t *pteg;
512 target_ulong pte0, pte1;
513 target_ulong ptex;
515 ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP;
516 pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
517 if (!pteg) {
518 return -1;
520 for (i = 0; i < HPTES_PER_GROUP; i++) {
521 pte0 = ppc_hash64_hpte0(cpu, pteg, i);
523 * pte0 contains the valid bit and must be read before pte1,
524 * otherwise we might see an old pte1 with a new valid bit and
525 * thus an inconsistent hpte value
527 smp_rmb();
528 pte1 = ppc_hash64_hpte1(cpu, pteg, i);
530 /* Convert format if necessary */
531 if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) {
532 ppc64_v3_new_to_old_hpte(&pte0, &pte1);
535 /* This compares V, B, H (secondary) and the AVPN */
536 if (HPTE64_V_COMPARE(pte0, ptem)) {
537 *pshift = hpte_page_shift(sps, pte0, pte1);
539 * If there is no match, ignore the PTE, it could simply
540 * be for a different segment size encoding and the
541 * architecture specifies we should not match. Linux will
542 * potentially leave behind PTEs for the wrong base page
543 * size when demoting segments.
545 if (*pshift == 0) {
546 continue;
548 /* We don't do anything with pshift yet as qemu TLB only deals
549 * with 4K pages anyway
551 pte->pte0 = pte0;
552 pte->pte1 = pte1;
553 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
554 return ptex + i;
557 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
559 * We didn't find a valid entry.
561 return -1;
564 static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
565 ppc_slb_t *slb, target_ulong eaddr,
566 ppc_hash_pte64_t *pte, unsigned *pshift)
568 CPUPPCState *env = &cpu->env;
569 hwaddr hash, ptex;
570 uint64_t vsid, epnmask, epn, ptem;
571 const PPCHash64SegmentPageSizes *sps = slb->sps;
573 /* The SLB store path should prevent any bad page size encodings
574 * getting in there, so: */
575 assert(sps);
577 /* If ISL is set in LPCR we need to clamp the page size to 4K */
578 if (env->spr[SPR_LPCR] & LPCR_ISL) {
579 /* We assume that when using TCG, 4k is first entry of SPS */
580 sps = &cpu->hash64_opts->sps[0];
581 assert(sps->page_shift == 12);
584 epnmask = ~((1ULL << sps->page_shift) - 1);
586 if (slb->vsid & SLB_VSID_B) {
587 /* 1TB segment */
588 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
589 epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
590 hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift);
591 } else {
592 /* 256M segment */
593 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
594 epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
595 hash = vsid ^ (epn >> sps->page_shift);
597 ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
598 ptem |= HPTE64_V_VALID;
600 /* Page address translation */
601 qemu_log_mask(CPU_LOG_MMU,
602 "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
603 " hash " TARGET_FMT_plx "\n",
604 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
606 /* Primary PTEG lookup */
607 qemu_log_mask(CPU_LOG_MMU,
608 "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
609 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
610 " hash=" TARGET_FMT_plx "\n",
611 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
612 vsid, ptem, hash);
613 ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
615 if (ptex == -1) {
616 /* Secondary PTEG lookup */
617 ptem |= HPTE64_V_SECONDARY;
618 qemu_log_mask(CPU_LOG_MMU,
619 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
620 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
621 " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
622 ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
624 ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
627 return ptex;
630 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
631 uint64_t pte0, uint64_t pte1)
633 int i;
635 if (!(pte0 & HPTE64_V_LARGE)) {
636 return 12;
640 * The encodings in env->sps need to be carefully chosen so that
641 * this gives an unambiguous result.
643 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
644 const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
645 unsigned shift;
647 if (!sps->page_shift) {
648 break;
651 shift = hpte_page_shift(sps, pte0, pte1);
652 if (shift) {
653 return shift;
657 return 0;
660 static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
662 CPUPPCState *env = &POWERPC_CPU(cs)->env;
663 bool vpm;
665 if (msr_ir) {
666 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
667 } else {
668 switch (env->mmu_model) {
669 case POWERPC_MMU_3_00:
670 /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
671 vpm = true;
672 break;
673 default:
674 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
675 break;
678 if (vpm && !msr_hv) {
679 cs->exception_index = POWERPC_EXCP_HISI;
680 } else {
681 cs->exception_index = POWERPC_EXCP_ISI;
683 env->error_code = error_code;
686 static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
688 CPUPPCState *env = &POWERPC_CPU(cs)->env;
689 bool vpm;
691 if (msr_dr) {
692 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
693 } else {
694 switch (env->mmu_model) {
695 case POWERPC_MMU_3_00:
696 /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
697 vpm = true;
698 break;
699 default:
700 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
701 break;
704 if (vpm && !msr_hv) {
705 cs->exception_index = POWERPC_EXCP_HDSI;
706 env->spr[SPR_HDAR] = dar;
707 env->spr[SPR_HDSISR] = dsisr;
708 } else {
709 cs->exception_index = POWERPC_EXCP_DSI;
710 env->spr[SPR_DAR] = dar;
711 env->spr[SPR_DSISR] = dsisr;
713 env->error_code = 0;
717 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
718 int rwx, int mmu_idx)
720 CPUState *cs = CPU(cpu);
721 CPUPPCState *env = &cpu->env;
722 ppc_slb_t *slb;
723 unsigned apshift;
724 hwaddr ptex;
725 ppc_hash_pte64_t pte;
726 int exec_prot, pp_prot, amr_prot, prot;
727 uint64_t new_pte1;
728 const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
729 hwaddr raddr;
731 assert((rwx == 0) || (rwx == 1) || (rwx == 2));
733 /* Note on LPCR usage: 970 uses HID4, but our special variant
734 * of store_spr copies relevant fields into env->spr[SPR_LPCR].
735 * Similarily we filter unimplemented bits when storing into
736 * LPCR depending on the MMU version. This code can thus just
737 * use the LPCR "as-is".
740 /* 1. Handle real mode accesses */
741 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
742 /* Translation is supposedly "off" */
743 /* In real mode the top 4 effective address bits are (mostly) ignored */
744 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
746 /* In HV mode, add HRMOR if top EA bit is clear */
747 if (msr_hv || !env->has_hv_mode) {
748 if (!(eaddr >> 63)) {
749 raddr |= env->spr[SPR_HRMOR];
751 } else {
752 /* Otherwise, check VPM for RMA vs VRMA */
753 if (env->spr[SPR_LPCR] & LPCR_VPM0) {
754 slb = &env->vrma_slb;
755 if (slb->sps) {
756 goto skip_slb_search;
758 /* Not much else to do here */
759 cs->exception_index = POWERPC_EXCP_MCHECK;
760 env->error_code = 0;
761 return 1;
762 } else if (raddr < env->rmls) {
763 /* RMA. Check bounds in RMLS */
764 raddr |= env->spr[SPR_RMOR];
765 } else {
766 /* The access failed, generate the approriate interrupt */
767 if (rwx == 2) {
768 ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
769 } else {
770 int dsisr = DSISR_PROTFAULT;
771 if (rwx == 1) {
772 dsisr |= DSISR_ISSTORE;
774 ppc_hash64_set_dsi(cs, eaddr, dsisr);
776 return 1;
779 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
780 PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
781 TARGET_PAGE_SIZE);
782 return 0;
785 /* 2. Translation is on, so look up the SLB */
786 slb = slb_lookup(cpu, eaddr);
787 if (!slb) {
788 /* No entry found, check if in-memory segment tables are in use */
789 if (ppc64_use_proc_tbl(cpu)) {
790 /* TODO - Unsupported */
791 error_report("Segment Table Support Unimplemented");
792 exit(1);
794 /* Segment still not found, generate the appropriate interrupt */
795 if (rwx == 2) {
796 cs->exception_index = POWERPC_EXCP_ISEG;
797 env->error_code = 0;
798 } else {
799 cs->exception_index = POWERPC_EXCP_DSEG;
800 env->error_code = 0;
801 env->spr[SPR_DAR] = eaddr;
803 return 1;
806 skip_slb_search:
808 /* 3. Check for segment level no-execute violation */
809 if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
810 ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
811 return 1;
814 /* 4. Locate the PTE in the hash table */
815 ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
816 if (ptex == -1) {
817 if (rwx == 2) {
818 ppc_hash64_set_isi(cs, SRR1_NOPTE);
819 } else {
820 int dsisr = DSISR_NOPTE;
821 if (rwx == 1) {
822 dsisr |= DSISR_ISSTORE;
824 ppc_hash64_set_dsi(cs, eaddr, dsisr);
826 return 1;
828 qemu_log_mask(CPU_LOG_MMU,
829 "found PTE at index %08" HWADDR_PRIx "\n", ptex);
831 /* 5. Check access permissions */
833 exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte);
834 pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
835 amr_prot = ppc_hash64_amr_prot(cpu, pte);
836 prot = exec_prot & pp_prot & amr_prot;
838 if ((need_prot[rwx] & ~prot) != 0) {
839 /* Access right violation */
840 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
841 if (rwx == 2) {
842 int srr1 = 0;
843 if (PAGE_EXEC & ~exec_prot) {
844 srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */
845 } else if (PAGE_EXEC & ~pp_prot) {
846 srr1 |= SRR1_PROTFAULT; /* Access violates access authority */
848 if (PAGE_EXEC & ~amr_prot) {
849 srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
851 ppc_hash64_set_isi(cs, srr1);
852 } else {
853 int dsisr = 0;
854 if (need_prot[rwx] & ~pp_prot) {
855 dsisr |= DSISR_PROTFAULT;
857 if (rwx == 1) {
858 dsisr |= DSISR_ISSTORE;
860 if (need_prot[rwx] & ~amr_prot) {
861 dsisr |= DSISR_AMR;
863 ppc_hash64_set_dsi(cs, eaddr, dsisr);
865 return 1;
868 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
870 /* 6. Update PTE referenced and changed bits if necessary */
872 new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */
873 if (rwx == 1) {
874 new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */
875 } else {
876 /* Treat the page as read-only for now, so that a later write
877 * will pass through this function again to set the C bit */
878 prot &= ~PAGE_WRITE;
881 if (new_pte1 != pte.pte1) {
882 ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1);
885 /* 7. Determine the real address from the PTE */
887 raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
889 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
890 prot, mmu_idx, 1ULL << apshift);
892 return 0;
895 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
897 CPUPPCState *env = &cpu->env;
898 ppc_slb_t *slb;
899 hwaddr ptex, raddr;
900 ppc_hash_pte64_t pte;
901 unsigned apshift;
903 /* Handle real mode */
904 if (msr_dr == 0) {
905 /* In real mode the top 4 effective address bits are ignored */
906 raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
908 /* In HV mode, add HRMOR if top EA bit is clear */
909 if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
910 return raddr | env->spr[SPR_HRMOR];
913 /* Otherwise, check VPM for RMA vs VRMA */
914 if (env->spr[SPR_LPCR] & LPCR_VPM0) {
915 slb = &env->vrma_slb;
916 if (!slb->sps) {
917 return -1;
919 } else if (raddr < env->rmls) {
920 /* RMA. Check bounds in RMLS */
921 return raddr | env->spr[SPR_RMOR];
922 } else {
923 return -1;
925 } else {
926 slb = slb_lookup(cpu, addr);
927 if (!slb) {
928 return -1;
932 ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
933 if (ptex == -1) {
934 return -1;
937 return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
938 & TARGET_PAGE_MASK;
941 void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
942 uint64_t pte0, uint64_t pte1)
944 hwaddr base = ppc_hash64_hpt_base(cpu);
945 hwaddr offset = ptex * HASH_PTE_SIZE_64;
947 if (cpu->vhyp) {
948 PPCVirtualHypervisorClass *vhc =
949 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
950 vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1);
951 return;
954 stq_phys(CPU(cpu)->as, base + offset, pte0);
955 stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1);
958 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
959 target_ulong pte0, target_ulong pte1)
962 * XXX: given the fact that there are too many segments to
963 * invalidate, and we still don't have a tlb_flush_mask(env, n,
964 * mask) in QEMU, we just invalidate all TLBs
966 cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
969 static void ppc_hash64_update_rmls(PowerPCCPU *cpu)
971 CPUPPCState *env = &cpu->env;
972 uint64_t lpcr = env->spr[SPR_LPCR];
975 * This is the full 4 bits encoding of POWER8. Previous
976 * CPUs only support a subset of these but the filtering
977 * is done when writing LPCR
979 switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
980 case 0x8: /* 32MB */
981 env->rmls = 0x2000000ull;
982 break;
983 case 0x3: /* 64MB */
984 env->rmls = 0x4000000ull;
985 break;
986 case 0x7: /* 128MB */
987 env->rmls = 0x8000000ull;
988 break;
989 case 0x4: /* 256MB */
990 env->rmls = 0x10000000ull;
991 break;
992 case 0x2: /* 1GB */
993 env->rmls = 0x40000000ull;
994 break;
995 case 0x1: /* 16GB */
996 env->rmls = 0x400000000ull;
997 break;
998 default:
999 /* What to do here ??? */
1000 env->rmls = 0;
1004 static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
1006 CPUPPCState *env = &cpu->env;
1007 const PPCHash64SegmentPageSizes *sps = NULL;
1008 target_ulong esid, vsid, lpcr;
1009 ppc_slb_t *slb = &env->vrma_slb;
1010 uint32_t vrmasd;
1011 int i;
1013 /* First clear it */
1014 slb->esid = slb->vsid = 0;
1015 slb->sps = NULL;
1017 /* Is VRMA enabled ? */
1018 lpcr = env->spr[SPR_LPCR];
1019 if (!(lpcr & LPCR_VPM0)) {
1020 return;
1023 /* Make one up. Mostly ignore the ESID which will not be
1024 * needed for translation
1026 vsid = SLB_VSID_VRMA;
1027 vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
1028 vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
1029 esid = SLB_ESID_V;
1031 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
1032 const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
1034 if (!sps1->page_shift) {
1035 break;
1038 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
1039 sps = sps1;
1040 break;
1044 if (!sps) {
1045 error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
1046 " vsid 0x"TARGET_FMT_lx, esid, vsid);
1047 return;
1050 slb->vsid = vsid;
1051 slb->esid = esid;
1052 slb->sps = sps;
1055 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
1057 CPUPPCState *env = &cpu->env;
1058 uint64_t lpcr = 0;
1060 /* Filter out bits */
1061 switch (env->mmu_model) {
1062 case POWERPC_MMU_64B: /* 970 */
1063 if (val & 0x40) {
1064 lpcr |= LPCR_LPES0;
1066 if (val & 0x8000000000000000ull) {
1067 lpcr |= LPCR_LPES1;
1069 if (val & 0x20) {
1070 lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
1072 if (val & 0x4000000000000000ull) {
1073 lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
1075 if (val & 0x2000000000000000ull) {
1076 lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
1078 env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
1080 /* XXX We could also write LPID from HID4 here
1081 * but since we don't tag any translation on it
1082 * it doesn't actually matter
1084 /* XXX For proper emulation of 970 we also need
1085 * to dig HRMOR out of HID5
1087 break;
1088 case POWERPC_MMU_2_03: /* P5p */
1089 lpcr = val & (LPCR_RMLS | LPCR_ILE |
1090 LPCR_LPES0 | LPCR_LPES1 |
1091 LPCR_RMI | LPCR_HDICE);
1092 break;
1093 case POWERPC_MMU_2_06: /* P7 */
1094 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
1095 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1096 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
1097 LPCR_MER | LPCR_TC |
1098 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
1099 break;
1100 case POWERPC_MMU_2_07: /* P8 */
1101 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
1102 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1103 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
1104 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
1105 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
1106 break;
1107 case POWERPC_MMU_3_00: /* P9 */
1108 lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
1109 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
1110 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR |
1111 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
1112 LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
1113 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
1115 * If we have a virtual hypervisor, we need to bring back RMLS. It
1116 * doesn't exist on an actual P9 but that's all we know how to
1117 * configure with softmmu at the moment
1119 if (cpu->vhyp) {
1120 lpcr |= (val & LPCR_RMLS);
1122 break;
1123 default:
1126 env->spr[SPR_LPCR] = lpcr;
1127 ppc_hash64_update_rmls(cpu);
1128 ppc_hash64_update_vrma(cpu);
1131 void helper_store_lpcr(CPUPPCState *env, target_ulong val)
1133 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1135 ppc_store_lpcr(cpu, val);
1138 void ppc_hash64_init(PowerPCCPU *cpu)
1140 CPUPPCState *env = &cpu->env;
1141 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
1143 if (!pcc->hash64_opts) {
1144 assert(!(env->mmu_model & POWERPC_MMU_64));
1145 return;
1148 cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
1151 void ppc_hash64_finalize(PowerPCCPU *cpu)
1153 g_free(cpu->hash64_opts);
1156 const PPCHash64Options ppc_hash64_opts_basic = {
1157 .flags = 0,
1158 .slb_size = 64,
1159 .sps = {
1160 { .page_shift = 12, /* 4K */
1161 .slb_enc = 0,
1162 .enc = { { .page_shift = 12, .pte_enc = 0 } }
1164 { .page_shift = 24, /* 16M */
1165 .slb_enc = 0x100,
1166 .enc = { { .page_shift = 24, .pte_enc = 0 } }
1171 const PPCHash64Options ppc_hash64_opts_POWER7 = {
1172 .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
1173 .slb_size = 32,
1174 .sps = {
1176 .page_shift = 12, /* 4K */
1177 .slb_enc = 0,
1178 .enc = { { .page_shift = 12, .pte_enc = 0 },
1179 { .page_shift = 16, .pte_enc = 0x7 },
1180 { .page_shift = 24, .pte_enc = 0x38 }, },
1183 .page_shift = 16, /* 64K */
1184 .slb_enc = SLB_VSID_64K,
1185 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
1186 { .page_shift = 24, .pte_enc = 0x8 }, },
1189 .page_shift = 24, /* 16M */
1190 .slb_enc = SLB_VSID_16M,
1191 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
1194 .page_shift = 34, /* 16G */
1195 .slb_enc = SLB_VSID_16G,
1196 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
1201 void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
1202 bool (*cb)(void *, uint32_t, uint32_t),
1203 void *opaque)
1205 PPCHash64Options *opts = cpu->hash64_opts;
1206 int i;
1207 int n = 0;
1208 bool ci_largepage = false;
1210 assert(opts);
1212 n = 0;
1213 for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
1214 PPCHash64SegmentPageSizes *sps = &opts->sps[i];
1215 int j;
1216 int m = 0;
1218 assert(n <= i);
1220 if (!sps->page_shift) {
1221 break;
1224 for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
1225 PPCHash64PageSize *ps = &sps->enc[j];
1227 assert(m <= j);
1228 if (!ps->page_shift) {
1229 break;
1232 if (cb(opaque, sps->page_shift, ps->page_shift)) {
1233 if (ps->page_shift >= 16) {
1234 ci_largepage = true;
1236 sps->enc[m++] = *ps;
1240 /* Clear rest of the row */
1241 for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
1242 memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
1245 if (m) {
1246 n++;
1250 /* Clear the rest of the table */
1251 for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
1252 memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
1255 if (!ci_largepage) {
1256 opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;