1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
45 /* Supported chipsets: */
46 #include "hw/acpi/piix4.h"
47 #include "hw/acpi/pcihp.h"
48 #include "hw/i386/ich9.h"
49 #include "hw/pci/pci_bus.h"
50 #include "hw/pci-host/q35.h"
51 #include "hw/i386/intel_iommu.h"
53 #include "hw/i386/q35-acpi-dsdt.hex"
54 #include "hw/i386/acpi-dsdt.hex"
56 #include "hw/acpi/aml-build.h"
58 #include "qapi/qmp/qint.h"
59 #include "qom/qom-qobject.h"
61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67 #define ACPI_BUILD_ALIGN_SIZE 0x1000
69 #define ACPI_BUILD_TABLE_SIZE 0x20000
71 /* #define DEBUG_ACPI_BUILD */
72 #ifdef DEBUG_ACPI_BUILD
73 #define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
76 #define ACPI_BUILD_DPRINTF(fmt, ...)
79 typedef struct AcpiCpuInfo
{
80 DECLARE_BITMAP(found_cpus
, ACPI_CPU_HOTPLUG_ID_LIMIT
);
83 typedef struct AcpiMcfgInfo
{
88 typedef struct AcpiPmInfo
{
94 uint8_t acpi_enable_cmd
;
95 uint8_t acpi_disable_cmd
;
97 uint32_t gpe0_blk_len
;
99 uint16_t cpu_hp_io_base
;
100 uint16_t cpu_hp_io_len
;
101 uint16_t mem_hp_io_base
;
102 uint16_t mem_hp_io_len
;
103 uint16_t pcihp_io_base
;
104 uint16_t pcihp_io_len
;
107 typedef struct AcpiMiscInfo
{
110 const unsigned char *dsdt_code
;
112 uint16_t pvpanic_port
;
113 uint16_t applesmc_io_base
;
116 typedef struct AcpiBuildPciBusHotplugState
{
117 GArray
*device_table
;
118 GArray
*notify_table
;
119 struct AcpiBuildPciBusHotplugState
*parent
;
120 bool pcihp_bridge_en
;
121 } AcpiBuildPciBusHotplugState
;
123 static void acpi_get_dsdt(AcpiMiscInfo
*info
)
125 Object
*piix
= piix4_pm_find();
126 Object
*lpc
= ich9_lpc_find();
127 assert(!!piix
!= !!lpc
);
130 info
->dsdt_code
= AcpiDsdtAmlCode
;
131 info
->dsdt_size
= sizeof AcpiDsdtAmlCode
;
134 info
->dsdt_code
= Q35AcpiDsdtAmlCode
;
135 info
->dsdt_size
= sizeof Q35AcpiDsdtAmlCode
;
140 int acpi_add_cpu_info(Object
*o
, void *opaque
)
142 AcpiCpuInfo
*cpu
= opaque
;
145 if (object_dynamic_cast(o
, TYPE_CPU
)) {
146 apic_id
= object_property_get_int(o
, "apic-id", NULL
);
147 assert(apic_id
< ACPI_CPU_HOTPLUG_ID_LIMIT
);
149 set_bit(apic_id
, cpu
->found_cpus
);
152 object_child_foreach(o
, acpi_add_cpu_info
, opaque
);
156 static void acpi_get_cpu_info(AcpiCpuInfo
*cpu
)
158 Object
*root
= object_get_root();
160 memset(cpu
->found_cpus
, 0, sizeof cpu
->found_cpus
);
161 object_child_foreach(root
, acpi_add_cpu_info
, cpu
);
164 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
166 Object
*piix
= piix4_pm_find();
167 Object
*lpc
= ich9_lpc_find();
171 pm
->pcihp_io_base
= 0;
172 pm
->pcihp_io_len
= 0;
175 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
177 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
179 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
183 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
187 pm
->cpu_hp_io_len
= ACPI_GPE_PROC_LEN
;
188 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
189 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
191 /* Fill in optional s3/s4 related properties */
192 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
194 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
196 pm
->s3_disabled
= false;
199 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
201 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
203 pm
->s4_disabled
= false;
206 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
208 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
214 /* Fill in mandatory properties */
215 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
217 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
218 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
220 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
221 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
223 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
225 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
227 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
229 pm
->pcihp_bridge_en
=
230 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
234 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
236 info
->has_hpet
= hpet_find();
237 info
->has_tpm
= tpm_find();
238 info
->pvpanic_port
= pvpanic_port();
239 info
->applesmc_io_base
= applesmc_port();
242 static void acpi_get_pci_info(PcPciInfo
*info
)
247 pci_host
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
248 g_assert(!ambiguous
);
251 info
->w32
.begin
= object_property_get_int(pci_host
,
252 PCI_HOST_PROP_PCI_HOLE_START
,
254 info
->w32
.end
= object_property_get_int(pci_host
,
255 PCI_HOST_PROP_PCI_HOLE_END
,
257 info
->w64
.begin
= object_property_get_int(pci_host
,
258 PCI_HOST_PROP_PCI_HOLE64_START
,
260 info
->w64
.end
= object_property_get_int(pci_host
,
261 PCI_HOST_PROP_PCI_HOLE64_END
,
265 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
267 static void acpi_align_size(GArray
*blob
, unsigned align
)
269 /* Align size to multiple of given size. This reduces the chance
270 * we need to change size in the future (breaking cross version migration).
272 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
277 build_facs(GArray
*table_data
, GArray
*linker
, PcGuestInfo
*guest_info
)
279 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
280 memcpy(&facs
->signature
, "FACS", 4);
281 facs
->length
= cpu_to_le32(sizeof(*facs
));
284 /* Load chipset information in FADT */
285 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
289 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
290 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
291 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
292 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
293 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
294 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
295 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
296 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
297 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
298 /* EVT, CNT, TMR length matches hw/acpi/core.c */
299 fadt
->pm1_evt_len
= 4;
300 fadt
->pm1_cnt_len
= 2;
301 fadt
->pm_tmr_len
= 4;
302 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
303 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
304 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
305 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
306 (1 << ACPI_FADT_F_PROC_C1
) |
307 (1 << ACPI_FADT_F_SLP_BUTTON
) |
308 (1 << ACPI_FADT_F_RTC_S4
));
309 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
310 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
311 * For more than 8 CPUs, "Clustered Logical" mode has to be used
314 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
321 build_fadt(GArray
*table_data
, GArray
*linker
, AcpiPmInfo
*pm
,
322 unsigned facs
, unsigned dsdt
)
324 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
326 fadt
->firmware_ctrl
= cpu_to_le32(facs
);
327 /* FACS address to be filled by Guest linker */
328 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
329 ACPI_BUILD_TABLE_FILE
,
330 table_data
, &fadt
->firmware_ctrl
,
331 sizeof fadt
->firmware_ctrl
);
333 fadt
->dsdt
= cpu_to_le32(dsdt
);
334 /* DSDT address to be filled by Guest linker */
335 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
336 ACPI_BUILD_TABLE_FILE
,
337 table_data
, &fadt
->dsdt
,
340 fadt_setup(fadt
, pm
);
342 build_header(linker
, table_data
,
343 (void *)fadt
, "FACP", sizeof(*fadt
), 1);
347 build_madt(GArray
*table_data
, GArray
*linker
, AcpiCpuInfo
*cpu
,
348 PcGuestInfo
*guest_info
)
350 int madt_start
= table_data
->len
;
352 AcpiMultipleApicTable
*madt
;
353 AcpiMadtIoApic
*io_apic
;
354 AcpiMadtIntsrcovr
*intsrcovr
;
355 AcpiMadtLocalNmi
*local_nmi
;
358 madt
= acpi_data_push(table_data
, sizeof *madt
);
359 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
360 madt
->flags
= cpu_to_le32(1);
362 for (i
= 0; i
< guest_info
->apic_id_limit
; i
++) {
363 AcpiMadtProcessorApic
*apic
= acpi_data_push(table_data
, sizeof *apic
);
364 apic
->type
= ACPI_APIC_PROCESSOR
;
365 apic
->length
= sizeof(*apic
);
366 apic
->processor_id
= i
;
367 apic
->local_apic_id
= i
;
368 if (test_bit(i
, cpu
->found_cpus
)) {
369 apic
->flags
= cpu_to_le32(1);
371 apic
->flags
= cpu_to_le32(0);
374 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
375 io_apic
->type
= ACPI_APIC_IO
;
376 io_apic
->length
= sizeof(*io_apic
);
377 #define ACPI_BUILD_IOAPIC_ID 0x0
378 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
379 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
380 io_apic
->interrupt
= cpu_to_le32(0);
382 if (guest_info
->apic_xrupt_override
) {
383 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
384 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
385 intsrcovr
->length
= sizeof(*intsrcovr
);
386 intsrcovr
->source
= 0;
387 intsrcovr
->gsi
= cpu_to_le32(2);
388 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
390 for (i
= 1; i
< 16; i
++) {
391 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
392 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
393 /* No need for a INT source override structure. */
396 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
397 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
398 intsrcovr
->length
= sizeof(*intsrcovr
);
399 intsrcovr
->source
= i
;
400 intsrcovr
->gsi
= cpu_to_le32(i
);
401 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
404 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
405 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
406 local_nmi
->length
= sizeof(*local_nmi
);
407 local_nmi
->processor_id
= 0xff; /* all processors */
408 local_nmi
->flags
= cpu_to_le16(0);
409 local_nmi
->lint
= 1; /* ACPI_LINT1 */
411 build_header(linker
, table_data
,
412 (void *)(table_data
->data
+ madt_start
), "APIC",
413 table_data
->len
- madt_start
, 1);
416 #include "hw/i386/ssdt-tpm.hex"
418 /* Assign BSEL property to all buses. In the future, this can be changed
419 * to only assign to buses that support hotplug.
421 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
423 unsigned *bsel_alloc
= opaque
;
426 if (qbus_is_hotpluggable(BUS(bus
))) {
427 bus_bsel
= g_malloc(sizeof *bus_bsel
);
429 *bus_bsel
= (*bsel_alloc
)++;
430 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
437 static void acpi_set_pci_info(void)
439 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
440 unsigned bsel_alloc
= 0;
443 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
444 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
448 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
451 int32_t devfn
= PCI_DEVFN(slot
, 0);
453 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
)));
454 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
455 aml_append(method
, if_ctx
);
458 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
459 bool pcihp_bridge_en
)
461 Aml
*dev
, *notify_method
, *method
;
466 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
468 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
470 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
471 notify_method
= aml_method("DVNT", 2);
474 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
477 PCIDevice
*pdev
= bus
->devices
[i
];
478 int slot
= PCI_SLOT(i
);
479 bool hotplug_enabled_dev
;
483 if (bsel
) { /* add hotplug slots for non present devices */
484 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
485 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
486 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
487 method
= aml_method("_EJ0", 1);
489 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
491 aml_append(dev
, method
);
492 aml_append(parent_scope
, dev
);
494 build_append_pcihp_notify_entry(notify_method
, slot
);
499 pc
= PCI_DEVICE_GET_CLASS(pdev
);
500 dc
= DEVICE_GET_CLASS(pdev
);
502 /* When hotplug for bridges is enabled, bridges are
503 * described in ACPI separately (see build_pci_bus_end).
504 * In this case they aren't themselves hot-pluggable.
505 * Hotplugged bridges *are* hot-pluggable.
507 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
508 !DEVICE(pdev
)->hotplugged
;
510 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
512 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
516 /* start to compose PCI slot descriptor */
517 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
518 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
520 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
521 /* add VGA specific AML methods */
524 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
530 method
= aml_method("_S1D", 0);
531 aml_append(method
, aml_return(aml_int(0)));
532 aml_append(dev
, method
);
534 method
= aml_method("_S2D", 0);
535 aml_append(method
, aml_return(aml_int(0)));
536 aml_append(dev
, method
);
538 method
= aml_method("_S3D", 0);
539 aml_append(method
, aml_return(aml_int(s3d
)));
540 aml_append(dev
, method
);
541 } else if (hotplug_enabled_dev
) {
542 /* add _SUN/_EJ0 to make slot hotpluggable */
543 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
545 method
= aml_method("_EJ0", 1);
547 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
549 aml_append(dev
, method
);
552 build_append_pcihp_notify_entry(notify_method
, slot
);
554 } else if (bridge_in_acpi
) {
556 * device is coldplugged bridge,
557 * add child device descriptions into its scope
559 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
561 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
563 /* slot descriptor has been composed, add it into parent context */
564 aml_append(parent_scope
, dev
);
568 aml_append(parent_scope
, notify_method
);
571 /* Append PCNT method to notify about events on local and child buses.
572 * Add unconditionally for root since DSDT expects it.
574 method
= aml_method("PCNT", 0);
576 /* If bus supports hotplug select it and notify about local events */
578 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
579 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
581 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
584 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
588 /* Notify about child bus events in any case */
589 if (pcihp_bridge_en
) {
590 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
591 int32_t devfn
= sec
->parent_dev
->devfn
;
593 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
596 aml_append(parent_scope
, method
);
600 build_ssdt(GArray
*table_data
, GArray
*linker
,
601 AcpiCpuInfo
*cpu
, AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
602 PcPciInfo
*pci
, PcGuestInfo
*guest_info
)
604 MachineState
*machine
= MACHINE(qdev_get_machine());
605 uint32_t nr_mem
= machine
->ram_slots
;
606 unsigned acpi_cpus
= guest_info
->apic_id_limit
;
607 Aml
*ssdt
, *sb_scope
, *scope
, *pkg
, *dev
, *method
, *crs
, *field
, *ifctx
;
610 ssdt
= init_aml_allocator();
611 /* The current AML generator can cover the APIC ID range [0..255],
612 * inclusive, for VCPU hotplug. */
613 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT
> 256);
614 g_assert(acpi_cpus
<= ACPI_CPU_HOTPLUG_ID_LIMIT
);
616 /* Reserve space for header */
617 acpi_data_push(ssdt
->buf
, sizeof(AcpiTableHeader
));
619 scope
= aml_scope("\\_SB.PCI0");
620 /* build PCI0._CRS */
621 crs
= aml_resource_template();
623 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
624 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
625 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
628 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
629 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
630 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
632 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
633 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
634 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
636 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
637 AML_CACHEABLE
, AML_READ_WRITE
,
638 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
640 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
641 AML_NON_CACHEABLE
, AML_READ_WRITE
,
642 0, pci
->w32
.begin
, pci
->w32
.end
- 1, 0,
643 pci
->w32
.end
- pci
->w32
.begin
));
644 if (pci
->w64
.begin
) {
646 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
647 AML_CACHEABLE
, AML_READ_WRITE
,
648 0, pci
->w64
.begin
, pci
->w64
.end
- 1, 0,
649 pci
->w64
.end
- pci
->w64
.begin
));
651 aml_append(scope
, aml_name_decl("_CRS", crs
));
653 /* reserve GPE0 block resources */
654 dev
= aml_device("GPE0");
655 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
656 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
657 /* device present, functioning, decoding, not shown in UI */
658 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
659 crs
= aml_resource_template();
661 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
663 aml_append(dev
, aml_name_decl("_CRS", crs
));
664 aml_append(scope
, dev
);
666 /* reserve PCIHP resources */
667 if (pm
->pcihp_io_len
) {
668 dev
= aml_device("PHPR");
669 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
671 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
672 /* device present, functioning, decoding, not shown in UI */
673 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
674 crs
= aml_resource_template();
676 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
679 aml_append(dev
, aml_name_decl("_CRS", crs
));
680 aml_append(scope
, dev
);
682 aml_append(ssdt
, scope
);
684 /* create S3_ / S4_ / S5_ packages if necessary */
685 scope
= aml_scope("\\");
686 if (!pm
->s3_disabled
) {
687 pkg
= aml_package(4);
688 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
689 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
690 aml_append(pkg
, aml_int(0)); /* reserved */
691 aml_append(pkg
, aml_int(0)); /* reserved */
692 aml_append(scope
, aml_name_decl("_S3", pkg
));
695 if (!pm
->s4_disabled
) {
696 pkg
= aml_package(4);
697 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
698 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
699 aml_append(pkg
, aml_int(pm
->s4_val
));
700 aml_append(pkg
, aml_int(0)); /* reserved */
701 aml_append(pkg
, aml_int(0)); /* reserved */
702 aml_append(scope
, aml_name_decl("_S4", pkg
));
705 pkg
= aml_package(4);
706 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
707 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
708 aml_append(pkg
, aml_int(0)); /* reserved */
709 aml_append(pkg
, aml_int(0)); /* reserved */
710 aml_append(scope
, aml_name_decl("_S5", pkg
));
711 aml_append(ssdt
, scope
);
713 if (misc
->applesmc_io_base
) {
714 scope
= aml_scope("\\_SB.PCI0.ISA");
715 dev
= aml_device("SMC");
717 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
718 /* device present, functioning, decoding, not shown in UI */
719 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
721 crs
= aml_resource_template();
723 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
724 0x01, APPLESMC_MAX_DATA_LENGTH
)
726 aml_append(crs
, aml_irq_no_flags(6));
727 aml_append(dev
, aml_name_decl("_CRS", crs
));
729 aml_append(scope
, dev
);
730 aml_append(ssdt
, scope
);
733 if (misc
->pvpanic_port
) {
734 scope
= aml_scope("\\_SB.PCI0.ISA");
736 dev
= aml_device("PEVR");
737 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
739 crs
= aml_resource_template();
741 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
743 aml_append(dev
, aml_name_decl("_CRS", crs
));
745 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
746 misc
->pvpanic_port
, 1));
747 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_PRESERVE
);
748 aml_append(field
, aml_named_field("PEPT", 8));
749 aml_append(dev
, field
);
751 method
= aml_method("RDPT", 0);
752 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
753 aml_append(method
, aml_return(aml_local(0)));
754 aml_append(dev
, method
);
756 method
= aml_method("WRPT", 1);
757 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
758 aml_append(dev
, method
);
760 aml_append(scope
, dev
);
761 aml_append(ssdt
, scope
);
764 sb_scope
= aml_scope("\\_SB");
766 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
767 dev
= aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE
));
768 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
770 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
772 /* device present, functioning, decoding, not shown in UI */
773 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
774 crs
= aml_resource_template();
776 aml_io(AML_DECODE16
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_base
, 1,
779 aml_append(dev
, aml_name_decl("_CRS", crs
));
780 aml_append(sb_scope
, dev
);
781 /* declare CPU hotplug MMIO region and PRS field to access it */
782 aml_append(sb_scope
, aml_operation_region(
783 "PRST", AML_SYSTEM_IO
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_len
));
784 field
= aml_field("PRST", AML_BYTE_ACC
, AML_PRESERVE
);
785 aml_append(field
, aml_named_field("PRS", 256));
786 aml_append(sb_scope
, field
);
788 /* build Processor object for each processor */
789 for (i
= 0; i
< acpi_cpus
; i
++) {
790 dev
= aml_processor(i
, 0, 0, "CP%.02X", i
);
792 method
= aml_method("_MAT", 0);
793 aml_append(method
, aml_return(aml_call1("CPMA", aml_int(i
))));
794 aml_append(dev
, method
);
796 method
= aml_method("_STA", 0);
797 aml_append(method
, aml_return(aml_call1("CPST", aml_int(i
))));
798 aml_append(dev
, method
);
800 method
= aml_method("_EJ0", 1);
802 aml_return(aml_call2("CPEJ", aml_int(i
), aml_arg(0)))
804 aml_append(dev
, method
);
806 aml_append(sb_scope
, dev
);
810 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
812 /* Arg0 = Processor ID = APIC ID */
813 method
= aml_method("NTFY", 2);
814 for (i
= 0; i
< acpi_cpus
; i
++) {
815 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
817 aml_notify(aml_name("CP%.02X", i
), aml_arg(1))
819 aml_append(method
, ifctx
);
821 aml_append(sb_scope
, method
);
823 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
825 * Note: The ability to create variable-sized packages was first
826 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
827 * ith up to 255 elements. Windows guests up to win2k8 fail when
828 * VarPackageOp is used.
830 pkg
= acpi_cpus
<= 255 ? aml_package(acpi_cpus
) :
831 aml_varpackage(acpi_cpus
);
833 for (i
= 0; i
< acpi_cpus
; i
++) {
834 uint8_t b
= test_bit(i
, cpu
->found_cpus
) ? 0x01 : 0x00;
835 aml_append(pkg
, aml_int(b
));
837 aml_append(sb_scope
, aml_name_decl("CPON", pkg
));
839 /* build memory devices */
840 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
841 scope
= aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE
));
843 aml_name_decl(stringify(MEMORY_SLOTS_NUMBER
), aml_int(nr_mem
))
846 crs
= aml_resource_template();
848 aml_io(AML_DECODE16
, pm
->mem_hp_io_base
, pm
->mem_hp_io_base
, 0,
851 aml_append(scope
, aml_name_decl("_CRS", crs
));
853 aml_append(scope
, aml_operation_region(
854 stringify(MEMORY_HOTPLUG_IO_REGION
), AML_SYSTEM_IO
,
855 pm
->mem_hp_io_base
, pm
->mem_hp_io_len
)
858 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), AML_DWORD_ACC
,
860 aml_append(field
, /* read only */
861 aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW
), 32));
862 aml_append(field
, /* read only */
863 aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH
), 32));
864 aml_append(field
, /* read only */
865 aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW
), 32));
866 aml_append(field
, /* read only */
867 aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH
), 32));
868 aml_append(field
, /* read only */
869 aml_named_field(stringify(MEMORY_SLOT_PROXIMITY
), 32));
870 aml_append(scope
, field
);
872 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), AML_BYTE_ACC
,
874 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
875 aml_append(field
, /* 1 if enabled, read only */
876 aml_named_field(stringify(MEMORY_SLOT_ENABLED
), 1));
878 /*(read) 1 if has a insert event. (write) 1 to clear event */
879 aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT
), 1));
881 /* (read) 1 if has a remove event. (write) 1 to clear event */
882 aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT
), 1));
884 /* initiates device eject, write only */
885 aml_named_field(stringify(MEMORY_SLOT_EJECT
), 1));
886 aml_append(scope
, field
);
888 field
= aml_field(stringify(MEMORY_HOTPLUG_IO_REGION
), AML_DWORD_ACC
,
890 aml_append(field
, /* DIMM selector, write only */
891 aml_named_field(stringify(MEMORY_SLOT_SLECTOR
), 32));
892 aml_append(field
, /* _OST event code, write only */
893 aml_named_field(stringify(MEMORY_SLOT_OST_EVENT
), 32));
894 aml_append(field
, /* _OST status code, write only */
895 aml_named_field(stringify(MEMORY_SLOT_OST_STATUS
), 32));
896 aml_append(scope
, field
);
898 aml_append(sb_scope
, scope
);
900 for (i
= 0; i
< nr_mem
; i
++) {
901 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
904 dev
= aml_device("MP%02X", i
);
905 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
906 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
908 method
= aml_method("_CRS", 0);
909 s
= BASEPATH
stringify(MEMORY_SLOT_CRS_METHOD
);
910 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
911 aml_append(dev
, method
);
913 method
= aml_method("_STA", 0);
914 s
= BASEPATH
stringify(MEMORY_SLOT_STATUS_METHOD
);
915 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
916 aml_append(dev
, method
);
918 method
= aml_method("_PXM", 0);
919 s
= BASEPATH
stringify(MEMORY_SLOT_PROXIMITY_METHOD
);
920 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
921 aml_append(dev
, method
);
923 method
= aml_method("_OST", 3);
924 s
= BASEPATH
stringify(MEMORY_SLOT_OST_METHOD
);
925 aml_append(method
, aml_return(aml_call4(
926 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
928 aml_append(dev
, method
);
930 method
= aml_method("_EJ0", 1);
931 s
= BASEPATH
stringify(MEMORY_SLOT_EJECT_METHOD
);
932 aml_append(method
, aml_return(aml_call2(
933 s
, aml_name("_UID"), aml_arg(0))));
934 aml_append(dev
, method
);
936 aml_append(sb_scope
, dev
);
939 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
940 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
942 method
= aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD
), 2);
943 for (i
= 0; i
< nr_mem
; i
++) {
944 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
946 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
948 aml_append(method
, ifctx
);
950 aml_append(sb_scope
, method
);
957 pci_host
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
958 if (!ambiguous
&& pci_host
) {
959 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
963 Aml
*scope
= aml_scope("PCI0");
964 /* Scan all PCI buses. Generate tables to support hotplug. */
965 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
966 aml_append(sb_scope
, scope
);
969 aml_append(ssdt
, sb_scope
);
972 /* copy AML table into ACPI tables blob and patch header there */
973 g_array_append_vals(table_data
, ssdt
->buf
->data
, ssdt
->buf
->len
);
974 build_header(linker
, table_data
,
975 (void *)(table_data
->data
+ table_data
->len
- ssdt
->buf
->len
),
976 "SSDT", ssdt
->buf
->len
, 1);
977 free_aml_allocator();
981 build_hpet(GArray
*table_data
, GArray
*linker
)
985 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
986 /* Note timer_block_id value must be kept in sync with value advertised by
989 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
990 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
991 build_header(linker
, table_data
,
992 (void *)hpet
, "HPET", sizeof(*hpet
), 1);
996 build_tpm_tcpa(GArray
*table_data
, GArray
*linker
, GArray
*tcpalog
)
998 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
999 uint64_t log_area_start_address
= acpi_data_len(tcpalog
);
1001 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
1002 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
1003 tcpa
->log_area_start_address
= cpu_to_le64(log_area_start_address
);
1005 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, 1,
1006 false /* high memory */);
1008 /* log area start address to be filled by Guest linker */
1009 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
1010 ACPI_BUILD_TPMLOG_FILE
,
1011 table_data
, &tcpa
->log_area_start_address
,
1012 sizeof(tcpa
->log_area_start_address
));
1014 build_header(linker
, table_data
,
1015 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2);
1017 acpi_data_push(tcpalog
, TPM_LOG_AREA_MINIMUM_SIZE
);
1021 build_tpm_ssdt(GArray
*table_data
, GArray
*linker
)
1025 tpm_ptr
= acpi_data_push(table_data
, sizeof(ssdt_tpm_aml
));
1026 memcpy(tpm_ptr
, ssdt_tpm_aml
, sizeof(ssdt_tpm_aml
));
1030 MEM_AFFINITY_NOFLAGS
= 0,
1031 MEM_AFFINITY_ENABLED
= (1 << 0),
1032 MEM_AFFINITY_HOTPLUGGABLE
= (1 << 1),
1033 MEM_AFFINITY_NON_VOLATILE
= (1 << 2),
1034 } MemoryAffinityFlags
;
1037 acpi_build_srat_memory(AcpiSratMemoryAffinity
*numamem
, uint64_t base
,
1038 uint64_t len
, int node
, MemoryAffinityFlags flags
)
1040 numamem
->type
= ACPI_SRAT_MEMORY
;
1041 numamem
->length
= sizeof(*numamem
);
1042 memset(numamem
->proximity
, 0, 4);
1043 numamem
->proximity
[0] = node
;
1044 numamem
->flags
= cpu_to_le32(flags
);
1045 numamem
->base_addr
= cpu_to_le64(base
);
1046 numamem
->range_length
= cpu_to_le64(len
);
1050 build_srat(GArray
*table_data
, GArray
*linker
, PcGuestInfo
*guest_info
)
1052 AcpiSystemResourceAffinityTable
*srat
;
1053 AcpiSratProcessorAffinity
*core
;
1054 AcpiSratMemoryAffinity
*numamem
;
1058 int srat_start
, numa_start
, slots
;
1059 uint64_t mem_len
, mem_base
, next_base
;
1060 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1061 ram_addr_t hotplugabble_address_space_size
=
1062 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
1065 srat_start
= table_data
->len
;
1067 srat
= acpi_data_push(table_data
, sizeof *srat
);
1068 srat
->reserved1
= cpu_to_le32(1);
1069 core
= (void *)(srat
+ 1);
1071 for (i
= 0; i
< guest_info
->apic_id_limit
; ++i
) {
1072 core
= acpi_data_push(table_data
, sizeof *core
);
1073 core
->type
= ACPI_SRAT_PROCESSOR
;
1074 core
->length
= sizeof(*core
);
1075 core
->local_apic_id
= i
;
1076 curnode
= guest_info
->node_cpu
[i
];
1077 core
->proximity_lo
= curnode
;
1078 memset(core
->proximity_hi
, 0, 3);
1079 core
->local_sapic_eid
= 0;
1080 core
->flags
= cpu_to_le32(1);
1084 /* the memory map is a bit tricky, it contains at least one hole
1085 * from 640k-1M and possibly another one from 3.5G-4G.
1088 numa_start
= table_data
->len
;
1090 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1091 acpi_build_srat_memory(numamem
, 0, 640*1024, 0, MEM_AFFINITY_ENABLED
);
1092 next_base
= 1024 * 1024;
1093 for (i
= 1; i
< guest_info
->numa_nodes
+ 1; ++i
) {
1094 mem_base
= next_base
;
1095 mem_len
= guest_info
->node_mem
[i
- 1];
1097 mem_len
-= 1024 * 1024;
1099 next_base
= mem_base
+ mem_len
;
1101 /* Cut out the ACPI_PCI hole */
1102 if (mem_base
<= guest_info
->ram_size_below_4g
&&
1103 next_base
> guest_info
->ram_size_below_4g
) {
1104 mem_len
-= next_base
- guest_info
->ram_size_below_4g
;
1106 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1107 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1108 MEM_AFFINITY_ENABLED
);
1110 mem_base
= 1ULL << 32;
1111 mem_len
= next_base
- guest_info
->ram_size_below_4g
;
1112 next_base
+= (1ULL << 32) - guest_info
->ram_size_below_4g
;
1114 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1115 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1116 MEM_AFFINITY_ENABLED
);
1118 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
1119 for (; slots
< guest_info
->numa_nodes
+ 2; slots
++) {
1120 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1121 acpi_build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
1125 * Entry is required for Windows to enable memory hotplug in OS.
1126 * Memory devices may override proximity set by this entry,
1127 * providing _PXM method if necessary.
1129 if (hotplugabble_address_space_size
) {
1130 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1131 acpi_build_srat_memory(numamem
, pcms
->hotplug_memory_base
,
1132 hotplugabble_address_space_size
, 0,
1133 MEM_AFFINITY_HOTPLUGGABLE
|
1134 MEM_AFFINITY_ENABLED
);
1137 build_header(linker
, table_data
,
1138 (void *)(table_data
->data
+ srat_start
),
1140 table_data
->len
- srat_start
, 1);
1144 build_mcfg_q35(GArray
*table_data
, GArray
*linker
, AcpiMcfgInfo
*info
)
1146 AcpiTableMcfg
*mcfg
;
1148 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
1150 mcfg
= acpi_data_push(table_data
, len
);
1151 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
1152 /* Only a single allocation so no need to play with segments */
1153 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
1154 mcfg
->allocation
[0].start_bus_number
= 0;
1155 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
1157 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1158 * To avoid table size changes (which create migration issues),
1159 * always create the table even if there are no allocations,
1160 * but set the signature to a reserved value in this case.
1161 * ACPI spec requires OSPMs to ignore such tables.
1163 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
1164 /* Reserved signature: ignored by OSPM */
1169 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1);
1173 build_dmar_q35(GArray
*table_data
, GArray
*linker
)
1175 int dmar_start
= table_data
->len
;
1177 AcpiTableDmar
*dmar
;
1178 AcpiDmarHardwareUnit
*drhd
;
1180 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
1181 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
1182 dmar
->flags
= 0; /* No intr_remap for now */
1184 /* DMAR Remapping Hardware Unit Definition structure */
1185 drhd
= acpi_data_push(table_data
, sizeof(*drhd
));
1186 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
1187 drhd
->length
= cpu_to_le16(sizeof(*drhd
)); /* No device scope now */
1188 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
1189 drhd
->pci_segment
= cpu_to_le16(0);
1190 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
1192 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
1193 "DMAR", table_data
->len
- dmar_start
, 1);
1197 build_dsdt(GArray
*table_data
, GArray
*linker
, AcpiMiscInfo
*misc
)
1199 AcpiTableHeader
*dsdt
;
1201 assert(misc
->dsdt_code
&& misc
->dsdt_size
);
1203 dsdt
= acpi_data_push(table_data
, misc
->dsdt_size
);
1204 memcpy(dsdt
, misc
->dsdt_code
, misc
->dsdt_size
);
1206 memset(dsdt
, 0, sizeof *dsdt
);
1207 build_header(linker
, table_data
, dsdt
, "DSDT",
1208 misc
->dsdt_size
, 1);
1212 build_rsdp(GArray
*rsdp_table
, GArray
*linker
, unsigned rsdt
)
1214 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
1216 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, 16,
1217 true /* fseg memory */);
1219 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
1220 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
1221 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt
);
1222 /* Address to be filled by Guest linker */
1223 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_RSDP_FILE
,
1224 ACPI_BUILD_TABLE_FILE
,
1225 rsdp_table
, &rsdp
->rsdt_physical_address
,
1226 sizeof rsdp
->rsdt_physical_address
);
1228 /* Checksum to be filled by Guest linker */
1229 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
1230 rsdp
, rsdp
, sizeof *rsdp
, &rsdp
->checksum
);
1236 struct AcpiBuildState
{
1237 /* Copy of table in RAM (for patching). */
1238 MemoryRegion
*table_mr
;
1239 /* Is table patched? */
1241 PcGuestInfo
*guest_info
;
1243 MemoryRegion
*rsdp_mr
;
1244 MemoryRegion
*linker_mr
;
1247 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
1253 pci_host
= object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE
, &ambiguous
);
1254 g_assert(!ambiguous
);
1257 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
1261 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
1264 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
1266 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
1271 static bool acpi_has_iommu(void)
1274 Object
*intel_iommu
;
1276 intel_iommu
= object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE
,
1278 return intel_iommu
&& !ambiguous
;
1282 void acpi_build(PcGuestInfo
*guest_info
, AcpiBuildTables
*tables
)
1284 GArray
*table_offsets
;
1285 unsigned facs
, ssdt
, dsdt
, rsdt
;
1293 GArray
*tables_blob
= tables
->table_data
;
1295 acpi_get_cpu_info(&cpu
);
1296 acpi_get_pm_info(&pm
);
1297 acpi_get_dsdt(&misc
);
1298 acpi_get_misc_info(&misc
);
1299 acpi_get_pci_info(&pci
);
1301 table_offsets
= g_array_new(false, true /* clear */,
1303 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1305 bios_linker_loader_alloc(tables
->linker
, ACPI_BUILD_TABLE_FILE
,
1306 64 /* Ensure FACS is aligned */,
1307 false /* high memory */);
1310 * FACS is pointed to by FADT.
1311 * We place it first since it's the only table that has alignment
1314 facs
= tables_blob
->len
;
1315 build_facs(tables_blob
, tables
->linker
, guest_info
);
1317 /* DSDT is pointed to by FADT */
1318 dsdt
= tables_blob
->len
;
1319 build_dsdt(tables_blob
, tables
->linker
, &misc
);
1321 /* Count the size of the DSDT and SSDT, we will need it for legacy
1322 * sizing of ACPI tables.
1324 aml_len
+= tables_blob
->len
- dsdt
;
1326 /* ACPI tables pointed to by RSDT */
1327 acpi_add_table(table_offsets
, tables_blob
);
1328 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
);
1330 ssdt
= tables_blob
->len
;
1331 acpi_add_table(table_offsets
, tables_blob
);
1332 build_ssdt(tables_blob
, tables
->linker
, &cpu
, &pm
, &misc
, &pci
,
1334 aml_len
+= tables_blob
->len
- ssdt
;
1336 acpi_add_table(table_offsets
, tables_blob
);
1337 build_madt(tables_blob
, tables
->linker
, &cpu
, guest_info
);
1339 if (misc
.has_hpet
) {
1340 acpi_add_table(table_offsets
, tables_blob
);
1341 build_hpet(tables_blob
, tables
->linker
);
1344 acpi_add_table(table_offsets
, tables_blob
);
1345 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
1347 acpi_add_table(table_offsets
, tables_blob
);
1348 build_tpm_ssdt(tables_blob
, tables
->linker
);
1350 if (guest_info
->numa_nodes
) {
1351 acpi_add_table(table_offsets
, tables_blob
);
1352 build_srat(tables_blob
, tables
->linker
, guest_info
);
1354 if (acpi_get_mcfg(&mcfg
)) {
1355 acpi_add_table(table_offsets
, tables_blob
);
1356 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
1358 if (acpi_has_iommu()) {
1359 acpi_add_table(table_offsets
, tables_blob
);
1360 build_dmar_q35(tables_blob
, tables
->linker
);
1363 /* Add tables supplied by user (if any) */
1364 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
1365 unsigned len
= acpi_table_len(u
);
1367 acpi_add_table(table_offsets
, tables_blob
);
1368 g_array_append_vals(tables_blob
, u
, len
);
1371 /* RSDT is pointed to by RSDP */
1372 rsdt
= tables_blob
->len
;
1373 build_rsdt(tables_blob
, tables
->linker
, table_offsets
);
1375 /* RSDP is in FSEG memory, so allocate it separately */
1376 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
1378 /* We'll expose it all to Guest so we want to reduce
1379 * chance of size changes.
1381 * We used to align the tables to 4k, but of course this would
1382 * too simple to be enough. 4k turned out to be too small an
1383 * alignment very soon, and in fact it is almost impossible to
1384 * keep the table size stable for all (max_cpus, max_memory_slots)
1385 * combinations. So the table size is always 64k for pc-i440fx-2.1
1386 * and we give an error if the table grows beyond that limit.
1388 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1389 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1390 * than 2.0 and we can always pad the smaller tables with zeros. We can
1391 * then use the exact size of the 2.0 tables.
1393 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1395 if (guest_info
->legacy_acpi_table_size
) {
1396 /* Subtracting aml_len gives the size of fixed tables. Then add the
1397 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1399 int legacy_aml_len
=
1400 guest_info
->legacy_acpi_table_size
+
1401 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
1402 int legacy_table_size
=
1403 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
1404 ACPI_BUILD_ALIGN_SIZE
);
1405 if (tables_blob
->len
> legacy_table_size
) {
1406 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1407 error_report("Warning: migration may not work.");
1409 g_array_set_size(tables_blob
, legacy_table_size
);
1411 /* Make sure we have a buffer in case we need to resize the tables. */
1412 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
1413 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1414 error_report("Warning: ACPI tables are larger than 64k.");
1415 error_report("Warning: migration may not work.");
1416 error_report("Warning: please remove CPUs, NUMA nodes, "
1417 "memory slots or PCI bridges.");
1419 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
1422 acpi_align_size(tables
->linker
, ACPI_BUILD_ALIGN_SIZE
);
1424 /* Cleanup memory that's no longer used. */
1425 g_array_free(table_offsets
, true);
1428 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
1430 uint32_t size
= acpi_data_len(data
);
1432 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1433 memory_region_ram_resize(mr
, size
, &error_abort
);
1435 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
1436 memory_region_set_dirty(mr
, 0, size
);
1439 static void acpi_build_update(void *build_opaque
, uint32_t offset
)
1441 AcpiBuildState
*build_state
= build_opaque
;
1442 AcpiBuildTables tables
;
1444 /* No state to update or already patched? Nothing to do. */
1445 if (!build_state
|| build_state
->patched
) {
1448 build_state
->patched
= 1;
1450 acpi_build_tables_init(&tables
);
1452 acpi_build(build_state
->guest_info
, &tables
);
1454 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
1456 if (build_state
->rsdp
) {
1457 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
1459 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
1462 acpi_ram_update(build_state
->linker_mr
, tables
.linker
);
1463 acpi_build_tables_cleanup(&tables
, true);
1466 static void acpi_build_reset(void *build_opaque
)
1468 AcpiBuildState
*build_state
= build_opaque
;
1469 build_state
->patched
= 0;
1472 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
1473 GArray
*blob
, const char *name
,
1476 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
1477 name
, acpi_build_update
, build_state
);
1480 static const VMStateDescription vmstate_acpi_build
= {
1481 .name
= "acpi_build",
1483 .minimum_version_id
= 1,
1484 .fields
= (VMStateField
[]) {
1485 VMSTATE_UINT8(patched
, AcpiBuildState
),
1486 VMSTATE_END_OF_LIST()
1490 void acpi_setup(PcGuestInfo
*guest_info
)
1492 AcpiBuildTables tables
;
1493 AcpiBuildState
*build_state
;
1495 if (!guest_info
->fw_cfg
) {
1496 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1500 if (!guest_info
->has_acpi_build
) {
1501 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1505 if (!acpi_enabled
) {
1506 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1510 build_state
= g_malloc0(sizeof *build_state
);
1512 build_state
->guest_info
= guest_info
;
1514 acpi_set_pci_info();
1516 acpi_build_tables_init(&tables
);
1517 acpi_build(build_state
->guest_info
, &tables
);
1519 /* Now expose it all to Guest */
1520 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
1521 ACPI_BUILD_TABLE_FILE
,
1522 ACPI_BUILD_TABLE_MAX_SIZE
);
1523 assert(build_state
->table_mr
!= NULL
);
1525 build_state
->linker_mr
=
1526 acpi_add_rom_blob(build_state
, tables
.linker
, "etc/table-loader", 0);
1528 fw_cfg_add_file(guest_info
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
1529 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
1531 if (!guest_info
->rsdp_in_ram
) {
1533 * Keep for compatibility with old machine types.
1534 * Though RSDP is small, its contents isn't immutable, so
1535 * we'll update it along with the rest of tables on guest access.
1537 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
1539 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
1540 fw_cfg_add_file_callback(guest_info
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
1541 acpi_build_update
, build_state
,
1542 build_state
->rsdp
, rsdp_size
);
1543 build_state
->rsdp_mr
= NULL
;
1545 build_state
->rsdp
= NULL
;
1546 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
1547 ACPI_BUILD_RSDP_FILE
, 0);
1550 qemu_register_reset(acpi_build_reset
, build_state
);
1551 acpi_build_reset(build_state
);
1552 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
1554 /* Cleanup tables but don't free the memory: we track it
1557 acpi_build_tables_cleanup(&tables
, false);