4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "qemu-common.h"
25 static void openrisc_cpu_set_pc(CPUState
*cs
, vaddr value
)
27 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
32 static bool openrisc_cpu_has_work(CPUState
*cs
)
34 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
38 static void openrisc_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
40 info
->print_insn
= print_insn_or1k
;
43 /* CPUClass::reset() */
44 static void openrisc_cpu_reset(CPUState
*s
)
46 OpenRISCCPU
*cpu
= OPENRISC_CPU(s
);
47 OpenRISCCPUClass
*occ
= OPENRISC_CPU_GET_CLASS(cpu
);
51 memset(&cpu
->env
, 0, offsetof(CPUOpenRISCState
, end_reset_fields
));
54 cpu
->env
.sr
= SR_FO
| SR_SM
;
55 cpu
->env
.lock_addr
= -1;
56 s
->exception_index
= -1;
58 cpu
->env
.upr
= UPR_UP
| UPR_DMP
| UPR_IMP
| UPR_PICP
| UPR_TTP
|
60 cpu
->env
.dmmucfgr
= (DMMUCFGR_NTW
& (0 << 2))
61 | (DMMUCFGR_NTS
& (ctz32(TLB_SIZE
) << 2));
62 cpu
->env
.immucfgr
= (IMMUCFGR_NTW
& (0 << 2))
63 | (IMMUCFGR_NTS
& (ctz32(TLB_SIZE
) << 2));
65 #ifndef CONFIG_USER_ONLY
66 cpu
->env
.picmr
= 0x00000000;
67 cpu
->env
.picsr
= 0x00000000;
69 cpu
->env
.ttmr
= 0x00000000;
73 static void openrisc_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
75 CPUState
*cs
= CPU(dev
);
76 OpenRISCCPUClass
*occ
= OPENRISC_CPU_GET_CLASS(dev
);
77 Error
*local_err
= NULL
;
79 cpu_exec_realizefn(cs
, &local_err
);
80 if (local_err
!= NULL
) {
81 error_propagate(errp
, local_err
);
88 occ
->parent_realize(dev
, errp
);
91 static void openrisc_cpu_initfn(Object
*obj
)
93 CPUState
*cs
= CPU(obj
);
94 OpenRISCCPU
*cpu
= OPENRISC_CPU(obj
);
96 cs
->env_ptr
= &cpu
->env
;
101 static ObjectClass
*openrisc_cpu_class_by_name(const char *cpu_model
)
106 typename
= g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model
);
107 oc
= object_class_by_name(typename
);
109 if (oc
!= NULL
&& (!object_class_dynamic_cast(oc
, TYPE_OPENRISC_CPU
) ||
110 object_class_is_abstract(oc
))) {
116 static void or1200_initfn(Object
*obj
)
118 OpenRISCCPU
*cpu
= OPENRISC_CPU(obj
);
120 cpu
->env
.cpucfgr
= CPUCFGR_NSGF
| CPUCFGR_OB32S
| CPUCFGR_OF32S
|
124 static void openrisc_any_initfn(Object
*obj
)
126 OpenRISCCPU
*cpu
= OPENRISC_CPU(obj
);
128 cpu
->env
.cpucfgr
= CPUCFGR_NSGF
| CPUCFGR_OB32S
| CPUCFGR_EVBARP
;
131 static void openrisc_cpu_class_init(ObjectClass
*oc
, void *data
)
133 OpenRISCCPUClass
*occ
= OPENRISC_CPU_CLASS(oc
);
134 CPUClass
*cc
= CPU_CLASS(occ
);
135 DeviceClass
*dc
= DEVICE_CLASS(oc
);
137 device_class_set_parent_realize(dc
, openrisc_cpu_realizefn
,
138 &occ
->parent_realize
);
139 occ
->parent_reset
= cc
->reset
;
140 cc
->reset
= openrisc_cpu_reset
;
142 cc
->class_by_name
= openrisc_cpu_class_by_name
;
143 cc
->has_work
= openrisc_cpu_has_work
;
144 cc
->do_interrupt
= openrisc_cpu_do_interrupt
;
145 cc
->cpu_exec_interrupt
= openrisc_cpu_exec_interrupt
;
146 cc
->dump_state
= openrisc_cpu_dump_state
;
147 cc
->set_pc
= openrisc_cpu_set_pc
;
148 cc
->gdb_read_register
= openrisc_cpu_gdb_read_register
;
149 cc
->gdb_write_register
= openrisc_cpu_gdb_write_register
;
150 #ifdef CONFIG_USER_ONLY
151 cc
->handle_mmu_fault
= openrisc_cpu_handle_mmu_fault
;
153 cc
->get_phys_page_debug
= openrisc_cpu_get_phys_page_debug
;
154 dc
->vmsd
= &vmstate_openrisc_cpu
;
156 cc
->gdb_num_core_regs
= 32 + 3;
157 cc
->tcg_initialize
= openrisc_translate_init
;
158 cc
->disas_set_info
= openrisc_disas_set_info
;
161 /* Sort alphabetically by type name, except for "any". */
162 static gint
openrisc_cpu_list_compare(gconstpointer a
, gconstpointer b
)
164 ObjectClass
*class_a
= (ObjectClass
*)a
;
165 ObjectClass
*class_b
= (ObjectClass
*)b
;
166 const char *name_a
, *name_b
;
168 name_a
= object_class_get_name(class_a
);
169 name_b
= object_class_get_name(class_b
);
170 if (strcmp(name_a
, "any-" TYPE_OPENRISC_CPU
) == 0) {
172 } else if (strcmp(name_b
, "any-" TYPE_OPENRISC_CPU
) == 0) {
175 return strcmp(name_a
, name_b
);
179 static void openrisc_cpu_list_entry(gpointer data
, gpointer user_data
)
181 ObjectClass
*oc
= data
;
182 CPUListState
*s
= user_data
;
183 const char *typename
;
186 typename
= object_class_get_name(oc
);
187 name
= g_strndup(typename
,
188 strlen(typename
) - strlen("-" TYPE_OPENRISC_CPU
));
189 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
194 void cpu_openrisc_list(FILE *f
, fprintf_function cpu_fprintf
)
198 .cpu_fprintf
= cpu_fprintf
,
202 list
= object_class_get_list(TYPE_OPENRISC_CPU
, false);
203 list
= g_slist_sort(list
, openrisc_cpu_list_compare
);
204 (*cpu_fprintf
)(f
, "Available CPUs:\n");
205 g_slist_foreach(list
, openrisc_cpu_list_entry
, &s
);
209 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
211 .parent = TYPE_OPENRISC_CPU, \
212 .instance_init = initfn, \
213 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \
216 static const TypeInfo openrisc_cpus_type_infos
[] = {
217 { /* base class should be registered first */
218 .name
= TYPE_OPENRISC_CPU
,
220 .instance_size
= sizeof(OpenRISCCPU
),
221 .instance_init
= openrisc_cpu_initfn
,
223 .class_size
= sizeof(OpenRISCCPUClass
),
224 .class_init
= openrisc_cpu_class_init
,
226 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn
),
227 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn
),
230 DEFINE_TYPES(openrisc_cpus_type_infos
)