| commit | 1cc9e5d896695091eeb126f5c578b02ddd0fc0e4 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Wed, 23 May 2018 05:04:46 +0000 (22 22:04 -0700) | ||
| committer | Stafford Horne <shorne@gmail.com> | |
| Mon, 2 Jul 2018 15:05:28 +0000 (3 00:05 +0900) | ||
| tree | 71efab11d996bde34b4f58531487adb52cc80cdd | treesnapshot (tar.gz zip) |
| parent | 5ce5dad3527e024c297f73f9eb79098235efba6b | commitdiff |
target/openrisc: Increase the TLB size
The architecture supports 128 TLB entries. There is no reason
not to provide all of them. In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
v2:
- Change VMState version.
The architecture supports 128 TLB entries. There is no reason
not to provide all of them. In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
v2:
- Change VMState version.
| target/openrisc/cpu.c | diffblobblamehistory | |
| target/openrisc/cpu.h | diffblobblamehistory | |
| target/openrisc/machine.c | diffblobblamehistory |