hw/misc/aspeed_sdmc.c

   1 /*
   2  * ASPEED SDRAM Memory Controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later.  See
   7  * the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/module.h"
  13 #include "qemu/error-report.h"
  14 #include "hw/misc/aspeed_sdmc.h"
  15 #include "hw/misc/aspeed_scu.h"
  16 #include "hw/qdev-properties.h"
  17 #include "migration/vmstate.h"
  18 #include "qapi/error.h"
  19 #include "trace.h"
  20 #include "qemu/units.h"
  21 #include "qemu/cutils.h"
  22 #include "qapi/visitor.h"
  23
  24 /* Protection Key Register */
  25 #define R_PROT            (0x00 / 4)
  26 #define   PROT_UNLOCKED      0x01
  27 #define   PROT_HARDLOCKED    0x10  /* AST2600 */
  28 #define   PROT_SOFTLOCKED    0x00
  29
  30 #define   PROT_KEY_UNLOCK     0xFC600309
  31 #define   PROT_KEY_HARDLOCK   0xDEADDEAD /* AST2600 */
  32
  33 /* Configuration Register */
  34 #define R_CONF            (0x04 / 4)
  35
  36 /* Control/Status Register #1 (ast2500) */
  37 #define R_STATUS1         (0x60 / 4)
  38 #define   PHY_BUSY_STATE      BIT(0)
  39 #define   PHY_PLL_LOCK_STATUS BIT(4)
  40
  41 #define R_ECC_TEST_CTRL   (0x70 / 4)
  42 #define   ECC_TEST_FINISHED   BIT(12)
  43 #define   ECC_TEST_FAIL       BIT(13)
  44
  45 /*
  46  * Configuration register Ox4 (for Aspeed AST2400 SOC)
  47  *
  48  * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
  49  * what we care about right now as it is checked by U-Boot to
  50  * determine the RAM size.
  51  */
  52
  53 #define ASPEED_SDMC_RESERVED            0xFFFFF800 /* 31:11 reserved */
  54 #define ASPEED_SDMC_AST2300_COMPAT      (1 << 10)
  55 #define ASPEED_SDMC_SCRAMBLE_PATTERN    (1 << 9)
  56 #define ASPEED_SDMC_DATA_SCRAMBLE       (1 << 8)
  57 #define ASPEED_SDMC_ECC_ENABLE          (1 << 7)
  58 #define ASPEED_SDMC_VGA_COMPAT          (1 << 6) /* readonly */
  59 #define ASPEED_SDMC_DRAM_BANK           (1 << 5)
  60 #define ASPEED_SDMC_DRAM_BURST          (1 << 4)
  61 #define ASPEED_SDMC_VGA_APERTURE(x)     ((x & 0x3) << 2) /* readonly */
  62 #define     ASPEED_SDMC_VGA_8MB             0x0
  63 #define     ASPEED_SDMC_VGA_16MB            0x1
  64 #define     ASPEED_SDMC_VGA_32MB            0x2
  65 #define     ASPEED_SDMC_VGA_64MB            0x3
  66 #define ASPEED_SDMC_DRAM_SIZE(x)        (x & 0x3)
  67 #define     ASPEED_SDMC_DRAM_64MB           0x0
  68 #define     ASPEED_SDMC_DRAM_128MB          0x1
  69 #define     ASPEED_SDMC_DRAM_256MB          0x2
  70 #define     ASPEED_SDMC_DRAM_512MB          0x3
  71
  72 #define ASPEED_SDMC_READONLY_MASK                       \
  73     (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT |    \
  74      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
  75 /*
  76  * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
  77  *
  78  * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
  79  * should be set to 1 for the AST2500 SOC.
  80  */
  81 #define ASPEED_SDMC_HW_VERSION(x)       ((x & 0xf) << 28) /* readonly */
  82 #define ASPEED_SDMC_SW_VERSION          ((x & 0xff) << 20)
  83 #define ASPEED_SDMC_CACHE_INITIAL_DONE  (1 << 19)  /* readonly */
  84 #define ASPEED_SDMC_AST2500_RESERVED    0x7C000 /* 18:14 reserved */
  85 #define ASPEED_SDMC_CACHE_DDR4_CONF     (1 << 13)
  86 #define ASPEED_SDMC_CACHE_INITIAL       (1 << 12)
  87 #define ASPEED_SDMC_CACHE_RANGE_CTRL    (1 << 11)
  88 #define ASPEED_SDMC_CACHE_ENABLE        (1 << 10) /* differs from AST2400 */
  89 #define ASPEED_SDMC_DRAM_TYPE           (1 << 4)  /* differs from AST2400 */
  90
  91 /* DRAM size definitions differs */
  92 #define     ASPEED_SDMC_AST2500_128MB       0x0
  93 #define     ASPEED_SDMC_AST2500_256MB       0x1
  94 #define     ASPEED_SDMC_AST2500_512MB       0x2
  95 #define     ASPEED_SDMC_AST2500_1024MB      0x3
  96
  97 #define     ASPEED_SDMC_AST2600_256MB       0x0
  98 #define     ASPEED_SDMC_AST2600_512MB       0x1
  99 #define     ASPEED_SDMC_AST2600_1024MB      0x2
 100 #define     ASPEED_SDMC_AST2600_2048MB      0x3
 101
 102 #define ASPEED_SDMC_AST2500_READONLY_MASK                               \
 103     (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE |     \
 104      ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT |            \
 105      ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
 106
 107 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
 108 {
 109     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 110
 111     addr >>= 2;
 112
 113     if (addr >= ARRAY_SIZE(s->regs)) {
 114         qemu_log_mask(LOG_GUEST_ERROR,
 115                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 116                       __func__, addr * 4);
 117         return 0;
 118     }
 119
 120     return s->regs[addr];
 121 }
 122
 123 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
 124                              unsigned int size)
 125 {
 126     AspeedSDMCState *s = ASPEED_SDMC(opaque);
 127     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 128
 129     addr >>= 2;
 130
 131     if (addr >= ARRAY_SIZE(s->regs)) {
 132         qemu_log_mask(LOG_GUEST_ERROR,
 133                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 134                       __func__, addr);
 135         return;
 136     }
 137
 138     asc->write(s, addr, data);
 139 }
 140
 141 static const MemoryRegionOps aspeed_sdmc_ops = {
 142     .read = aspeed_sdmc_read,
 143     .write = aspeed_sdmc_write,
 144     .endianness = DEVICE_LITTLE_ENDIAN,
 145     .valid.min_access_size = 4,
 146     .valid.max_access_size = 4,
 147 };
 148
 149 static int ast2400_rambits(AspeedSDMCState *s)
 150 {
 151     switch (s->ram_size >> 20) {
 152     case 64:
 153         return ASPEED_SDMC_DRAM_64MB;
 154     case 128:
 155         return ASPEED_SDMC_DRAM_128MB;
 156     case 256:
 157         return ASPEED_SDMC_DRAM_256MB;
 158     case 512:
 159         return ASPEED_SDMC_DRAM_512MB;
 160     default:
 161         g_assert_not_reached();
 162         break;
 163     }
 164 }
 165
 166 static int ast2500_rambits(AspeedSDMCState *s)
 167 {
 168     switch (s->ram_size >> 20) {
 169     case 128:
 170         return ASPEED_SDMC_AST2500_128MB;
 171     case 256:
 172         return ASPEED_SDMC_AST2500_256MB;
 173     case 512:
 174         return ASPEED_SDMC_AST2500_512MB;
 175     case 1024:
 176         return ASPEED_SDMC_AST2500_1024MB;
 177     default:
 178         g_assert_not_reached();
 179         break;
 180     }
 181 }
 182
 183 static int ast2600_rambits(AspeedSDMCState *s)
 184 {
 185     switch (s->ram_size >> 20) {
 186     case 256:
 187         return ASPEED_SDMC_AST2600_256MB;
 188     case 512:
 189         return ASPEED_SDMC_AST2600_512MB;
 190     case 1024:
 191         return ASPEED_SDMC_AST2600_1024MB;
 192     case 2048:
 193         return ASPEED_SDMC_AST2600_2048MB;
 194     default:
 195         g_assert_not_reached();
 196         break;
 197     }
 198 }
 199
 200 static void aspeed_sdmc_reset(DeviceState *dev)
 201 {
 202     AspeedSDMCState *s = ASPEED_SDMC(dev);
 203     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 204
 205     memset(s->regs, 0, sizeof(s->regs));
 206
 207     /* Set ram size bit and defaults values */
 208     s->regs[R_CONF] = asc->compute_conf(s, 0);
 209
 210     /*
 211      * PHY status:
 212      *  - set phy status ok (set bit 1)
 213      *  - initial PVT calibration ok (clear bit 3)
 214      *  - runtime calibration ok (clear bit 5)
 215      */
 216     s->regs[0x100] = BIT(1);
 217
 218     /* PHY eye window: set all as passing */
 219     s->regs[0x100 | (0x68 / 4)] = 0xff;
 220     s->regs[0x100 | (0x7c / 4)] = 0xff;
 221     s->regs[0x100 | (0x50 / 4)] = 0xfffffff;
 222 }
 223
 224 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
 225                                      void *opaque, Error **errp)
 226 {
 227     AspeedSDMCState *s = ASPEED_SDMC(obj);
 228     int64_t value = s->ram_size;
 229
 230     visit_type_int(v, name, &value, errp);
 231 }
 232
 233 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
 234                                      void *opaque, Error **errp)
 235 {
 236     int i;
 237     char *sz;
 238     int64_t value;
 239     AspeedSDMCState *s = ASPEED_SDMC(obj);
 240     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 241
 242     if (!visit_type_int(v, name, &value, errp)) {
 243         return;
 244     }
 245
 246     for (i = 0; asc->valid_ram_sizes[i]; i++) {
 247         if (value == asc->valid_ram_sizes[i]) {
 248             s->ram_size = value;
 249             return;
 250         }
 251     }
 252
 253     sz = size_to_str(value);
 254     error_setg(errp, "Invalid RAM size %s", sz);
 255     g_free(sz);
 256 }
 257
 258 static void aspeed_sdmc_initfn(Object *obj)
 259 {
 260     object_property_add(obj, "ram-size", "int",
 261                         aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
 262                         NULL, NULL);
 263 }
 264
 265 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 266 {
 267     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 268     AspeedSDMCState *s = ASPEED_SDMC(dev);
 269     AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
 270
 271     assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */
 272     s->max_ram_size = asc->max_ram_size;
 273
 274     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
 275                           TYPE_ASPEED_SDMC, 0x1000);
 276     sysbus_init_mmio(sbd, &s->iomem);
 277 }
 278
 279 static const VMStateDescription vmstate_aspeed_sdmc = {
 280     .name = "aspeed.sdmc",
 281     .version_id = 1,
 282     .minimum_version_id = 1,
 283     .fields = (VMStateField[]) {
 284         VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
 285         VMSTATE_END_OF_LIST()
 286     }
 287 };
 288
 289 static Property aspeed_sdmc_properties[] = {
 290     DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
 291     DEFINE_PROP_END_OF_LIST(),
 292 };
 293
 294 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
 295 {
 296     DeviceClass *dc = DEVICE_CLASS(klass);
 297     dc->realize = aspeed_sdmc_realize;
 298     dc->reset = aspeed_sdmc_reset;
 299     dc->desc = "ASPEED SDRAM Memory Controller";
 300     dc->vmsd = &vmstate_aspeed_sdmc;
 301     device_class_set_props(dc, aspeed_sdmc_properties);
 302 }
 303
 304 static const TypeInfo aspeed_sdmc_info = {
 305     .name = TYPE_ASPEED_SDMC,
 306     .parent = TYPE_SYS_BUS_DEVICE,
 307     .instance_size = sizeof(AspeedSDMCState),
 308     .instance_init = aspeed_sdmc_initfn,
 309     .class_init = aspeed_sdmc_class_init,
 310     .class_size = sizeof(AspeedSDMCClass),
 311     .abstract   = true,
 312 };
 313
 314 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 315 {
 316     uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
 317         ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
 318
 319     /* Make sure readonly bits are kept */
 320     data &= ~ASPEED_SDMC_READONLY_MASK;
 321
 322     return data | fixed_conf;
 323 }
 324
 325 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 326                                    uint32_t data)
 327 {
 328     if (reg == R_PROT) {
 329         s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
 330         return;
 331     }
 332
 333     if (!s->regs[R_PROT]) {
 334         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 335         return;
 336     }
 337
 338     switch (reg) {
 339     case R_CONF:
 340         data = aspeed_2400_sdmc_compute_conf(s, data);
 341         break;
 342     default:
 343         break;
 344     }
 345
 346     s->regs[reg] = data;
 347 }
 348
 349 static const uint64_t
 350 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
 351
 352 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
 353 {
 354     DeviceClass *dc = DEVICE_CLASS(klass);
 355     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 356
 357     dc->desc = "ASPEED 2400 SDRAM Memory Controller";
 358     asc->max_ram_size = 512 * MiB;
 359     asc->compute_conf = aspeed_2400_sdmc_compute_conf;
 360     asc->write = aspeed_2400_sdmc_write;
 361     asc->valid_ram_sizes = aspeed_2400_ram_sizes;
 362 }
 363
 364 static const TypeInfo aspeed_2400_sdmc_info = {
 365     .name = TYPE_ASPEED_2400_SDMC,
 366     .parent = TYPE_ASPEED_SDMC,
 367     .class_init = aspeed_2400_sdmc_class_init,
 368 };
 369
 370 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 371 {
 372     uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
 373         ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 374         ASPEED_SDMC_CACHE_INITIAL_DONE |
 375         ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
 376
 377     /* Make sure readonly bits are kept */
 378     data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 379
 380     return data | fixed_conf;
 381 }
 382
 383 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 384                                    uint32_t data)
 385 {
 386     if (reg == R_PROT) {
 387         s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
 388         return;
 389     }
 390
 391     if (!s->regs[R_PROT]) {
 392         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
 393         return;
 394     }
 395
 396     switch (reg) {
 397     case R_CONF:
 398         data = aspeed_2500_sdmc_compute_conf(s, data);
 399         break;
 400     case R_STATUS1:
 401         /* Will never return 'busy' */
 402         data &= ~PHY_BUSY_STATE;
 403         break;
 404     case R_ECC_TEST_CTRL:
 405         /* Always done, always happy */
 406         data |= ECC_TEST_FINISHED;
 407         data &= ~ECC_TEST_FAIL;
 408         break;
 409     default:
 410         break;
 411     }
 412
 413     s->regs[reg] = data;
 414 }
 415
 416 static const uint64_t
 417 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
 418
 419 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
 420 {
 421     DeviceClass *dc = DEVICE_CLASS(klass);
 422     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 423
 424     dc->desc = "ASPEED 2500 SDRAM Memory Controller";
 425     asc->max_ram_size = 1 * GiB;
 426     asc->compute_conf = aspeed_2500_sdmc_compute_conf;
 427     asc->write = aspeed_2500_sdmc_write;
 428     asc->valid_ram_sizes = aspeed_2500_ram_sizes;
 429 }
 430
 431 static const TypeInfo aspeed_2500_sdmc_info = {
 432     .name = TYPE_ASPEED_2500_SDMC,
 433     .parent = TYPE_ASPEED_SDMC,
 434     .class_init = aspeed_2500_sdmc_class_init,
 435 };
 436
 437 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
 438 {
 439     uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
 440         ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
 441         ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));
 442
 443     /* Make sure readonly bits are kept (use ast2500 mask) */
 444     data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
 445
 446     return data | fixed_conf;
 447 }
 448
 449 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
 450                                    uint32_t data)
 451 {
 452     if (s->regs[R_PROT] == PROT_HARDLOCKED) {
 453         qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
 454                 __func__);
 455         return;
 456     }
 457
 458     if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
 459         qemu_log_mask(LOG_GUEST_ERROR,
 460                       "%s: SDMC is locked! (write to MCR%02x blocked)\n",
 461                       __func__, reg * 4);
 462         return;
 463     }
 464
 465     switch (reg) {
 466     case R_PROT:
 467         if (data == PROT_KEY_UNLOCK)  {
 468             data = PROT_UNLOCKED;
 469         } else if (data == PROT_KEY_HARDLOCK) {
 470             data = PROT_HARDLOCKED;
 471         } else {
 472             data = PROT_SOFTLOCKED;
 473         }
 474         break;
 475     case R_CONF:
 476         data = aspeed_2600_sdmc_compute_conf(s, data);
 477         break;
 478     case R_STATUS1:
 479         /* Will never return 'busy'. 'lock status' is always set */
 480         data &= ~PHY_BUSY_STATE;
 481         data |= PHY_PLL_LOCK_STATUS;
 482         break;
 483     case R_ECC_TEST_CTRL:
 484         /* Always done, always happy */
 485         data |= ECC_TEST_FINISHED;
 486         data &= ~ECC_TEST_FAIL;
 487         break;
 488     default:
 489         break;
 490     }
 491
 492     s->regs[reg] = data;
 493 }
 494
 495 static const uint64_t
 496 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
 497
 498 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
 499 {
 500     DeviceClass *dc = DEVICE_CLASS(klass);
 501     AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
 502
 503     dc->desc = "ASPEED 2600 SDRAM Memory Controller";
 504     asc->max_ram_size = 2 * GiB;
 505     asc->compute_conf = aspeed_2600_sdmc_compute_conf;
 506     asc->write = aspeed_2600_sdmc_write;
 507     asc->valid_ram_sizes = aspeed_2600_ram_sizes;
 508 }
 509
 510 static const TypeInfo aspeed_2600_sdmc_info = {
 511     .name = TYPE_ASPEED_2600_SDMC,
 512     .parent = TYPE_ASPEED_SDMC,
 513     .class_init = aspeed_2600_sdmc_class_init,
 514 };
 515
 516 static void aspeed_sdmc_register_types(void)
 517 {
 518     type_register_static(&aspeed_sdmc_info);
 519     type_register_static(&aspeed_2400_sdmc_info);
 520     type_register_static(&aspeed_2500_sdmc_info);
 521     type_register_static(&aspeed_2600_sdmc_info);
 522 }
 523
 524 type_init(aspeed_sdmc_register_types);