| commit | 14c179541bbf083f4b215ddb389828ad8b9d0b28 | |
| author | Joel Stanley <joel@jms.id.au> | |
| Tue, 1 Sep 2020 12:21:51 +0000 (1 14:21 +0200) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Tue, 1 Sep 2020 12:21:51 +0000 (1 14:21 +0200) | ||
| tree | c620b503af9345237463bd9f3e7adc5ffe30c634 | treesnapshot (tar.gz zip) |
| parent | e0059c8883944605d1f5c4dc9c60a881c4b3be39 | commitdiff |
aspeed/sdmc: Perform memory training
This allows qemu to run the "normal" power on reset boot path through
u-boot, where the DDR is trained.
An enhancement would be to have the SCU bit stick across qemu reboots,
but be unset on initial boot.
Proper modelling would be to discard all writes to the phy setting regs
at offset 0x100 - 0x400 and to model the phy status regs at offset
0x400.
The status regs model would only need to account for offets 0x00,
0x50, 0x68 and 0x7c.
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: checkpatch fixes ]
Message-Id: <20200819100956.2216690-17-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This allows qemu to run the "normal" power on reset boot path through
u-boot, where the DDR is trained.
An enhancement would be to have the SCU bit stick across qemu reboots,
but be unset on initial boot.
Proper modelling would be to discard all writes to the phy setting regs
at offset 0x100 - 0x400 and to model the phy status regs at offset
0x400.
The status regs model would only need to account for offets 0x00,
0x50, 0x68 and 0x7c.
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: checkpatch fixes ]
Message-Id: <20200819100956.2216690-17-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| hw/misc/aspeed_scu.c | diffblobblamehistory | |
| hw/misc/aspeed_sdmc.c | diffblobblamehistory | |
| include/hw/misc/aspeed_sdmc.h | diffblobblamehistory |