hw/arm/allwinner-a10.c

   1 /*
   2  * Allwinner A10 SoC emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "hw/char/serial.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/allwinner-a10.h"
  24 #include "hw/misc/unimp.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "hw/usb/hcd-ohci.h"
  28 #include "hw/loader.h"
  29
  30 #define AW_A10_SRAM_A_BASE      0x00000000
  31 #define AW_A10_DRAMC_BASE       0x01c01000
  32 #define AW_A10_MMC0_BASE        0x01c0f000
  33 #define AW_A10_CCM_BASE         0x01c20000
  34 #define AW_A10_PIC_REG_BASE     0x01c20400
  35 #define AW_A10_PIT_REG_BASE     0x01c20c00
  36 #define AW_A10_UART0_REG_BASE   0x01c28000
  37 #define AW_A10_EMAC_BASE        0x01c0b000
  38 #define AW_A10_EHCI_BASE        0x01c14000
  39 #define AW_A10_OHCI_BASE        0x01c14400
  40 #define AW_A10_SATA_BASE        0x01c18000
  41 #define AW_A10_RTC_BASE         0x01c20d00
  42 #define AW_A10_I2C0_BASE        0x01c2ac00
  43
  44 void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
  45 {
  46     const int64_t rom_size = 32 * KiB;
  47     g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
  48
  49     if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
  50         error_setg(&error_fatal, "%s: failed to read BlockBackend data",
  51                    __func__);
  52         return;
  53     }
  54
  55     rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
  56                   rom_size, AW_A10_SRAM_A_BASE,
  57                   NULL, NULL, NULL, NULL, false);
  58 }
  59
  60 static void aw_a10_init(Object *obj)
  61 {
  62     AwA10State *s = AW_A10(obj);
  63
  64     object_initialize_child(obj, "cpu", &s->cpu,
  65                             ARM_CPU_TYPE_NAME("cortex-a8"));
  66
  67     object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
  68
  69     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
  70
  71     object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
  72
  73     object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
  74
  75     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
  76
  77     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
  78
  79     object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
  80
  81     if (machine_usb(current_machine)) {
  82         int i;
  83
  84         for (i = 0; i < AW_A10_NUM_USB; i++) {
  85             object_initialize_child(obj, "ehci[*]", &s->ehci[i],
  86                                     TYPE_PLATFORM_EHCI);
  87             object_initialize_child(obj, "ohci[*]", &s->ohci[i],
  88                                     TYPE_SYSBUS_OHCI);
  89         }
  90     }
  91
  92     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
  93
  94     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
  95 }
  96
  97 static void aw_a10_realize(DeviceState *dev, Error **errp)
  98 {
  99     AwA10State *s = AW_A10(dev);
 100     SysBusDevice *sysbusdev;
 101
 102     if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
 103         return;
 104     }
 105
 106     if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) {
 107         return;
 108     }
 109     sysbusdev = SYS_BUS_DEVICE(&s->intc);
 110     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
 111     sysbus_connect_irq(sysbusdev, 0,
 112                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 113     sysbus_connect_irq(sysbusdev, 1,
 114                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 115     qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
 116
 117     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
 118         return;
 119     }
 120     sysbusdev = SYS_BUS_DEVICE(&s->timer);
 121     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
 122     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
 123     sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
 124     sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
 125     sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
 126     sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
 127     sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
 128
 129     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
 130                            &error_fatal);
 131     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
 132     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
 133
 134     /* Clock Control Module */
 135     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
 136     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
 137
 138     /* DRAM Control Module */
 139     sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
 140     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
 141
 142     /* FIXME use qdev NIC properties instead of nd_table[] */
 143     if (nd_table[0].used) {
 144         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
 145         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
 146     }
 147     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
 148         return;
 149     }
 150     sysbusdev = SYS_BUS_DEVICE(&s->emac);
 151     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
 152     sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
 153
 154     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
 155         return;
 156     }
 157     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
 158     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
 159
 160     /* FIXME use a qdev chardev prop instead of serial_hd() */
 161     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
 162                    qdev_get_gpio_in(dev, 1),
 163                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 164
 165     if (machine_usb(current_machine)) {
 166         int i;
 167
 168         for (i = 0; i < AW_A10_NUM_USB; i++) {
 169             g_autofree char *bus = g_strdup_printf("usb-bus.%d", i);
 170
 171             object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
 172                                      true, &error_fatal);
 173             sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
 174             sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 175                             AW_A10_EHCI_BASE + i * 0x8000);
 176             sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 177                                qdev_get_gpio_in(dev, 39 + i));
 178
 179             object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
 180                                     &error_fatal);
 181             sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
 182             sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
 183                             AW_A10_OHCI_BASE + i * 0x8000);
 184             sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
 185                                qdev_get_gpio_in(dev, 64 + i));
 186         }
 187     }
 188
 189     /* SD/MMC */
 190     object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
 191                              OBJECT(get_system_memory()), &error_fatal);
 192     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
 193     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
 194     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
 195     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
 196                               "sd-bus");
 197
 198     /* RTC */
 199     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
 200     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
 201
 202     /* I2C */
 203     sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
 204     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
 205     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
 206 }
 207
 208 static void aw_a10_class_init(ObjectClass *oc, void *data)
 209 {
 210     DeviceClass *dc = DEVICE_CLASS(oc);
 211
 212     dc->realize = aw_a10_realize;
 213     /* Reason: Uses serial_hds and nd_table in realize function */
 214     dc->user_creatable = false;
 215 }
 216
 217 static const TypeInfo aw_a10_type_info = {
 218     .name = TYPE_AW_A10,
 219     .parent = TYPE_DEVICE,
 220     .instance_size = sizeof(AwA10State),
 221     .instance_init = aw_a10_init,
 222     .class_init = aw_a10_class_init,
 223 };
 224
 225 static void aw_a10_register_types(void)
 226 {
 227     type_register_static(&aw_a10_type_info);
 228 }
 229
 230 type_init(aw_a10_register_types)