target-arm/helper-a64.c

   1 /*
   2  *  AArch64 specific helpers
   3  *
   4  *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23 #include "exec/helper-proto.h"
  24 #include "qemu/host-utils.h"
  25 #include "qemu/log.h"
  26 #include "sysemu/sysemu.h"
  27 #include "qemu/bitops.h"
  28 #include "internals.h"
  29 #include "qemu/crc32c.h"
  30 #include "exec/exec-all.h"
  31 #include "exec/cpu_ldst.h"
  32 #include "qemu/int128.h"
  33 #include "tcg.h"
  34 #include <zlib.h> /* For crc32 */
  35
  36 /* C2.4.7 Multiply and divide */
  37 /* special cases for 0 and LLONG_MIN are mandated by the standard */
  38 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
  39 {
  40     if (den == 0) {
  41         return 0;
  42     }
  43     return num / den;
  44 }
  45
  46 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
  47 {
  48     if (den == 0) {
  49         return 0;
  50     }
  51     if (num == LLONG_MIN && den == -1) {
  52         return LLONG_MIN;
  53     }
  54     return num / den;
  55 }
  56
  57 uint64_t HELPER(clz64)(uint64_t x)
  58 {
  59     return clz64(x);
  60 }
  61
  62 uint64_t HELPER(cls64)(uint64_t x)
  63 {
  64     return clrsb64(x);
  65 }
  66
  67 uint32_t HELPER(cls32)(uint32_t x)
  68 {
  69     return clrsb32(x);
  70 }
  71
  72 uint32_t HELPER(clz32)(uint32_t x)
  73 {
  74     return clz32(x);
  75 }
  76
  77 uint64_t HELPER(rbit64)(uint64_t x)
  78 {
  79     return revbit64(x);
  80 }
  81
  82 /* Convert a softfloat float_relation_ (as returned by
  83  * the float*_compare functions) to the correct ARM
  84  * NZCV flag state.
  85  */
  86 static inline uint32_t float_rel_to_flags(int res)
  87 {
  88     uint64_t flags;
  89     switch (res) {
  90     case float_relation_equal:
  91         flags = PSTATE_Z | PSTATE_C;
  92         break;
  93     case float_relation_less:
  94         flags = PSTATE_N;
  95         break;
  96     case float_relation_greater:
  97         flags = PSTATE_C;
  98         break;
  99     case float_relation_unordered:
 100     default:
 101         flags = PSTATE_C | PSTATE_V;
 102         break;
 103     }
 104     return flags;
 105 }
 106
 107 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
 108 {
 109     return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
 110 }
 111
 112 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
 113 {
 114     return float_rel_to_flags(float32_compare(x, y, fp_status));
 115 }
 116
 117 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
 118 {
 119     return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
 120 }
 121
 122 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
 123 {
 124     return float_rel_to_flags(float64_compare(x, y, fp_status));
 125 }
 126
 127 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
 128 {
 129     float_status *fpst = fpstp;
 130
 131     a = float32_squash_input_denormal(a, fpst);
 132     b = float32_squash_input_denormal(b, fpst);
 133
 134     if ((float32_is_zero(a) && float32_is_infinity(b)) ||
 135         (float32_is_infinity(a) && float32_is_zero(b))) {
 136         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 137         return make_float32((1U << 30) |
 138                             ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
 139     }
 140     return float32_mul(a, b, fpst);
 141 }
 142
 143 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
 144 {
 145     float_status *fpst = fpstp;
 146
 147     a = float64_squash_input_denormal(a, fpst);
 148     b = float64_squash_input_denormal(b, fpst);
 149
 150     if ((float64_is_zero(a) && float64_is_infinity(b)) ||
 151         (float64_is_infinity(a) && float64_is_zero(b))) {
 152         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 153         return make_float64((1ULL << 62) |
 154                             ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
 155     }
 156     return float64_mul(a, b, fpst);
 157 }
 158
 159 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
 160                           uint32_t rn, uint32_t numregs)
 161 {
 162     /* Helper function for SIMD TBL and TBX. We have to do the table
 163      * lookup part for the 64 bits worth of indices we're passed in.
 164      * result is the initial results vector (either zeroes for TBL
 165      * or some guest values for TBX), rn the register number where
 166      * the table starts, and numregs the number of registers in the table.
 167      * We return the results of the lookups.
 168      */
 169     int shift;
 170
 171     for (shift = 0; shift < 64; shift += 8) {
 172         int index = extract64(indices, shift, 8);
 173         if (index < 16 * numregs) {
 174             /* Convert index (a byte offset into the virtual table
 175              * which is a series of 128-bit vectors concatenated)
 176              * into the correct vfp.regs[] element plus a bit offset
 177              * into that element, bearing in mind that the table
 178              * can wrap around from V31 to V0.
 179              */
 180             int elt = (rn * 2 + (index >> 3)) % 64;
 181             int bitidx = (index & 7) * 8;
 182             uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
 183
 184             result = deposit64(result, shift, 8, val);
 185         }
 186     }
 187     return result;
 188 }
 189
 190 /* 64bit/double versions of the neon float compare functions */
 191 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
 192 {
 193     float_status *fpst = fpstp;
 194     return -float64_eq_quiet(a, b, fpst);
 195 }
 196
 197 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
 198 {
 199     float_status *fpst = fpstp;
 200     return -float64_le(b, a, fpst);
 201 }
 202
 203 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 204 {
 205     float_status *fpst = fpstp;
 206     return -float64_lt(b, a, fpst);
 207 }
 208
 209 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
 210  * versions, these do a fully fused multiply-add or
 211  * multiply-add-and-halve.
 212  */
 213 #define float32_two make_float32(0x40000000)
 214 #define float32_three make_float32(0x40400000)
 215 #define float32_one_point_five make_float32(0x3fc00000)
 216
 217 #define float64_two make_float64(0x4000000000000000ULL)
 218 #define float64_three make_float64(0x4008000000000000ULL)
 219 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 220
 221 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 222 {
 223     float_status *fpst = fpstp;
 224
 225     a = float32_squash_input_denormal(a, fpst);
 226     b = float32_squash_input_denormal(b, fpst);
 227
 228     a = float32_chs(a);
 229     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 230         (float32_is_infinity(b) && float32_is_zero(a))) {
 231         return float32_two;
 232     }
 233     return float32_muladd(a, b, float32_two, 0, fpst);
 234 }
 235
 236 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
 237 {
 238     float_status *fpst = fpstp;
 239
 240     a = float64_squash_input_denormal(a, fpst);
 241     b = float64_squash_input_denormal(b, fpst);
 242
 243     a = float64_chs(a);
 244     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 245         (float64_is_infinity(b) && float64_is_zero(a))) {
 246         return float64_two;
 247     }
 248     return float64_muladd(a, b, float64_two, 0, fpst);
 249 }
 250
 251 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 252 {
 253     float_status *fpst = fpstp;
 254
 255     a = float32_squash_input_denormal(a, fpst);
 256     b = float32_squash_input_denormal(b, fpst);
 257
 258     a = float32_chs(a);
 259     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 260         (float32_is_infinity(b) && float32_is_zero(a))) {
 261         return float32_one_point_five;
 262     }
 263     return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
 264 }
 265
 266 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
 267 {
 268     float_status *fpst = fpstp;
 269
 270     a = float64_squash_input_denormal(a, fpst);
 271     b = float64_squash_input_denormal(b, fpst);
 272
 273     a = float64_chs(a);
 274     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 275         (float64_is_infinity(b) && float64_is_zero(a))) {
 276         return float64_one_point_five;
 277     }
 278     return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
 279 }
 280
 281 /* Pairwise long add: add pairs of adjacent elements into
 282  * double-width elements in the result (eg _s8 is an 8x8->16 op)
 283  */
 284 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
 285 {
 286     uint64_t nsignmask = 0x0080008000800080ULL;
 287     uint64_t wsignmask = 0x8000800080008000ULL;
 288     uint64_t elementmask = 0x00ff00ff00ff00ffULL;
 289     uint64_t tmp1, tmp2;
 290     uint64_t res, signres;
 291
 292     /* Extract odd elements, sign extend each to a 16 bit field */
 293     tmp1 = a & elementmask;
 294     tmp1 ^= nsignmask;
 295     tmp1 |= wsignmask;
 296     tmp1 = (tmp1 - nsignmask) ^ wsignmask;
 297     /* Ditto for the even elements */
 298     tmp2 = (a >> 8) & elementmask;
 299     tmp2 ^= nsignmask;
 300     tmp2 |= wsignmask;
 301     tmp2 = (tmp2 - nsignmask) ^ wsignmask;
 302
 303     /* calculate the result by summing bits 0..14, 16..22, etc,
 304      * and then adjusting the sign bits 15, 23, etc manually.
 305      * This ensures the addition can't overflow the 16 bit field.
 306      */
 307     signres = (tmp1 ^ tmp2) & wsignmask;
 308     res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
 309     res ^= signres;
 310
 311     return res;
 312 }
 313
 314 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
 315 {
 316     uint64_t tmp;
 317
 318     tmp = a & 0x00ff00ff00ff00ffULL;
 319     tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
 320     return tmp;
 321 }
 322
 323 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
 324 {
 325     int32_t reslo, reshi;
 326
 327     reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
 328     reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
 329
 330     return (uint32_t)reslo | (((uint64_t)reshi) << 32);
 331 }
 332
 333 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 334 {
 335     uint64_t tmp;
 336
 337     tmp = a & 0x0000ffff0000ffffULL;
 338     tmp += (a >> 16) & 0x0000ffff0000ffffULL;
 339     return tmp;
 340 }
 341
 342 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
 343 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
 344 {
 345     float_status *fpst = fpstp;
 346     uint32_t val32, sbit;
 347     int32_t exp;
 348
 349     if (float32_is_any_nan(a)) {
 350         float32 nan = a;
 351         if (float32_is_signaling_nan(a, fpst)) {
 352             float_raise(float_flag_invalid, fpst);
 353             nan = float32_maybe_silence_nan(a, fpst);
 354         }
 355         if (fpst->default_nan_mode) {
 356             nan = float32_default_nan(fpst);
 357         }
 358         return nan;
 359     }
 360
 361     val32 = float32_val(a);
 362     sbit = 0x80000000ULL & val32;
 363     exp = extract32(val32, 23, 8);
 364
 365     if (exp == 0) {
 366         return make_float32(sbit | (0xfe << 23));
 367     } else {
 368         return make_float32(sbit | (~exp & 0xff) << 23);
 369     }
 370 }
 371
 372 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
 373 {
 374     float_status *fpst = fpstp;
 375     uint64_t val64, sbit;
 376     int64_t exp;
 377
 378     if (float64_is_any_nan(a)) {
 379         float64 nan = a;
 380         if (float64_is_signaling_nan(a, fpst)) {
 381             float_raise(float_flag_invalid, fpst);
 382             nan = float64_maybe_silence_nan(a, fpst);
 383         }
 384         if (fpst->default_nan_mode) {
 385             nan = float64_default_nan(fpst);
 386         }
 387         return nan;
 388     }
 389
 390     val64 = float64_val(a);
 391     sbit = 0x8000000000000000ULL & val64;
 392     exp = extract64(float64_val(a), 52, 11);
 393
 394     if (exp == 0) {
 395         return make_float64(sbit | (0x7feULL << 52));
 396     } else {
 397         return make_float64(sbit | (~exp & 0x7ffULL) << 52);
 398     }
 399 }
 400
 401 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
 402 {
 403     /* Von Neumann rounding is implemented by using round-to-zero
 404      * and then setting the LSB of the result if Inexact was raised.
 405      */
 406     float32 r;
 407     float_status *fpst = &env->vfp.fp_status;
 408     float_status tstat = *fpst;
 409     int exflags;
 410
 411     set_float_rounding_mode(float_round_to_zero, &tstat);
 412     set_float_exception_flags(0, &tstat);
 413     r = float64_to_float32(a, &tstat);
 414     r = float32_maybe_silence_nan(r, &tstat);
 415     exflags = get_float_exception_flags(&tstat);
 416     if (exflags & float_flag_inexact) {
 417         r = make_float32(float32_val(r) | 1);
 418     }
 419     exflags |= get_float_exception_flags(fpst);
 420     set_float_exception_flags(exflags, fpst);
 421     return r;
 422 }
 423
 424 /* 64-bit versions of the CRC helpers. Note that although the operation
 425  * (and the prototypes of crc32c() and crc32() mean that only the bottom
 426  * 32 bits of the accumulator and result are used, we pass and return
 427  * uint64_t for convenience of the generated code. Unlike the 32-bit
 428  * instruction set versions, val may genuinely have 64 bits of data in it.
 429  * The upper bytes of val (above the number specified by 'bytes') must have
 430  * been zeroed out by the caller.
 431  */
 432 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
 433 {
 434     uint8_t buf[8];
 435
 436     stq_le_p(buf, val);
 437
 438     /* zlib crc32 converts the accumulator and output to one's complement.  */
 439     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
 440 }
 441
 442 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
 443 {
 444     uint8_t buf[8];
 445
 446     stq_le_p(buf, val);
 447
 448     /* Linux crc32c converts the output to one's complement.  */
 449     return crc32c(acc, buf, bytes) ^ 0xffffffff;
 450 }
 451
 452 /* Returns 0 on success; 1 otherwise.  */
 453 uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
 454                                      uint64_t new_lo, uint64_t new_hi)
 455 {
 456     uintptr_t ra = GETPC();
 457     Int128 oldv, cmpv, newv;
 458     bool success;
 459
 460     cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
 461     newv = int128_make128(new_lo, new_hi);
 462
 463     if (parallel_cpus) {
 464 #ifndef CONFIG_ATOMIC128
 465         cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
 466 #else
 467         int mem_idx = cpu_mmu_index(env, false);
 468         TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
 469         oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
 470         success = int128_eq(oldv, cmpv);
 471 #endif
 472     } else {
 473         uint64_t o0, o1;
 474
 475 #ifdef CONFIG_USER_ONLY
 476         /* ??? Enforce alignment.  */
 477         uint64_t *haddr = g2h(addr);
 478         o0 = ldq_le_p(haddr + 0);
 479         o1 = ldq_le_p(haddr + 1);
 480         oldv = int128_make128(o0, o1);
 481
 482         success = int128_eq(oldv, cmpv);
 483         if (success) {
 484             stq_le_p(haddr + 0, int128_getlo(newv));
 485             stq_le_p(haddr + 1, int128_gethi(newv));
 486         }
 487 #else
 488         int mem_idx = cpu_mmu_index(env, false);
 489         TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
 490         TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
 491
 492         o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
 493         o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
 494         oldv = int128_make128(o0, o1);
 495
 496         success = int128_eq(oldv, cmpv);
 497         if (success) {
 498             helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
 499             helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
 500         }
 501 #endif
 502     }
 503
 504     return !success;
 505 }
 506
 507 uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
 508                                      uint64_t new_lo, uint64_t new_hi)
 509 {
 510     uintptr_t ra = GETPC();
 511     Int128 oldv, cmpv, newv;
 512     bool success;
 513
 514     cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
 515     newv = int128_make128(new_lo, new_hi);
 516
 517     if (parallel_cpus) {
 518 #ifndef CONFIG_ATOMIC128
 519         cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
 520 #else
 521         int mem_idx = cpu_mmu_index(env, false);
 522         TCGMemOpIdx oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
 523         oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
 524         success = int128_eq(oldv, cmpv);
 525 #endif
 526     } else {
 527         uint64_t o0, o1;
 528
 529 #ifdef CONFIG_USER_ONLY
 530         /* ??? Enforce alignment.  */
 531         uint64_t *haddr = g2h(addr);
 532         o1 = ldq_be_p(haddr + 0);
 533         o0 = ldq_be_p(haddr + 1);
 534         oldv = int128_make128(o0, o1);
 535
 536         success = int128_eq(oldv, cmpv);
 537         if (success) {
 538             stq_be_p(haddr + 0, int128_gethi(newv));
 539             stq_be_p(haddr + 1, int128_getlo(newv));
 540         }
 541 #else
 542         int mem_idx = cpu_mmu_index(env, false);
 543         TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
 544         TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
 545
 546         o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
 547         o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
 548         oldv = int128_make128(o0, o1);
 549
 550         success = int128_eq(oldv, cmpv);
 551         if (success) {
 552             helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
 553             helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
 554         }
 555 #endif
 556     }
 557
 558     return !success;
 559 }