?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
iscsi: Switch cluster_sectors to byte-based
[qemu/ericb.git] / memory.c
blob6515131ac241f9973d99193faa540522ab5e6ae1
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "exec/ioport.h"
23 #include "qapi/visitor.h"
24 #include "qemu/bitops.h"
25 #include "qemu/error-report.h"
26 #include "qom/object.h"
27 #include "trace-root.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/misc/mmio_interface.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
36
37 //#define DEBUG_UNASSIGNED
38
39 static unsigned memory_region_transaction_depth;
40 static bool memory_region_update_pending;
41 static bool ioeventfd_update_pending;
42 static bool global_dirty_log = false;
43
44 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
46
47 static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
50 static GHashTable *flat_views;
51
52 typedef struct AddrRange AddrRange;
53
54 /*
55 * Note that signed integers are needed for negative offsetting in aliases
56 * (large MemoryRegion::alias_offset).
57 */
58 struct AddrRange {
59 Int128 start;
60 Int128 size;
61 };
62
63 static AddrRange addrrange_make(Int128 start, Int128 size)
64 {
65 return (AddrRange) { start, size };
66 }
67
68 static bool addrrange_equal(AddrRange r1, AddrRange r2)
69 {
70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
71 }
72
73 static Int128 addrrange_end(AddrRange r)
74 {
75 return int128_add(r.start, r.size);
76 }
77
78 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
79 {
80 int128_addto(&range.start, delta);
81 return range;
82 }
83
84 static bool addrrange_contains(AddrRange range, Int128 addr)
85 {
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88 }
89
90 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91 {
92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
94 }
95
96 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97 {
98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
101 }
102
103 enum ListenerDirection { Forward, Reverse };
104
105 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
130 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
131 do { \
132 MemoryListener *_listener; \
133 struct memory_listeners_as *list = &(_as)->listeners; \
134 \
135 switch (_direction) { \
136 case Forward: \
137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
156 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
157 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
158 do { \
159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
162 } while(0)
163
164 struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167 };
168
169 struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
173 EventNotifier *e;
174 };
175
176 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178 {
179 if (int128_lt(a.addr.start, b.addr.start)) {
180 return true;
181 } else if (int128_gt(a.addr.start, b.addr.start)) {
182 return false;
183 } else if (int128_lt(a.addr.size, b.addr.size)) {
184 return true;
185 } else if (int128_gt(a.addr.size, b.addr.size)) {
186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
198 if (a.e < b.e) {
199 return true;
200 } else if (a.e > b.e) {
201 return false;
202 }
203 return false;
204 }
205
206 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208 {
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211 }
212
213 typedef struct FlatRange FlatRange;
214
215 /* Range of memory in the global map. Addresses are absolute. */
216 struct FlatRange {
217 MemoryRegion *mr;
218 hwaddr offset_in_region;
219 AddrRange addr;
220 uint8_t dirty_log_mask;
221 bool romd_mode;
222 bool readonly;
223 };
224
225 /* Flattened global view of current active memory hierarchy. Kept in sorted
226 * order.
227 */
228 struct FlatView {
229 struct rcu_head rcu;
230 unsigned ref;
231 FlatRange *ranges;
232 unsigned nr;
233 unsigned nr_allocated;
234 struct AddressSpaceDispatch *dispatch;
235 MemoryRegion *root;
236 };
237
238 typedef struct AddressSpaceOps AddressSpaceOps;
239
240 #define FOR_EACH_FLAT_RANGE(var, view) \
241 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
242
243 static inline MemoryRegionSection
244 section_from_flat_range(FlatRange *fr, FlatView *fv)
245 {
246 return (MemoryRegionSection) {
247 .mr = fr->mr,
248 .fv = fv,
249 .offset_within_region = fr->offset_in_region,
250 .size = fr->addr.size,
251 .offset_within_address_space = int128_get64(fr->addr.start),
252 .readonly = fr->readonly,
253 };
254 }
255
256 static bool flatrange_equal(FlatRange *a, FlatRange *b)
257 {
258 return a->mr == b->mr
259 && addrrange_equal(a->addr, b->addr)
260 && a->offset_in_region == b->offset_in_region
261 && a->romd_mode == b->romd_mode
262 && a->readonly == b->readonly;
263 }
264
265 static FlatView *flatview_new(MemoryRegion *mr_root)
266 {
267 FlatView *view;
268
269 view = g_new0(FlatView, 1);
270 view->ref = 1;
271 view->root = mr_root;
272 memory_region_ref(mr_root);
273 trace_flatview_new(view, mr_root);
274
275 return view;
276 }
277
278 /* Insert a range into a given position. Caller is responsible for maintaining
279 * sorting order.
280 */
281 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
282 {
283 if (view->nr == view->nr_allocated) {
284 view->nr_allocated = MAX(2 * view->nr, 10);
285 view->ranges = g_realloc(view->ranges,
286 view->nr_allocated * sizeof(*view->ranges));
287 }
288 memmove(view->ranges + pos + 1, view->ranges + pos,
289 (view->nr - pos) * sizeof(FlatRange));
290 view->ranges[pos] = *range;
291 memory_region_ref(range->mr);
292 ++view->nr;
293 }
294
295 static void flatview_destroy(FlatView *view)
296 {
297 int i;
298
299 trace_flatview_destroy(view, view->root);
300 if (view->dispatch) {
301 address_space_dispatch_free(view->dispatch);
302 }
303 for (i = 0; i < view->nr; i++) {
304 memory_region_unref(view->ranges[i].mr);
305 }
306 g_free(view->ranges);
307 memory_region_unref(view->root);
308 g_free(view);
309 }
310
311 static bool flatview_ref(FlatView *view)
312 {
313 return atomic_fetch_inc_nonzero(&view->ref) > 0;
314 }
315
316 static void flatview_unref(FlatView *view)
317 {
318 if (atomic_fetch_dec(&view->ref) == 1) {
319 trace_flatview_destroy_rcu(view, view->root);
320 assert(view->root);
321 call_rcu(view, flatview_destroy, rcu);
322 }
323 }
324
325 FlatView *address_space_to_flatview(AddressSpace *as)
326 {
327 return atomic_rcu_read(&as->current_map);
328 }
329
330 AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
331 {
332 return fv->dispatch;
333 }
334
335 AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as)
336 {
337 return flatview_to_dispatch(address_space_to_flatview(as));
338 }
339
340 static bool can_merge(FlatRange *r1, FlatRange *r2)
341 {
342 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
343 && r1->mr == r2->mr
344 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
345 r1->addr.size),
346 int128_make64(r2->offset_in_region))
347 && r1->dirty_log_mask == r2->dirty_log_mask
348 && r1->romd_mode == r2->romd_mode
349 && r1->readonly == r2->readonly;
350 }
351
352 /* Attempt to simplify a view by merging adjacent ranges */
353 static void flatview_simplify(FlatView *view)
354 {
355 unsigned i, j;
356
357 i = 0;
358 while (i < view->nr) {
359 j = i + 1;
360 while (j < view->nr
361 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
362 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
363 ++j;
364 }
365 ++i;
366 memmove(&view->ranges[i], &view->ranges[j],
367 (view->nr - j) * sizeof(view->ranges[j]));
368 view->nr -= j - i;
369 }
370 }
371
372 static bool memory_region_big_endian(MemoryRegion *mr)
373 {
374 #ifdef TARGET_WORDS_BIGENDIAN
375 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
376 #else
377 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
378 #endif
379 }
380
381 static bool memory_region_wrong_endianness(MemoryRegion *mr)
382 {
383 #ifdef TARGET_WORDS_BIGENDIAN
384 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
385 #else
386 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
387 #endif
388 }
389
390 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
391 {
392 if (memory_region_wrong_endianness(mr)) {
393 switch (size) {
394 case 1:
395 break;
396 case 2:
397 *data = bswap16(*data);
398 break;
399 case 4:
400 *data = bswap32(*data);
401 break;
402 case 8:
403 *data = bswap64(*data);
404 break;
405 default:
406 abort();
407 }
408 }
409 }
410
411 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
412 {
413 MemoryRegion *root;
414 hwaddr abs_addr = offset;
415
416 abs_addr += mr->addr;
417 for (root = mr; root->container; ) {
418 root = root->container;
419 abs_addr += root->addr;
420 }
421
422 return abs_addr;
423 }
424
425 static int get_cpu_index(void)
426 {
427 if (current_cpu) {
428 return current_cpu->cpu_index;
429 }
430 return -1;
431 }
432
433 static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
434 hwaddr addr,
435 uint64_t *value,
436 unsigned size,
437 unsigned shift,
438 uint64_t mask,
439 MemTxAttrs attrs)
440 {
441 uint64_t tmp;
442
443 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
444 if (mr->subpage) {
445 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
446 } else if (mr == &io_mem_notdirty) {
447 /* Accesses to code which has previously been translated into a TB show
448 * up in the MMIO path, as accesses to the io_mem_notdirty
449 * MemoryRegion. */
450 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
451 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
452 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
453 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
454 }
455 *value |= (tmp & mask) << shift;
456 return MEMTX_OK;
457 }
458
459 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
460 hwaddr addr,
461 uint64_t *value,
462 unsigned size,
463 unsigned shift,
464 uint64_t mask,
465 MemTxAttrs attrs)
466 {
467 uint64_t tmp;
468
469 tmp = mr->ops->read(mr->opaque, addr, size);
470 if (mr->subpage) {
471 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
472 } else if (mr == &io_mem_notdirty) {
473 /* Accesses to code which has previously been translated into a TB show
474 * up in the MMIO path, as accesses to the io_mem_notdirty
475 * MemoryRegion. */
476 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
477 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
478 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
479 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
480 }
481 *value |= (tmp & mask) << shift;
482 return MEMTX_OK;
483 }
484
485 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
486 hwaddr addr,
487 uint64_t *value,
488 unsigned size,
489 unsigned shift,
490 uint64_t mask,
491 MemTxAttrs attrs)
492 {
493 uint64_t tmp = 0;
494 MemTxResult r;
495
496 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
497 if (mr->subpage) {
498 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
499 } else if (mr == &io_mem_notdirty) {
500 /* Accesses to code which has previously been translated into a TB show
501 * up in the MMIO path, as accesses to the io_mem_notdirty
502 * MemoryRegion. */
503 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
504 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
505 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
506 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
507 }
508 *value |= (tmp & mask) << shift;
509 return r;
510 }
511
512 static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
516 unsigned shift,
517 uint64_t mask,
518 MemTxAttrs attrs)
519 {
520 uint64_t tmp;
521
522 tmp = (*value >> shift) & mask;
523 if (mr->subpage) {
524 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
525 } else if (mr == &io_mem_notdirty) {
526 /* Accesses to code which has previously been translated into a TB show
527 * up in the MMIO path, as accesses to the io_mem_notdirty
528 * MemoryRegion. */
529 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
530 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
531 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
532 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
533 }
534 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
535 return MEMTX_OK;
536 }
537
538 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
539 hwaddr addr,
540 uint64_t *value,
541 unsigned size,
542 unsigned shift,
543 uint64_t mask,
544 MemTxAttrs attrs)
545 {
546 uint64_t tmp;
547
548 tmp = (*value >> shift) & mask;
549 if (mr->subpage) {
550 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
551 } else if (mr == &io_mem_notdirty) {
552 /* Accesses to code which has previously been translated into a TB show
553 * up in the MMIO path, as accesses to the io_mem_notdirty
554 * MemoryRegion. */
555 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
556 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
557 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
558 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
559 }
560 mr->ops->write(mr->opaque, addr, tmp, size);
561 return MEMTX_OK;
562 }
563
564 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
565 hwaddr addr,
566 uint64_t *value,
567 unsigned size,
568 unsigned shift,
569 uint64_t mask,
570 MemTxAttrs attrs)
571 {
572 uint64_t tmp;
573
574 tmp = (*value >> shift) & mask;
575 if (mr->subpage) {
576 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
577 } else if (mr == &io_mem_notdirty) {
578 /* Accesses to code which has previously been translated into a TB show
579 * up in the MMIO path, as accesses to the io_mem_notdirty
580 * MemoryRegion. */
581 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
582 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
583 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
584 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
585 }
586 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
587 }
588
589 static MemTxResult access_with_adjusted_size(hwaddr addr,
590 uint64_t *value,
591 unsigned size,
592 unsigned access_size_min,
593 unsigned access_size_max,
594 MemTxResult (*access_fn)
595 (MemoryRegion *mr,
596 hwaddr addr,
597 uint64_t *value,
598 unsigned size,
599 unsigned shift,
600 uint64_t mask,
601 MemTxAttrs attrs),
602 MemoryRegion *mr,
603 MemTxAttrs attrs)
604 {
605 uint64_t access_mask;
606 unsigned access_size;
607 unsigned i;
608 MemTxResult r = MEMTX_OK;
609
610 if (!access_size_min) {
611 access_size_min = 1;
612 }
613 if (!access_size_max) {
614 access_size_max = 4;
615 }
616
617 /* FIXME: support unaligned access? */
618 access_size = MAX(MIN(size, access_size_max), access_size_min);
619 access_mask = -1ULL >> (64 - access_size * 8);
620 if (memory_region_big_endian(mr)) {
621 for (i = 0; i < size; i += access_size) {
622 r |= access_fn(mr, addr + i, value, access_size,
623 (size - access_size - i) * 8, access_mask, attrs);
624 }
625 } else {
626 for (i = 0; i < size; i += access_size) {
627 r |= access_fn(mr, addr + i, value, access_size, i * 8,
628 access_mask, attrs);
629 }
630 }
631 return r;
632 }
633
634 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
635 {
636 AddressSpace *as;
637
638 while (mr->container) {
639 mr = mr->container;
640 }
641 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
642 if (mr == as->root) {
643 return as;
644 }
645 }
646 return NULL;
647 }
648
649 /* Render a memory region into the global view. Ranges in @view obscure
650 * ranges in @mr.
651 */
652 static void render_memory_region(FlatView *view,
653 MemoryRegion *mr,
654 Int128 base,
655 AddrRange clip,
656 bool readonly)
657 {
658 MemoryRegion *subregion;
659 unsigned i;
660 hwaddr offset_in_region;
661 Int128 remain;
662 Int128 now;
663 FlatRange fr;
664 AddrRange tmp;
665
666 if (!mr->enabled) {
667 return;
668 }
669
670 int128_addto(&base, int128_make64(mr->addr));
671 readonly |= mr->readonly;
672
673 tmp = addrrange_make(base, mr->size);
674
675 if (!addrrange_intersects(tmp, clip)) {
676 return;
677 }
678
679 clip = addrrange_intersection(tmp, clip);
680
681 if (mr->alias) {
682 int128_subfrom(&base, int128_make64(mr->alias->addr));
683 int128_subfrom(&base, int128_make64(mr->alias_offset));
684 render_memory_region(view, mr->alias, base, clip, readonly);
685 return;
686 }
687
688 /* Render subregions in priority order. */
689 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
690 render_memory_region(view, subregion, base, clip, readonly);
691 }
692
693 if (!mr->terminates) {
694 return;
695 }
696
697 offset_in_region = int128_get64(int128_sub(clip.start, base));
698 base = clip.start;
699 remain = clip.size;
700
701 fr.mr = mr;
702 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
703 fr.romd_mode = mr->romd_mode;
704 fr.readonly = readonly;
705
706 /* Render the region itself into any gaps left by the current view. */
707 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
708 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
709 continue;
710 }
711 if (int128_lt(base, view->ranges[i].addr.start)) {
712 now = int128_min(remain,
713 int128_sub(view->ranges[i].addr.start, base));
714 fr.offset_in_region = offset_in_region;
715 fr.addr = addrrange_make(base, now);
716 flatview_insert(view, i, &fr);
717 ++i;
718 int128_addto(&base, now);
719 offset_in_region += int128_get64(now);
720 int128_subfrom(&remain, now);
721 }
722 now = int128_sub(int128_min(int128_add(base, remain),
723 addrrange_end(view->ranges[i].addr)),
724 base);
725 int128_addto(&base, now);
726 offset_in_region += int128_get64(now);
727 int128_subfrom(&remain, now);
728 }
729 if (int128_nz(remain)) {
730 fr.offset_in_region = offset_in_region;
731 fr.addr = addrrange_make(base, remain);
732 flatview_insert(view, i, &fr);
733 }
734 }
735
736 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
737 {
738 while (mr->enabled) {
739 if (mr->alias) {
740 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
741 /* The alias is included in its entirety. Use it as
742 * the "real" root, so that we can share more FlatViews.
743 */
744 mr = mr->alias;
745 continue;
746 }
747 } else if (!mr->terminates) {
748 unsigned int found = 0;
749 MemoryRegion *child, *next = NULL;
750 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
751 if (child->enabled) {
752 if (++found > 1) {
753 next = NULL;
754 break;
755 }
756 if (!child->addr && int128_ge(mr->size, child->size)) {
757 /* A child is included in its entirety. If it's the only
758 * enabled one, use it in the hope of finding an alias down the
759 * way. This will also let us share FlatViews.
760 */
761 next = child;
762 }
763 }
764 }
765 if (found == 0) {
766 return NULL;
767 }
768 if (next) {
769 mr = next;
770 continue;
771 }
772 }
773
774 return mr;
775 }
776
777 return NULL;
778 }
779
780 /* Render a memory topology into a list of disjoint absolute ranges. */
781 static FlatView *generate_memory_topology(MemoryRegion *mr)
782 {
783 int i;
784 FlatView *view;
785
786 view = flatview_new(mr);
787
788 if (mr) {
789 render_memory_region(view, mr, int128_zero(),
790 addrrange_make(int128_zero(), int128_2_64()), false);
791 }
792 flatview_simplify(view);
793
794 view->dispatch = address_space_dispatch_new(view);
795 for (i = 0; i < view->nr; i++) {
796 MemoryRegionSection mrs =
797 section_from_flat_range(&view->ranges[i], view);
798 flatview_add_to_dispatch(view, &mrs);
799 }
800 address_space_dispatch_compact(view->dispatch);
801 g_hash_table_replace(flat_views, mr, view);
802
803 return view;
804 }
805
806 static void address_space_add_del_ioeventfds(AddressSpace *as,
807 MemoryRegionIoeventfd *fds_new,
808 unsigned fds_new_nb,
809 MemoryRegionIoeventfd *fds_old,
810 unsigned fds_old_nb)
811 {
812 unsigned iold, inew;
813 MemoryRegionIoeventfd *fd;
814 MemoryRegionSection section;
815
816 /* Generate a symmetric difference of the old and new fd sets, adding
817 * and deleting as necessary.
818 */
819
820 iold = inew = 0;
821 while (iold < fds_old_nb || inew < fds_new_nb) {
822 if (iold < fds_old_nb
823 && (inew == fds_new_nb
824 || memory_region_ioeventfd_before(fds_old[iold],
825 fds_new[inew]))) {
826 fd = &fds_old[iold];
827 section = (MemoryRegionSection) {
828 .fv = address_space_to_flatview(as),
829 .offset_within_address_space = int128_get64(fd->addr.start),
830 .size = fd->addr.size,
831 };
832 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
833 fd->match_data, fd->data, fd->e);
834 ++iold;
835 } else if (inew < fds_new_nb
836 && (iold == fds_old_nb
837 || memory_region_ioeventfd_before(fds_new[inew],
838 fds_old[iold]))) {
839 fd = &fds_new[inew];
840 section = (MemoryRegionSection) {
841 .fv = address_space_to_flatview(as),
842 .offset_within_address_space = int128_get64(fd->addr.start),
843 .size = fd->addr.size,
844 };
845 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
846 fd->match_data, fd->data, fd->e);
847 ++inew;
848 } else {
849 ++iold;
850 ++inew;
851 }
852 }
853 }
854
855 static FlatView *address_space_get_flatview(AddressSpace *as)
856 {
857 FlatView *view;
858
859 rcu_read_lock();
860 do {
861 view = address_space_to_flatview(as);
862 /* If somebody has replaced as->current_map concurrently,
863 * flatview_ref returns false.
864 */
865 } while (!flatview_ref(view));
866 rcu_read_unlock();
867 return view;
868 }
869
870 static void address_space_update_ioeventfds(AddressSpace *as)
871 {
872 FlatView *view;
873 FlatRange *fr;
874 unsigned ioeventfd_nb = 0;
875 MemoryRegionIoeventfd *ioeventfds = NULL;
876 AddrRange tmp;
877 unsigned i;
878
879 view = address_space_get_flatview(as);
880 FOR_EACH_FLAT_RANGE(fr, view) {
881 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
882 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
883 int128_sub(fr->addr.start,
884 int128_make64(fr->offset_in_region)));
885 if (addrrange_intersects(fr->addr, tmp)) {
886 ++ioeventfd_nb;
887 ioeventfds = g_realloc(ioeventfds,
888 ioeventfd_nb * sizeof(*ioeventfds));
889 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
890 ioeventfds[ioeventfd_nb-1].addr = tmp;
891 }
892 }
893 }
894
895 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
896 as->ioeventfds, as->ioeventfd_nb);
897
898 g_free(as->ioeventfds);
899 as->ioeventfds = ioeventfds;
900 as->ioeventfd_nb = ioeventfd_nb;
901 flatview_unref(view);
902 }
903
904 static void address_space_update_topology_pass(AddressSpace *as,
905 const FlatView *old_view,
906 const FlatView *new_view,
907 bool adding)
908 {
909 unsigned iold, inew;
910 FlatRange *frold, *frnew;
911
912 /* Generate a symmetric difference of the old and new memory maps.
913 * Kill ranges in the old map, and instantiate ranges in the new map.
914 */
915 iold = inew = 0;
916 while (iold < old_view->nr || inew < new_view->nr) {
917 if (iold < old_view->nr) {
918 frold = &old_view->ranges[iold];
919 } else {
920 frold = NULL;
921 }
922 if (inew < new_view->nr) {
923 frnew = &new_view->ranges[inew];
924 } else {
925 frnew = NULL;
926 }
927
928 if (frold
929 && (!frnew
930 || int128_lt(frold->addr.start, frnew->addr.start)
931 || (int128_eq(frold->addr.start, frnew->addr.start)
932 && !flatrange_equal(frold, frnew)))) {
933 /* In old but not in new, or in both but attributes changed. */
934
935 if (!adding) {
936 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
937 }
938
939 ++iold;
940 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
941 /* In both and unchanged (except logging may have changed) */
942
943 if (adding) {
944 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
945 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
946 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
947 frold->dirty_log_mask,
948 frnew->dirty_log_mask);
949 }
950 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
951 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
952 frold->dirty_log_mask,
953 frnew->dirty_log_mask);
954 }
955 }
956
957 ++iold;
958 ++inew;
959 } else {
960 /* In new */
961
962 if (adding) {
963 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
964 }
965
966 ++inew;
967 }
968 }
969 }
970
971 static void flatviews_init(void)
972 {
973 static FlatView *empty_view;
974
975 if (flat_views) {
976 return;
977 }
978
979 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
980 (GDestroyNotify) flatview_unref);
981 if (!empty_view) {
982 empty_view = generate_memory_topology(NULL);
983 /* We keep it alive forever in the global variable. */
984 flatview_ref(empty_view);
985 } else {
986 g_hash_table_replace(flat_views, NULL, empty_view);
987 flatview_ref(empty_view);
988 }
989 }
990
991 static void flatviews_reset(void)
992 {
993 AddressSpace *as;
994
995 if (flat_views) {
996 g_hash_table_unref(flat_views);
997 flat_views = NULL;
998 }
999 flatviews_init();
1000
1001 /* Render unique FVs */
1002 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1003 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1004
1005 if (g_hash_table_lookup(flat_views, physmr)) {
1006 continue;
1007 }
1008
1009 generate_memory_topology(physmr);
1010 }
1011 }
1012
1013 static void address_space_set_flatview(AddressSpace *as)
1014 {
1015 FlatView *old_view = address_space_to_flatview(as);
1016 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1017 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1018
1019 assert(new_view);
1020
1021 if (old_view == new_view) {
1022 return;
1023 }
1024
1025 if (old_view) {
1026 flatview_ref(old_view);
1027 }
1028
1029 flatview_ref(new_view);
1030
1031 if (!QTAILQ_EMPTY(&as->listeners)) {
1032 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1033
1034 if (!old_view2) {
1035 old_view2 = &tmpview;
1036 }
1037 address_space_update_topology_pass(as, old_view2, new_view, false);
1038 address_space_update_topology_pass(as, old_view2, new_view, true);
1039 }
1040
1041 /* Writes are protected by the BQL. */
1042 atomic_rcu_set(&as->current_map, new_view);
1043 if (old_view) {
1044 flatview_unref(old_view);
1045 }
1046
1047 /* Note that all the old MemoryRegions are still alive up to this
1048 * point. This relieves most MemoryListeners from the need to
1049 * ref/unref the MemoryRegions they get---unless they use them
1050 * outside the iothread mutex, in which case precise reference
1051 * counting is necessary.
1052 */
1053 if (old_view) {
1054 flatview_unref(old_view);
1055 }
1056 }
1057
1058 static void address_space_update_topology(AddressSpace *as)
1059 {
1060 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1061
1062 flatviews_init();
1063 if (!g_hash_table_lookup(flat_views, physmr)) {
1064 generate_memory_topology(physmr);
1065 }
1066 address_space_set_flatview(as);
1067 }
1068
1069 void memory_region_transaction_begin(void)
1070 {
1071 qemu_flush_coalesced_mmio_buffer();
1072 ++memory_region_transaction_depth;
1073 }
1074
1075 void memory_region_transaction_commit(void)
1076 {
1077 AddressSpace *as;
1078
1079 assert(memory_region_transaction_depth);
1080 assert(qemu_mutex_iothread_locked());
1081
1082 --memory_region_transaction_depth;
1083 if (!memory_region_transaction_depth) {
1084 if (memory_region_update_pending) {
1085 flatviews_reset();
1086
1087 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1088
1089 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1090 address_space_set_flatview(as);
1091 address_space_update_ioeventfds(as);
1092 }
1093 memory_region_update_pending = false;
1094 ioeventfd_update_pending = false;
1095 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1096 } else if (ioeventfd_update_pending) {
1097 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1098 address_space_update_ioeventfds(as);
1099 }
1100 ioeventfd_update_pending = false;
1101 }
1102 }
1103 }
1104
1105 static void memory_region_destructor_none(MemoryRegion *mr)
1106 {
1107 }
1108
1109 static void memory_region_destructor_ram(MemoryRegion *mr)
1110 {
1111 qemu_ram_free(mr->ram_block);
1112 }
1113
1114 static bool memory_region_need_escape(char c)
1115 {
1116 return c == '/' || c == '[' || c == '\\' || c == ']';
1117 }
1118
1119 static char *memory_region_escape_name(const char *name)
1120 {
1121 const char *p;
1122 char *escaped, *q;
1123 uint8_t c;
1124 size_t bytes = 0;
1125
1126 for (p = name; *p; p++) {
1127 bytes += memory_region_need_escape(*p) ? 4 : 1;
1128 }
1129 if (bytes == p - name) {
1130 return g_memdup(name, bytes + 1);
1131 }
1132
1133 escaped = g_malloc(bytes + 1);
1134 for (p = name, q = escaped; *p; p++) {
1135 c = *p;
1136 if (unlikely(memory_region_need_escape(c))) {
1137 *q++ = '\\';
1138 *q++ = 'x';
1139 *q++ = "0123456789abcdef"[c >> 4];
1140 c = "0123456789abcdef"[c & 15];
1141 }
1142 *q++ = c;
1143 }
1144 *q = 0;
1145 return escaped;
1146 }
1147
1148 static void memory_region_do_init(MemoryRegion *mr,
1149 Object *owner,
1150 const char *name,
1151 uint64_t size)
1152 {
1153 mr->size = int128_make64(size);
1154 if (size == UINT64_MAX) {
1155 mr->size = int128_2_64();
1156 }
1157 mr->name = g_strdup(name);
1158 mr->owner = owner;
1159 mr->ram_block = NULL;
1160
1161 if (name) {
1162 char *escaped_name = memory_region_escape_name(name);
1163 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1164
1165 if (!owner) {
1166 owner = container_get(qdev_get_machine(), "/unattached");
1167 }
1168
1169 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1170 object_unref(OBJECT(mr));
1171 g_free(name_array);
1172 g_free(escaped_name);
1173 }
1174 }
1175
1176 void memory_region_init(MemoryRegion *mr,
1177 Object *owner,
1178 const char *name,
1179 uint64_t size)
1180 {
1181 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1182 memory_region_do_init(mr, owner, name, size);
1183 }
1184
1185 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1186 void *opaque, Error **errp)
1187 {
1188 MemoryRegion *mr = MEMORY_REGION(obj);
1189 uint64_t value = mr->addr;
1190
1191 visit_type_uint64(v, name, &value, errp);
1192 }
1193
1194 static void memory_region_get_container(Object *obj, Visitor *v,
1195 const char *name, void *opaque,
1196 Error **errp)
1197 {
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 gchar *path = (gchar *)"";
1200
1201 if (mr->container) {
1202 path = object_get_canonical_path(OBJECT(mr->container));
1203 }
1204 visit_type_str(v, name, &path, errp);
1205 if (mr->container) {
1206 g_free(path);
1207 }
1208 }
1209
1210 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1211 const char *part)
1212 {
1213 MemoryRegion *mr = MEMORY_REGION(obj);
1214
1215 return OBJECT(mr->container);
1216 }
1217
1218 static void memory_region_get_priority(Object *obj, Visitor *v,
1219 const char *name, void *opaque,
1220 Error **errp)
1221 {
1222 MemoryRegion *mr = MEMORY_REGION(obj);
1223 int32_t value = mr->priority;
1224
1225 visit_type_int32(v, name, &value, errp);
1226 }
1227
1228 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1229 void *opaque, Error **errp)
1230 {
1231 MemoryRegion *mr = MEMORY_REGION(obj);
1232 uint64_t value = memory_region_size(mr);
1233
1234 visit_type_uint64(v, name, &value, errp);
1235 }
1236
1237 static void memory_region_initfn(Object *obj)
1238 {
1239 MemoryRegion *mr = MEMORY_REGION(obj);
1240 ObjectProperty *op;
1241
1242 mr->ops = &unassigned_mem_ops;
1243 mr->enabled = true;
1244 mr->romd_mode = true;
1245 mr->global_locking = true;
1246 mr->destructor = memory_region_destructor_none;
1247 QTAILQ_INIT(&mr->subregions);
1248 QTAILQ_INIT(&mr->coalesced);
1249
1250 op = object_property_add(OBJECT(mr), "container",
1251 "link<" TYPE_MEMORY_REGION ">",
1252 memory_region_get_container,
1253 NULL, /* memory_region_set_container */
1254 NULL, NULL, &error_abort);
1255 op->resolve = memory_region_resolve_container;
1256
1257 object_property_add(OBJECT(mr), "addr", "uint64",
1258 memory_region_get_addr,
1259 NULL, /* memory_region_set_addr */
1260 NULL, NULL, &error_abort);
1261 object_property_add(OBJECT(mr), "priority", "uint32",
1262 memory_region_get_priority,
1263 NULL, /* memory_region_set_priority */
1264 NULL, NULL, &error_abort);
1265 object_property_add(OBJECT(mr), "size", "uint64",
1266 memory_region_get_size,
1267 NULL, /* memory_region_set_size, */
1268 NULL, NULL, &error_abort);
1269 }
1270
1271 static void iommu_memory_region_initfn(Object *obj)
1272 {
1273 MemoryRegion *mr = MEMORY_REGION(obj);
1274
1275 mr->is_iommu = true;
1276 }
1277
1278 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1279 unsigned size)
1280 {
1281 #ifdef DEBUG_UNASSIGNED
1282 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1283 #endif
1284 if (current_cpu != NULL) {
1285 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
1286 }
1287 return 0;
1288 }
1289
1290 static void unassigned_mem_write(void *opaque, hwaddr addr,
1291 uint64_t val, unsigned size)
1292 {
1293 #ifdef DEBUG_UNASSIGNED
1294 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1295 #endif
1296 if (current_cpu != NULL) {
1297 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1298 }
1299 }
1300
1301 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1302 unsigned size, bool is_write)
1303 {
1304 return false;
1305 }
1306
1307 const MemoryRegionOps unassigned_mem_ops = {
1308 .valid.accepts = unassigned_mem_accepts,
1309 .endianness = DEVICE_NATIVE_ENDIAN,
1310 };
1311
1312 static uint64_t memory_region_ram_device_read(void *opaque,
1313 hwaddr addr, unsigned size)
1314 {
1315 MemoryRegion *mr = opaque;
1316 uint64_t data = (uint64_t)~0;
1317
1318 switch (size) {
1319 case 1:
1320 data = *(uint8_t *)(mr->ram_block->host + addr);
1321 break;
1322 case 2:
1323 data = *(uint16_t *)(mr->ram_block->host + addr);
1324 break;
1325 case 4:
1326 data = *(uint32_t *)(mr->ram_block->host + addr);
1327 break;
1328 case 8:
1329 data = *(uint64_t *)(mr->ram_block->host + addr);
1330 break;
1331 }
1332
1333 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1334
1335 return data;
1336 }
1337
1338 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1339 uint64_t data, unsigned size)
1340 {
1341 MemoryRegion *mr = opaque;
1342
1343 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1344
1345 switch (size) {
1346 case 1:
1347 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1348 break;
1349 case 2:
1350 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1351 break;
1352 case 4:
1353 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1354 break;
1355 case 8:
1356 *(uint64_t *)(mr->ram_block->host + addr) = data;
1357 break;
1358 }
1359 }
1360
1361 static const MemoryRegionOps ram_device_mem_ops = {
1362 .read = memory_region_ram_device_read,
1363 .write = memory_region_ram_device_write,
1364 .endianness = DEVICE_HOST_ENDIAN,
1365 .valid = {
1366 .min_access_size = 1,
1367 .max_access_size = 8,
1368 .unaligned = true,
1369 },
1370 .impl = {
1371 .min_access_size = 1,
1372 .max_access_size = 8,
1373 .unaligned = true,
1374 },
1375 };
1376
1377 bool memory_region_access_valid(MemoryRegion *mr,
1378 hwaddr addr,
1379 unsigned size,
1380 bool is_write)
1381 {
1382 int access_size_min, access_size_max;
1383 int access_size, i;
1384
1385 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1386 return false;
1387 }
1388
1389 if (!mr->ops->valid.accepts) {
1390 return true;
1391 }
1392
1393 access_size_min = mr->ops->valid.min_access_size;
1394 if (!mr->ops->valid.min_access_size) {
1395 access_size_min = 1;
1396 }
1397
1398 access_size_max = mr->ops->valid.max_access_size;
1399 if (!mr->ops->valid.max_access_size) {
1400 access_size_max = 4;
1401 }
1402
1403 access_size = MAX(MIN(size, access_size_max), access_size_min);
1404 for (i = 0; i < size; i += access_size) {
1405 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1406 is_write)) {
1407 return false;
1408 }
1409 }
1410
1411 return true;
1412 }
1413
1414 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1415 hwaddr addr,
1416 uint64_t *pval,
1417 unsigned size,
1418 MemTxAttrs attrs)
1419 {
1420 *pval = 0;
1421
1422 if (mr->ops->read) {
1423 return access_with_adjusted_size(addr, pval, size,
1424 mr->ops->impl.min_access_size,
1425 mr->ops->impl.max_access_size,
1426 memory_region_read_accessor,
1427 mr, attrs);
1428 } else if (mr->ops->read_with_attrs) {
1429 return access_with_adjusted_size(addr, pval, size,
1430 mr->ops->impl.min_access_size,
1431 mr->ops->impl.max_access_size,
1432 memory_region_read_with_attrs_accessor,
1433 mr, attrs);
1434 } else {
1435 return access_with_adjusted_size(addr, pval, size, 1, 4,
1436 memory_region_oldmmio_read_accessor,
1437 mr, attrs);
1438 }
1439 }
1440
1441 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1442 hwaddr addr,
1443 uint64_t *pval,
1444 unsigned size,
1445 MemTxAttrs attrs)
1446 {
1447 MemTxResult r;
1448
1449 if (!memory_region_access_valid(mr, addr, size, false)) {
1450 *pval = unassigned_mem_read(mr, addr, size);
1451 return MEMTX_DECODE_ERROR;
1452 }
1453
1454 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1455 adjust_endianness(mr, pval, size);
1456 return r;
1457 }
1458
1459 /* Return true if an eventfd was signalled */
1460 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1461 hwaddr addr,
1462 uint64_t data,
1463 unsigned size,
1464 MemTxAttrs attrs)
1465 {
1466 MemoryRegionIoeventfd ioeventfd = {
1467 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1468 .data = data,
1469 };
1470 unsigned i;
1471
1472 for (i = 0; i < mr->ioeventfd_nb; i++) {
1473 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1474 ioeventfd.e = mr->ioeventfds[i].e;
1475
1476 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1477 event_notifier_set(ioeventfd.e);
1478 return true;
1479 }
1480 }
1481
1482 return false;
1483 }
1484
1485 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1486 hwaddr addr,
1487 uint64_t data,
1488 unsigned size,
1489 MemTxAttrs attrs)
1490 {
1491 if (!memory_region_access_valid(mr, addr, size, true)) {
1492 unassigned_mem_write(mr, addr, data, size);
1493 return MEMTX_DECODE_ERROR;
1494 }
1495
1496 adjust_endianness(mr, &data, size);
1497
1498 if ((!kvm_eventfds_enabled()) &&
1499 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1500 return MEMTX_OK;
1501 }
1502
1503 if (mr->ops->write) {
1504 return access_with_adjusted_size(addr, &data, size,
1505 mr->ops->impl.min_access_size,
1506 mr->ops->impl.max_access_size,
1507 memory_region_write_accessor, mr,
1508 attrs);
1509 } else if (mr->ops->write_with_attrs) {
1510 return
1511 access_with_adjusted_size(addr, &data, size,
1512 mr->ops->impl.min_access_size,
1513 mr->ops->impl.max_access_size,
1514 memory_region_write_with_attrs_accessor,
1515 mr, attrs);
1516 } else {
1517 return access_with_adjusted_size(addr, &data, size, 1, 4,
1518 memory_region_oldmmio_write_accessor,
1519 mr, attrs);
1520 }
1521 }
1522
1523 void memory_region_init_io(MemoryRegion *mr,
1524 Object *owner,
1525 const MemoryRegionOps *ops,
1526 void *opaque,
1527 const char *name,
1528 uint64_t size)
1529 {
1530 memory_region_init(mr, owner, name, size);
1531 mr->ops = ops ? ops : &unassigned_mem_ops;
1532 mr->opaque = opaque;
1533 mr->terminates = true;
1534 }
1535
1536 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1537 Object *owner,
1538 const char *name,
1539 uint64_t size,
1540 Error **errp)
1541 {
1542 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1543 }
1544
1545 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1546 Object *owner,
1547 const char *name,
1548 uint64_t size,
1549 bool share,
1550 Error **errp)
1551 {
1552 memory_region_init(mr, owner, name, size);
1553 mr->ram = true;
1554 mr->terminates = true;
1555 mr->destructor = memory_region_destructor_ram;
1556 mr->ram_block = qemu_ram_alloc(size, share, mr, errp);
1557 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1558 }
1559
1560 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1561 Object *owner,
1562 const char *name,
1563 uint64_t size,
1564 uint64_t max_size,
1565 void (*resized)(const char*,
1566 uint64_t length,
1567 void *host),
1568 Error **errp)
1569 {
1570 memory_region_init(mr, owner, name, size);
1571 mr->ram = true;
1572 mr->terminates = true;
1573 mr->destructor = memory_region_destructor_ram;
1574 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1575 mr, errp);
1576 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1577 }
1578
1579 #ifdef __linux__
1580 void memory_region_init_ram_from_file(MemoryRegion *mr,
1581 struct Object *owner,
1582 const char *name,
1583 uint64_t size,
1584 uint64_t align,
1585 bool share,
1586 const char *path,
1587 Error **errp)
1588 {
1589 memory_region_init(mr, owner, name, size);
1590 mr->ram = true;
1591 mr->terminates = true;
1592 mr->destructor = memory_region_destructor_ram;
1593 mr->align = align;
1594 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
1595 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1596 }
1597
1598 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1599 struct Object *owner,
1600 const char *name,
1601 uint64_t size,
1602 bool share,
1603 int fd,
1604 Error **errp)
1605 {
1606 memory_region_init(mr, owner, name, size);
1607 mr->ram = true;
1608 mr->terminates = true;
1609 mr->destructor = memory_region_destructor_ram;
1610 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1611 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1612 }
1613 #endif
1614
1615 void memory_region_init_ram_ptr(MemoryRegion *mr,
1616 Object *owner,
1617 const char *name,
1618 uint64_t size,
1619 void *ptr)
1620 {
1621 memory_region_init(mr, owner, name, size);
1622 mr->ram = true;
1623 mr->terminates = true;
1624 mr->destructor = memory_region_destructor_ram;
1625 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1626
1627 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1628 assert(ptr != NULL);
1629 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1630 }
1631
1632 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1633 Object *owner,
1634 const char *name,
1635 uint64_t size,
1636 void *ptr)
1637 {
1638 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1639 mr->ram_device = true;
1640 mr->ops = &ram_device_mem_ops;
1641 mr->opaque = mr;
1642 }
1643
1644 void memory_region_init_alias(MemoryRegion *mr,
1645 Object *owner,
1646 const char *name,
1647 MemoryRegion *orig,
1648 hwaddr offset,
1649 uint64_t size)
1650 {
1651 memory_region_init(mr, owner, name, size);
1652 mr->alias = orig;
1653 mr->alias_offset = offset;
1654 }
1655
1656 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1657 struct Object *owner,
1658 const char *name,
1659 uint64_t size,
1660 Error **errp)
1661 {
1662 memory_region_init(mr, owner, name, size);
1663 mr->ram = true;
1664 mr->readonly = true;
1665 mr->terminates = true;
1666 mr->destructor = memory_region_destructor_ram;
1667 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1668 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1669 }
1670
1671 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1672 Object *owner,
1673 const MemoryRegionOps *ops,
1674 void *opaque,
1675 const char *name,
1676 uint64_t size,
1677 Error **errp)
1678 {
1679 assert(ops);
1680 memory_region_init(mr, owner, name, size);
1681 mr->ops = ops;
1682 mr->opaque = opaque;
1683 mr->terminates = true;
1684 mr->rom_device = true;
1685 mr->destructor = memory_region_destructor_ram;
1686 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1687 }
1688
1689 void memory_region_init_iommu(void *_iommu_mr,
1690 size_t instance_size,
1691 const char *mrtypename,
1692 Object *owner,
1693 const char *name,
1694 uint64_t size)
1695 {
1696 struct IOMMUMemoryRegion *iommu_mr;
1697 struct MemoryRegion *mr;
1698
1699 object_initialize(_iommu_mr, instance_size, mrtypename);
1700 mr = MEMORY_REGION(_iommu_mr);
1701 memory_region_do_init(mr, owner, name, size);
1702 iommu_mr = IOMMU_MEMORY_REGION(mr);
1703 mr->terminates = true; /* then re-forwards */
1704 QLIST_INIT(&iommu_mr->iommu_notify);
1705 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1706 }
1707
1708 static void memory_region_finalize(Object *obj)
1709 {
1710 MemoryRegion *mr = MEMORY_REGION(obj);
1711
1712 assert(!mr->container);
1713
1714 /* We know the region is not visible in any address space (it
1715 * does not have a container and cannot be a root either because
1716 * it has no references, so we can blindly clear mr->enabled.
1717 * memory_region_set_enabled instead could trigger a transaction
1718 * and cause an infinite loop.
1719 */
1720 mr->enabled = false;
1721 memory_region_transaction_begin();
1722 while (!QTAILQ_EMPTY(&mr->subregions)) {
1723 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1724 memory_region_del_subregion(mr, subregion);
1725 }
1726 memory_region_transaction_commit();
1727
1728 mr->destructor(mr);
1729 memory_region_clear_coalescing(mr);
1730 g_free((char *)mr->name);
1731 g_free(mr->ioeventfds);
1732 }
1733
1734 Object *memory_region_owner(MemoryRegion *mr)
1735 {
1736 Object *obj = OBJECT(mr);
1737 return obj->parent;
1738 }
1739
1740 void memory_region_ref(MemoryRegion *mr)
1741 {
1742 /* MMIO callbacks most likely will access data that belongs
1743 * to the owner, hence the need to ref/unref the owner whenever
1744 * the memory region is in use.
1745 *
1746 * The memory region is a child of its owner. As long as the
1747 * owner doesn't call unparent itself on the memory region,
1748 * ref-ing the owner will also keep the memory region alive.
1749 * Memory regions without an owner are supposed to never go away;
1750 * we do not ref/unref them because it slows down DMA sensibly.
1751 */
1752 if (mr && mr->owner) {
1753 object_ref(mr->owner);
1754 }
1755 }
1756
1757 void memory_region_unref(MemoryRegion *mr)
1758 {
1759 if (mr && mr->owner) {
1760 object_unref(mr->owner);
1761 }
1762 }
1763
1764 uint64_t memory_region_size(MemoryRegion *mr)
1765 {
1766 if (int128_eq(mr->size, int128_2_64())) {
1767 return UINT64_MAX;
1768 }
1769 return int128_get64(mr->size);
1770 }
1771
1772 const char *memory_region_name(const MemoryRegion *mr)
1773 {
1774 if (!mr->name) {
1775 ((MemoryRegion *)mr)->name =
1776 object_get_canonical_path_component(OBJECT(mr));
1777 }
1778 return mr->name;
1779 }
1780
1781 bool memory_region_is_ram_device(MemoryRegion *mr)
1782 {
1783 return mr->ram_device;
1784 }
1785
1786 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1787 {
1788 uint8_t mask = mr->dirty_log_mask;
1789 if (global_dirty_log && mr->ram_block) {
1790 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1791 }
1792 return mask;
1793 }
1794
1795 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1796 {
1797 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1798 }
1799
1800 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1801 {
1802 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1803 IOMMUNotifier *iommu_notifier;
1804 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1805
1806 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1807 flags |= iommu_notifier->notifier_flags;
1808 }
1809
1810 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1811 imrc->notify_flag_changed(iommu_mr,
1812 iommu_mr->iommu_notify_flags,
1813 flags);
1814 }
1815
1816 iommu_mr->iommu_notify_flags = flags;
1817 }
1818
1819 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1820 IOMMUNotifier *n)
1821 {
1822 IOMMUMemoryRegion *iommu_mr;
1823
1824 if (mr->alias) {
1825 memory_region_register_iommu_notifier(mr->alias, n);
1826 return;
1827 }
1828
1829 /* We need to register for at least one bitfield */
1830 iommu_mr = IOMMU_MEMORY_REGION(mr);
1831 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1832 assert(n->start <= n->end);
1833 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1834 memory_region_update_iommu_notify_flags(iommu_mr);
1835 }
1836
1837 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1838 {
1839 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1840
1841 if (imrc->get_min_page_size) {
1842 return imrc->get_min_page_size(iommu_mr);
1843 }
1844 return TARGET_PAGE_SIZE;
1845 }
1846
1847 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1848 {
1849 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1850 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1851 hwaddr addr, granularity;
1852 IOMMUTLBEntry iotlb;
1853
1854 /* If the IOMMU has its own replay callback, override */
1855 if (imrc->replay) {
1856 imrc->replay(iommu_mr, n);
1857 return;
1858 }
1859
1860 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1861
1862 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1863 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
1864 if (iotlb.perm != IOMMU_NONE) {
1865 n->notify(n, &iotlb);
1866 }
1867
1868 /* if (2^64 - MR size) < granularity, it's possible to get an
1869 * infinite loop here. This should catch such a wraparound */
1870 if ((addr + granularity) < addr) {
1871 break;
1872 }
1873 }
1874 }
1875
1876 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1877 {
1878 IOMMUNotifier *notifier;
1879
1880 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1881 memory_region_iommu_replay(iommu_mr, notifier);
1882 }
1883 }
1884
1885 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1886 IOMMUNotifier *n)
1887 {
1888 IOMMUMemoryRegion *iommu_mr;
1889
1890 if (mr->alias) {
1891 memory_region_unregister_iommu_notifier(mr->alias, n);
1892 return;
1893 }
1894 QLIST_REMOVE(n, node);
1895 iommu_mr = IOMMU_MEMORY_REGION(mr);
1896 memory_region_update_iommu_notify_flags(iommu_mr);
1897 }
1898
1899 void memory_region_notify_one(IOMMUNotifier *notifier,
1900 IOMMUTLBEntry *entry)
1901 {
1902 IOMMUNotifierFlag request_flags;
1903
1904 /*
1905 * Skip the notification if the notification does not overlap
1906 * with registered range.
1907 */
1908 if (notifier->start > entry->iova + entry->addr_mask ||
1909 notifier->end < entry->iova) {
1910 return;
1911 }
1912
1913 if (entry->perm & IOMMU_RW) {
1914 request_flags = IOMMU_NOTIFIER_MAP;
1915 } else {
1916 request_flags = IOMMU_NOTIFIER_UNMAP;
1917 }
1918
1919 if (notifier->notifier_flags & request_flags) {
1920 notifier->notify(notifier, entry);
1921 }
1922 }
1923
1924 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1925 IOMMUTLBEntry entry)
1926 {
1927 IOMMUNotifier *iommu_notifier;
1928
1929 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1930
1931 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1932 memory_region_notify_one(iommu_notifier, &entry);
1933 }
1934 }
1935
1936 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1937 enum IOMMUMemoryRegionAttr attr,
1938 void *data)
1939 {
1940 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1941
1942 if (!imrc->get_attr) {
1943 return -EINVAL;
1944 }
1945
1946 return imrc->get_attr(iommu_mr, attr, data);
1947 }
1948
1949 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1950 {
1951 uint8_t mask = 1 << client;
1952 uint8_t old_logging;
1953
1954 assert(client == DIRTY_MEMORY_VGA);
1955 old_logging = mr->vga_logging_count;
1956 mr->vga_logging_count += log ? 1 : -1;
1957 if (!!old_logging == !!mr->vga_logging_count) {
1958 return;
1959 }
1960
1961 memory_region_transaction_begin();
1962 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
1963 memory_region_update_pending |= mr->enabled;
1964 memory_region_transaction_commit();
1965 }
1966
1967 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1968 hwaddr size, unsigned client)
1969 {
1970 assert(mr->ram_block);
1971 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1972 size, client);
1973 }
1974
1975 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1976 hwaddr size)
1977 {
1978 assert(mr->ram_block);
1979 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1980 size,
1981 memory_region_get_dirty_log_mask(mr));
1982 }
1983
1984 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1985 {
1986 MemoryListener *listener;
1987 AddressSpace *as;
1988 FlatView *view;
1989 FlatRange *fr;
1990
1991 /* If the same address space has multiple log_sync listeners, we
1992 * visit that address space's FlatView multiple times. But because
1993 * log_sync listeners are rare, it's still cheaper than walking each
1994 * address space once.
1995 */
1996 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1997 if (!listener->log_sync) {
1998 continue;
1999 }
2000 as = listener->address_space;
2001 view = address_space_get_flatview(as);
2002 FOR_EACH_FLAT_RANGE(fr, view) {
2003 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2004 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2005 listener->log_sync(listener, &mrs);
2006 }
2007 }
2008 flatview_unref(view);
2009 }
2010 }
2011
2012 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2013 hwaddr addr,
2014 hwaddr size,
2015 unsigned client)
2016 {
2017 assert(mr->ram_block);
2018 memory_region_sync_dirty_bitmap(mr);
2019 return cpu_physical_memory_snapshot_and_clear_dirty(
2020 memory_region_get_ram_addr(mr) + addr, size, client);
2021 }
2022
2023 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2024 hwaddr addr, hwaddr size)
2025 {
2026 assert(mr->ram_block);
2027 return cpu_physical_memory_snapshot_get_dirty(snap,
2028 memory_region_get_ram_addr(mr) + addr, size);
2029 }
2030
2031 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2032 {
2033 if (mr->readonly != readonly) {
2034 memory_region_transaction_begin();
2035 mr->readonly = readonly;
2036 memory_region_update_pending |= mr->enabled;
2037 memory_region_transaction_commit();
2038 }
2039 }
2040
2041 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2042 {
2043 if (mr->romd_mode != romd_mode) {
2044 memory_region_transaction_begin();
2045 mr->romd_mode = romd_mode;
2046 memory_region_update_pending |= mr->enabled;
2047 memory_region_transaction_commit();
2048 }
2049 }
2050
2051 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2052 hwaddr size, unsigned client)
2053 {
2054 assert(mr->ram_block);
2055 cpu_physical_memory_test_and_clear_dirty(
2056 memory_region_get_ram_addr(mr) + addr, size, client);
2057 }
2058
2059 int memory_region_get_fd(MemoryRegion *mr)
2060 {
2061 int fd;
2062
2063 rcu_read_lock();
2064 while (mr->alias) {
2065 mr = mr->alias;
2066 }
2067 fd = mr->ram_block->fd;
2068 rcu_read_unlock();
2069
2070 return fd;
2071 }
2072
2073 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2074 {
2075 void *ptr;
2076 uint64_t offset = 0;
2077
2078 rcu_read_lock();
2079 while (mr->alias) {
2080 offset += mr->alias_offset;
2081 mr = mr->alias;
2082 }
2083 assert(mr->ram_block);
2084 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2085 rcu_read_unlock();
2086
2087 return ptr;
2088 }
2089
2090 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2091 {
2092 RAMBlock *block;
2093
2094 block = qemu_ram_block_from_host(ptr, false, offset);
2095 if (!block) {
2096 return NULL;
2097 }
2098
2099 return block->mr;
2100 }
2101
2102 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2103 {
2104 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2105 }
2106
2107 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2108 {
2109 assert(mr->ram_block);
2110
2111 qemu_ram_resize(mr->ram_block, newsize, errp);
2112 }
2113
2114 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2115 {
2116 FlatView *view;
2117 FlatRange *fr;
2118 CoalescedMemoryRange *cmr;
2119 AddrRange tmp;
2120 MemoryRegionSection section;
2121
2122 view = address_space_get_flatview(as);
2123 FOR_EACH_FLAT_RANGE(fr, view) {
2124 if (fr->mr == mr) {
2125 section = (MemoryRegionSection) {
2126 .fv = view,
2127 .offset_within_address_space = int128_get64(fr->addr.start),
2128 .size = fr->addr.size,
2129 };
2130
2131 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
2132 int128_get64(fr->addr.start),
2133 int128_get64(fr->addr.size));
2134 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2135 tmp = addrrange_shift(cmr->addr,
2136 int128_sub(fr->addr.start,
2137 int128_make64(fr->offset_in_region)));
2138 if (!addrrange_intersects(tmp, fr->addr)) {
2139 continue;
2140 }
2141 tmp = addrrange_intersection(tmp, fr->addr);
2142 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
2143 int128_get64(tmp.start),
2144 int128_get64(tmp.size));
2145 }
2146 }
2147 }
2148 flatview_unref(view);
2149 }
2150
2151 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2152 {
2153 AddressSpace *as;
2154
2155 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2156 memory_region_update_coalesced_range_as(mr, as);
2157 }
2158 }
2159
2160 void memory_region_set_coalescing(MemoryRegion *mr)
2161 {
2162 memory_region_clear_coalescing(mr);
2163 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2164 }
2165
2166 void memory_region_add_coalescing(MemoryRegion *mr,
2167 hwaddr offset,
2168 uint64_t size)
2169 {
2170 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2171
2172 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2173 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2174 memory_region_update_coalesced_range(mr);
2175 memory_region_set_flush_coalesced(mr);
2176 }
2177
2178 void memory_region_clear_coalescing(MemoryRegion *mr)
2179 {
2180 CoalescedMemoryRange *cmr;
2181 bool updated = false;
2182
2183 qemu_flush_coalesced_mmio_buffer();
2184 mr->flush_coalesced_mmio = false;
2185
2186 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2187 cmr = QTAILQ_FIRST(&mr->coalesced);
2188 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2189 g_free(cmr);
2190 updated = true;
2191 }
2192
2193 if (updated) {
2194 memory_region_update_coalesced_range(mr);
2195 }
2196 }
2197
2198 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2199 {
2200 mr->flush_coalesced_mmio = true;
2201 }
2202
2203 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2204 {
2205 qemu_flush_coalesced_mmio_buffer();
2206 if (QTAILQ_EMPTY(&mr->coalesced)) {
2207 mr->flush_coalesced_mmio = false;
2208 }
2209 }
2210
2211 void memory_region_clear_global_locking(MemoryRegion *mr)
2212 {
2213 mr->global_locking = false;
2214 }
2215
2216 static bool userspace_eventfd_warning;
2217
2218 void memory_region_add_eventfd(MemoryRegion *mr,
2219 hwaddr addr,
2220 unsigned size,
2221 bool match_data,
2222 uint64_t data,
2223 EventNotifier *e)
2224 {
2225 MemoryRegionIoeventfd mrfd = {
2226 .addr.start = int128_make64(addr),
2227 .addr.size = int128_make64(size),
2228 .match_data = match_data,
2229 .data = data,
2230 .e = e,
2231 };
2232 unsigned i;
2233
2234 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2235 userspace_eventfd_warning))) {
2236 userspace_eventfd_warning = true;
2237 error_report("Using eventfd without MMIO binding in KVM. "
2238 "Suboptimal performance expected");
2239 }
2240
2241 if (size) {
2242 adjust_endianness(mr, &mrfd.data, size);
2243 }
2244 memory_region_transaction_begin();
2245 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2246 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2247 break;
2248 }
2249 }
2250 ++mr->ioeventfd_nb;
2251 mr->ioeventfds = g_realloc(mr->ioeventfds,
2252 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2253 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2254 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2255 mr->ioeventfds[i] = mrfd;
2256 ioeventfd_update_pending |= mr->enabled;
2257 memory_region_transaction_commit();
2258 }
2259
2260 void memory_region_del_eventfd(MemoryRegion *mr,
2261 hwaddr addr,
2262 unsigned size,
2263 bool match_data,
2264 uint64_t data,
2265 EventNotifier *e)
2266 {
2267 MemoryRegionIoeventfd mrfd = {
2268 .addr.start = int128_make64(addr),
2269 .addr.size = int128_make64(size),
2270 .match_data = match_data,
2271 .data = data,
2272 .e = e,
2273 };
2274 unsigned i;
2275
2276 if (size) {
2277 adjust_endianness(mr, &mrfd.data, size);
2278 }
2279 memory_region_transaction_begin();
2280 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2281 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2282 break;
2283 }
2284 }
2285 assert(i != mr->ioeventfd_nb);
2286 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2287 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2288 --mr->ioeventfd_nb;
2289 mr->ioeventfds = g_realloc(mr->ioeventfds,
2290 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2291 ioeventfd_update_pending |= mr->enabled;
2292 memory_region_transaction_commit();
2293 }
2294
2295 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2296 {
2297 MemoryRegion *mr = subregion->container;
2298 MemoryRegion *other;
2299
2300 memory_region_transaction_begin();
2301
2302 memory_region_ref(subregion);
2303 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2304 if (subregion->priority >= other->priority) {
2305 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2306 goto done;
2307 }
2308 }
2309 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2310 done:
2311 memory_region_update_pending |= mr->enabled && subregion->enabled;
2312 memory_region_transaction_commit();
2313 }
2314
2315 static void memory_region_add_subregion_common(MemoryRegion *mr,
2316 hwaddr offset,
2317 MemoryRegion *subregion)
2318 {
2319 assert(!subregion->container);
2320 subregion->container = mr;
2321 subregion->addr = offset;
2322 memory_region_update_container_subregions(subregion);
2323 }
2324
2325 void memory_region_add_subregion(MemoryRegion *mr,
2326 hwaddr offset,
2327 MemoryRegion *subregion)
2328 {
2329 subregion->priority = 0;
2330 memory_region_add_subregion_common(mr, offset, subregion);
2331 }
2332
2333 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2334 hwaddr offset,
2335 MemoryRegion *subregion,
2336 int priority)
2337 {
2338 subregion->priority = priority;
2339 memory_region_add_subregion_common(mr, offset, subregion);
2340 }
2341
2342 void memory_region_del_subregion(MemoryRegion *mr,
2343 MemoryRegion *subregion)
2344 {
2345 memory_region_transaction_begin();
2346 assert(subregion->container == mr);
2347 subregion->container = NULL;
2348 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2349 memory_region_unref(subregion);
2350 memory_region_update_pending |= mr->enabled && subregion->enabled;
2351 memory_region_transaction_commit();
2352 }
2353
2354 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2355 {
2356 if (enabled == mr->enabled) {
2357 return;
2358 }
2359 memory_region_transaction_begin();
2360 mr->enabled = enabled;
2361 memory_region_update_pending = true;
2362 memory_region_transaction_commit();
2363 }
2364
2365 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2366 {
2367 Int128 s = int128_make64(size);
2368
2369 if (size == UINT64_MAX) {
2370 s = int128_2_64();
2371 }
2372 if (int128_eq(s, mr->size)) {
2373 return;
2374 }
2375 memory_region_transaction_begin();
2376 mr->size = s;
2377 memory_region_update_pending = true;
2378 memory_region_transaction_commit();
2379 }
2380
2381 static void memory_region_readd_subregion(MemoryRegion *mr)
2382 {
2383 MemoryRegion *container = mr->container;
2384
2385 if (container) {
2386 memory_region_transaction_begin();
2387 memory_region_ref(mr);
2388 memory_region_del_subregion(container, mr);
2389 mr->container = container;
2390 memory_region_update_container_subregions(mr);
2391 memory_region_unref(mr);
2392 memory_region_transaction_commit();
2393 }
2394 }
2395
2396 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2397 {
2398 if (addr != mr->addr) {
2399 mr->addr = addr;
2400 memory_region_readd_subregion(mr);
2401 }
2402 }
2403
2404 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2405 {
2406 assert(mr->alias);
2407
2408 if (offset == mr->alias_offset) {
2409 return;
2410 }
2411
2412 memory_region_transaction_begin();
2413 mr->alias_offset = offset;
2414 memory_region_update_pending |= mr->enabled;
2415 memory_region_transaction_commit();
2416 }
2417
2418 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2419 {
2420 return mr->align;
2421 }
2422
2423 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2424 {
2425 const AddrRange *addr = addr_;
2426 const FlatRange *fr = fr_;
2427
2428 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2429 return -1;
2430 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2431 return 1;
2432 }
2433 return 0;
2434 }
2435
2436 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2437 {
2438 return bsearch(&addr, view->ranges, view->nr,
2439 sizeof(FlatRange), cmp_flatrange_addr);
2440 }
2441
2442 bool memory_region_is_mapped(MemoryRegion *mr)
2443 {
2444 return mr->container ? true : false;
2445 }
2446
2447 /* Same as memory_region_find, but it does not add a reference to the
2448 * returned region. It must be called from an RCU critical section.
2449 */
2450 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2451 hwaddr addr, uint64_t size)
2452 {
2453 MemoryRegionSection ret = { .mr = NULL };
2454 MemoryRegion *root;
2455 AddressSpace *as;
2456 AddrRange range;
2457 FlatView *view;
2458 FlatRange *fr;
2459
2460 addr += mr->addr;
2461 for (root = mr; root->container; ) {
2462 root = root->container;
2463 addr += root->addr;
2464 }
2465
2466 as = memory_region_to_address_space(root);
2467 if (!as) {
2468 return ret;
2469 }
2470 range = addrrange_make(int128_make64(addr), int128_make64(size));
2471
2472 view = address_space_to_flatview(as);
2473 fr = flatview_lookup(view, range);
2474 if (!fr) {
2475 return ret;
2476 }
2477
2478 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2479 --fr;
2480 }
2481
2482 ret.mr = fr->mr;
2483 ret.fv = view;
2484 range = addrrange_intersection(range, fr->addr);
2485 ret.offset_within_region = fr->offset_in_region;
2486 ret.offset_within_region += int128_get64(int128_sub(range.start,
2487 fr->addr.start));
2488 ret.size = range.size;
2489 ret.offset_within_address_space = int128_get64(range.start);
2490 ret.readonly = fr->readonly;
2491 return ret;
2492 }
2493
2494 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2495 hwaddr addr, uint64_t size)
2496 {
2497 MemoryRegionSection ret;
2498 rcu_read_lock();
2499 ret = memory_region_find_rcu(mr, addr, size);
2500 if (ret.mr) {
2501 memory_region_ref(ret.mr);
2502 }
2503 rcu_read_unlock();
2504 return ret;
2505 }
2506
2507 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2508 {
2509 MemoryRegion *mr;
2510
2511 rcu_read_lock();
2512 mr = memory_region_find_rcu(container, addr, 1).mr;
2513 rcu_read_unlock();
2514 return mr && mr != container;
2515 }
2516
2517 void memory_global_dirty_log_sync(void)
2518 {
2519 memory_region_sync_dirty_bitmap(NULL);
2520 }
2521
2522 static VMChangeStateEntry *vmstate_change;
2523
2524 void memory_global_dirty_log_start(void)
2525 {
2526 if (vmstate_change) {
2527 qemu_del_vm_change_state_handler(vmstate_change);
2528 vmstate_change = NULL;
2529 }
2530
2531 global_dirty_log = true;
2532
2533 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2534
2535 /* Refresh DIRTY_LOG_MIGRATION bit. */
2536 memory_region_transaction_begin();
2537 memory_region_update_pending = true;
2538 memory_region_transaction_commit();
2539 }
2540
2541 static void memory_global_dirty_log_do_stop(void)
2542 {
2543 global_dirty_log = false;
2544
2545 /* Refresh DIRTY_LOG_MIGRATION bit. */
2546 memory_region_transaction_begin();
2547 memory_region_update_pending = true;
2548 memory_region_transaction_commit();
2549
2550 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2551 }
2552
2553 static void memory_vm_change_state_handler(void *opaque, int running,
2554 RunState state)
2555 {
2556 if (running) {
2557 memory_global_dirty_log_do_stop();
2558
2559 if (vmstate_change) {
2560 qemu_del_vm_change_state_handler(vmstate_change);
2561 vmstate_change = NULL;
2562 }
2563 }
2564 }
2565
2566 void memory_global_dirty_log_stop(void)
2567 {
2568 if (!runstate_is_running()) {
2569 if (vmstate_change) {
2570 return;
2571 }
2572 vmstate_change = qemu_add_vm_change_state_handler(
2573 memory_vm_change_state_handler, NULL);
2574 return;
2575 }
2576
2577 memory_global_dirty_log_do_stop();
2578 }
2579
2580 static void listener_add_address_space(MemoryListener *listener,
2581 AddressSpace *as)
2582 {
2583 FlatView *view;
2584 FlatRange *fr;
2585
2586 if (listener->begin) {
2587 listener->begin(listener);
2588 }
2589 if (global_dirty_log) {
2590 if (listener->log_global_start) {
2591 listener->log_global_start(listener);
2592 }
2593 }
2594
2595 view = address_space_get_flatview(as);
2596 FOR_EACH_FLAT_RANGE(fr, view) {
2597 MemoryRegionSection section = section_from_flat_range(fr, view);
2598
2599 if (listener->region_add) {
2600 listener->region_add(listener, &section);
2601 }
2602 if (fr->dirty_log_mask && listener->log_start) {
2603 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2604 }
2605 }
2606 if (listener->commit) {
2607 listener->commit(listener);
2608 }
2609 flatview_unref(view);
2610 }
2611
2612 static void listener_del_address_space(MemoryListener *listener,
2613 AddressSpace *as)
2614 {
2615 FlatView *view;
2616 FlatRange *fr;
2617
2618 if (listener->begin) {
2619 listener->begin(listener);
2620 }
2621 view = address_space_get_flatview(as);
2622 FOR_EACH_FLAT_RANGE(fr, view) {
2623 MemoryRegionSection section = section_from_flat_range(fr, view);
2624
2625 if (fr->dirty_log_mask && listener->log_stop) {
2626 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2627 }
2628 if (listener->region_del) {
2629 listener->region_del(listener, &section);
2630 }
2631 }
2632 if (listener->commit) {
2633 listener->commit(listener);
2634 }
2635 flatview_unref(view);
2636 }
2637
2638 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2639 {
2640 MemoryListener *other = NULL;
2641
2642 listener->address_space = as;
2643 if (QTAILQ_EMPTY(&memory_listeners)
2644 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2645 memory_listeners)->priority) {
2646 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2647 } else {
2648 QTAILQ_FOREACH(other, &memory_listeners, link) {
2649 if (listener->priority < other->priority) {
2650 break;
2651 }
2652 }
2653 QTAILQ_INSERT_BEFORE(other, listener, link);
2654 }
2655
2656 if (QTAILQ_EMPTY(&as->listeners)
2657 || listener->priority >= QTAILQ_LAST(&as->listeners,
2658 memory_listeners)->priority) {
2659 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2660 } else {
2661 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2662 if (listener->priority < other->priority) {
2663 break;
2664 }
2665 }
2666 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2667 }
2668
2669 listener_add_address_space(listener, as);
2670 }
2671
2672 void memory_listener_unregister(MemoryListener *listener)
2673 {
2674 if (!listener->address_space) {
2675 return;
2676 }
2677
2678 listener_del_address_space(listener, listener->address_space);
2679 QTAILQ_REMOVE(&memory_listeners, listener, link);
2680 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2681 listener->address_space = NULL;
2682 }
2683
2684 bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2685 {
2686 void *host;
2687 unsigned size = 0;
2688 unsigned offset = 0;
2689 Object *new_interface;
2690
2691 if (!mr || !mr->ops->request_ptr) {
2692 return false;
2693 }
2694
2695 /*
2696 * Avoid an update if the request_ptr call
2697 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2698 * a cache.
2699 */
2700 memory_region_transaction_begin();
2701
2702 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2703
2704 if (!host || !size) {
2705 memory_region_transaction_commit();
2706 return false;
2707 }
2708
2709 new_interface = object_new("mmio_interface");
2710 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2711 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2712 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2713 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2714 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2715 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2716
2717 memory_region_transaction_commit();
2718 return true;
2719 }
2720
2721 typedef struct MMIOPtrInvalidate {
2722 MemoryRegion *mr;
2723 hwaddr offset;
2724 unsigned size;
2725 int busy;
2726 int allocated;
2727 } MMIOPtrInvalidate;
2728
2729 #define MAX_MMIO_INVALIDATE 10
2730 static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2731
2732 static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2733 run_on_cpu_data data)
2734 {
2735 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2736 MemoryRegion *mr = invalidate_data->mr;
2737 hwaddr offset = invalidate_data->offset;
2738 unsigned size = invalidate_data->size;
2739 MemoryRegionSection section = memory_region_find(mr, offset, size);
2740
2741 qemu_mutex_lock_iothread();
2742
2743 /* Reset dirty so this doesn't happen later. */
2744 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2745
2746 if (section.mr != mr) {
2747 /* memory_region_find add a ref on section.mr */
2748 memory_region_unref(section.mr);
2749 if (MMIO_INTERFACE(section.mr->owner)) {
2750 /* We found the interface just drop it. */
2751 object_property_set_bool(section.mr->owner, false, "realized",
2752 NULL);
2753 object_unref(section.mr->owner);
2754 object_unparent(section.mr->owner);
2755 }
2756 }
2757
2758 qemu_mutex_unlock_iothread();
2759
2760 if (invalidate_data->allocated) {
2761 g_free(invalidate_data);
2762 } else {
2763 invalidate_data->busy = 0;
2764 }
2765 }
2766
2767 void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2768 unsigned size)
2769 {
2770 size_t i;
2771 MMIOPtrInvalidate *invalidate_data = NULL;
2772
2773 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2774 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2775 invalidate_data = &mmio_ptr_invalidate_list[i];
2776 break;
2777 }
2778 }
2779
2780 if (!invalidate_data) {
2781 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2782 invalidate_data->allocated = 1;
2783 }
2784
2785 invalidate_data->mr = mr;
2786 invalidate_data->offset = offset;
2787 invalidate_data->size = size;
2788
2789 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2790 RUN_ON_CPU_HOST_PTR(invalidate_data));
2791 }
2792
2793 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2794 {
2795 memory_region_ref(root);
2796 as->root = root;
2797 as->current_map = NULL;
2798 as->ioeventfd_nb = 0;
2799 as->ioeventfds = NULL;
2800 QTAILQ_INIT(&as->listeners);
2801 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2802 as->name = g_strdup(name ? name : "anonymous");
2803 address_space_update_topology(as);
2804 address_space_update_ioeventfds(as);
2805 }
2806
2807 static void do_address_space_destroy(AddressSpace *as)
2808 {
2809 assert(QTAILQ_EMPTY(&as->listeners));
2810
2811 flatview_unref(as->current_map);
2812 g_free(as->name);
2813 g_free(as->ioeventfds);
2814 memory_region_unref(as->root);
2815 }
2816
2817 void address_space_destroy(AddressSpace *as)
2818 {
2819 MemoryRegion *root = as->root;
2820
2821 /* Flush out anything from MemoryListeners listening in on this */
2822 memory_region_transaction_begin();
2823 as->root = NULL;
2824 memory_region_transaction_commit();
2825 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2826
2827 /* At this point, as->dispatch and as->current_map are dummy
2828 * entries that the guest should never use. Wait for the old
2829 * values to expire before freeing the data.
2830 */
2831 as->root = root;
2832 call_rcu(as, do_address_space_destroy, rcu);
2833 }
2834
2835 static const char *memory_region_type(MemoryRegion *mr)
2836 {
2837 if (memory_region_is_ram_device(mr)) {
2838 return "ramd";
2839 } else if (memory_region_is_romd(mr)) {
2840 return "romd";
2841 } else if (memory_region_is_rom(mr)) {
2842 return "rom";
2843 } else if (memory_region_is_ram(mr)) {
2844 return "ram";
2845 } else {
2846 return "i/o";
2847 }
2848 }
2849
2850 typedef struct MemoryRegionList MemoryRegionList;
2851
2852 struct MemoryRegionList {
2853 const MemoryRegion *mr;
2854 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2855 };
2856
2857 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2858
2859 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2860 int128_sub((size), int128_one())) : 0)
2861 #define MTREE_INDENT " "
2862
2863 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2864 const MemoryRegion *mr, unsigned int level,
2865 hwaddr base,
2866 MemoryRegionListHead *alias_print_queue)
2867 {
2868 MemoryRegionList *new_ml, *ml, *next_ml;
2869 MemoryRegionListHead submr_print_queue;
2870 const MemoryRegion *submr;
2871 unsigned int i;
2872 hwaddr cur_start, cur_end;
2873
2874 if (!mr) {
2875 return;
2876 }
2877
2878 for (i = 0; i < level; i++) {
2879 mon_printf(f, MTREE_INDENT);
2880 }
2881
2882 cur_start = base + mr->addr;
2883 cur_end = cur_start + MR_SIZE(mr->size);
2884
2885 /*
2886 * Try to detect overflow of memory region. This should never
2887 * happen normally. When it happens, we dump something to warn the
2888 * user who is observing this.
2889 */
2890 if (cur_start < base || cur_end < cur_start) {
2891 mon_printf(f, "[DETECTED OVERFLOW!] ");
2892 }
2893
2894 if (mr->alias) {
2895 MemoryRegionList *ml;
2896 bool found = false;
2897
2898 /* check if the alias is already in the queue */
2899 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2900 if (ml->mr == mr->alias) {
2901 found = true;
2902 }
2903 }
2904
2905 if (!found) {
2906 ml = g_new(MemoryRegionList, 1);
2907 ml->mr = mr->alias;
2908 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2909 }
2910 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2911 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2912 "-" TARGET_FMT_plx "%s\n",
2913 cur_start, cur_end,
2914 mr->priority,
2915 memory_region_type((MemoryRegion *)mr),
2916 memory_region_name(mr),
2917 memory_region_name(mr->alias),
2918 mr->alias_offset,
2919 mr->alias_offset + MR_SIZE(mr->size),
2920 mr->enabled ? "" : " [disabled]");
2921 } else {
2922 mon_printf(f,
2923 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
2924 cur_start, cur_end,
2925 mr->priority,
2926 memory_region_type((MemoryRegion *)mr),
2927 memory_region_name(mr),
2928 mr->enabled ? "" : " [disabled]");
2929 }
2930
2931 QTAILQ_INIT(&submr_print_queue);
2932
2933 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2934 new_ml = g_new(MemoryRegionList, 1);
2935 new_ml->mr = submr;
2936 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2937 if (new_ml->mr->addr < ml->mr->addr ||
2938 (new_ml->mr->addr == ml->mr->addr &&
2939 new_ml->mr->priority > ml->mr->priority)) {
2940 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2941 new_ml = NULL;
2942 break;
2943 }
2944 }
2945 if (new_ml) {
2946 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2947 }
2948 }
2949
2950 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2951 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2952 alias_print_queue);
2953 }
2954
2955 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2956 g_free(ml);
2957 }
2958 }
2959
2960 struct FlatViewInfo {
2961 fprintf_function mon_printf;
2962 void *f;
2963 int counter;
2964 bool dispatch_tree;
2965 };
2966
2967 static void mtree_print_flatview(gpointer key, gpointer value,
2968 gpointer user_data)
2969 {
2970 FlatView *view = key;
2971 GArray *fv_address_spaces = value;
2972 struct FlatViewInfo *fvi = user_data;
2973 fprintf_function p = fvi->mon_printf;
2974 void *f = fvi->f;
2975 FlatRange *range = &view->ranges[0];
2976 MemoryRegion *mr;
2977 int n = view->nr;
2978 int i;
2979 AddressSpace *as;
2980
2981 p(f, "FlatView #%d\n", fvi->counter);
2982 ++fvi->counter;
2983
2984 for (i = 0; i < fv_address_spaces->len; ++i) {
2985 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2986 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2987 if (as->root->alias) {
2988 p(f, ", alias %s", memory_region_name(as->root->alias));
2989 }
2990 p(f, "\n");
2991 }
2992
2993 p(f, " Root memory region: %s\n",
2994 view->root ? memory_region_name(view->root) : "(none)");
2995
2996 if (n <= 0) {
2997 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2998 return;
2999 }
3000
3001 while (n--) {
3002 mr = range->mr;
3003 if (range->offset_in_region) {
3004 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3005 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
3006 int128_get64(range->addr.start),
3007 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3008 mr->priority,
3009 range->readonly ? "rom" : memory_region_type(mr),
3010 memory_region_name(mr),
3011 range->offset_in_region);
3012 } else {
3013 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3014 TARGET_FMT_plx " (prio %d, %s): %s\n",
3015 int128_get64(range->addr.start),
3016 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3017 mr->priority,
3018 range->readonly ? "rom" : memory_region_type(mr),
3019 memory_region_name(mr));
3020 }
3021 range++;
3022 }
3023
3024 #if !defined(CONFIG_USER_ONLY)
3025 if (fvi->dispatch_tree && view->root) {
3026 mtree_print_dispatch(p, f, view->dispatch, view->root);
3027 }
3028 #endif
3029
3030 p(f, "\n");
3031 }
3032
3033 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3034 gpointer user_data)
3035 {
3036 FlatView *view = key;
3037 GArray *fv_address_spaces = value;
3038
3039 g_array_unref(fv_address_spaces);
3040 flatview_unref(view);
3041
3042 return true;
3043 }
3044
3045 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3046 bool dispatch_tree)
3047 {
3048 MemoryRegionListHead ml_head;
3049 MemoryRegionList *ml, *ml2;
3050 AddressSpace *as;
3051
3052 if (flatview) {
3053 FlatView *view;
3054 struct FlatViewInfo fvi = {
3055 .mon_printf = mon_printf,
3056 .f = f,
3057 .counter = 0,
3058 .dispatch_tree = dispatch_tree
3059 };
3060 GArray *fv_address_spaces;
3061 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3062
3063 /* Gather all FVs in one table */
3064 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3065 view = address_space_get_flatview(as);
3066
3067 fv_address_spaces = g_hash_table_lookup(views, view);
3068 if (!fv_address_spaces) {
3069 fv_address_spaces = g_array_new(false, false, sizeof(as));
3070 g_hash_table_insert(views, view, fv_address_spaces);
3071 }
3072
3073 g_array_append_val(fv_address_spaces, as);
3074 }
3075
3076 /* Print */
3077 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3078
3079 /* Free */
3080 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3081 g_hash_table_unref(views);
3082
3083 return;
3084 }
3085
3086 QTAILQ_INIT(&ml_head);
3087
3088 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3089 mon_printf(f, "address-space: %s\n", as->name);
3090 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3091 mon_printf(f, "\n");
3092 }
3093
3094 /* print aliased regions */
3095 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3096 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3097 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3098 mon_printf(f, "\n");
3099 }
3100
3101 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3102 g_free(ml);
3103 }
3104 }
3105
3106 void memory_region_init_ram(MemoryRegion *mr,
3107 struct Object *owner,
3108 const char *name,
3109 uint64_t size,
3110 Error **errp)
3111 {
3112 DeviceState *owner_dev;
3113 Error *err = NULL;
3114
3115 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3116 if (err) {
3117 error_propagate(errp, err);
3118 return;
3119 }
3120 /* This will assert if owner is neither NULL nor a DeviceState.
3121 * We only want the owner here for the purposes of defining a
3122 * unique name for migration. TODO: Ideally we should implement
3123 * a naming scheme for Objects which are not DeviceStates, in
3124 * which case we can relax this restriction.
3125 */
3126 owner_dev = DEVICE(owner);
3127 vmstate_register_ram(mr, owner_dev);
3128 }
3129
3130 void memory_region_init_rom(MemoryRegion *mr,
3131 struct Object *owner,
3132 const char *name,
3133 uint64_t size,
3134 Error **errp)
3135 {
3136 DeviceState *owner_dev;
3137 Error *err = NULL;
3138
3139 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3140 if (err) {
3141 error_propagate(errp, err);
3142 return;
3143 }
3144 /* This will assert if owner is neither NULL nor a DeviceState.
3145 * We only want the owner here for the purposes of defining a
3146 * unique name for migration. TODO: Ideally we should implement
3147 * a naming scheme for Objects which are not DeviceStates, in
3148 * which case we can relax this restriction.
3149 */
3150 owner_dev = DEVICE(owner);
3151 vmstate_register_ram(mr, owner_dev);
3152 }
3153
3154 void memory_region_init_rom_device(MemoryRegion *mr,
3155 struct Object *owner,
3156 const MemoryRegionOps *ops,
3157 void *opaque,
3158 const char *name,
3159 uint64_t size,
3160 Error **errp)
3161 {
3162 DeviceState *owner_dev;
3163 Error *err = NULL;
3164
3165 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3166 name, size, &err);
3167 if (err) {
3168 error_propagate(errp, err);
3169 return;
3170 }
3171 /* This will assert if owner is neither NULL nor a DeviceState.
3172 * We only want the owner here for the purposes of defining a
3173 * unique name for migration. TODO: Ideally we should implement
3174 * a naming scheme for Objects which are not DeviceStates, in
3175 * which case we can relax this restriction.
3176 */
3177 owner_dev = DEVICE(owner);
3178 vmstate_register_ram(mr, owner_dev);
3179 }
3180
3181 static const TypeInfo memory_region_info = {
3182 .parent = TYPE_OBJECT,
3183 .name = TYPE_MEMORY_REGION,
3184 .instance_size = sizeof(MemoryRegion),
3185 .instance_init = memory_region_initfn,
3186 .instance_finalize = memory_region_finalize,
3187 };
3188
3189 static const TypeInfo iommu_memory_region_info = {
3190 .parent = TYPE_MEMORY_REGION,
3191 .name = TYPE_IOMMU_MEMORY_REGION,
3192 .class_size = sizeof(IOMMUMemoryRegionClass),
3193 .instance_size = sizeof(IOMMUMemoryRegion),
3194 .instance_init = iommu_memory_region_initfn,
3195 .abstract = true,
3196 };
3197
3198 static void memory_register_types(void)
3199 {
3200 type_register_static(&memory_region_info);
3201 type_register_static(&iommu_memory_region_info);
3202 }
3203
3204 type_init(memory_register_types)
Eric Blake's pending patches to qemu