2 * MIPS Boston development board emulation.
4 * Copyright (c) 2016 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
23 #include "exec/address-spaces.h"
24 #include "hw/boards.h"
25 #include "hw/char/serial.h"
26 #include "hw/ide/pci.h"
27 #include "hw/ide/ahci.h"
28 #include "hw/loader.h"
29 #include "hw/loader-fit.h"
30 #include "hw/mips/cps.h"
31 #include "hw/mips/cpudevs.h"
32 #include "hw/pci-host/xilinx-pcie.h"
33 #include "hw/qdev-properties.h"
34 #include "qapi/error.h"
35 #include "qemu/error-report.h"
37 #include "chardev/char.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/qtest.h"
41 #include "sysemu/runstate.h"
45 #define TYPE_MIPS_BOSTON "mips-boston"
46 #define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON)
49 SysBusDevice parent_obj
;
55 CharBackend lcd_display
;
63 enum boston_plat_reg
{
64 PLAT_FPGA_BUILD
= 0x00,
66 PLAT_WRAPPER_CL
= 0x08,
67 PLAT_SYSCLK_STATUS
= 0x0c,
68 PLAT_SOFTRST_CTL
= 0x10,
69 #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4)
70 PLAT_DDR3_STATUS
= 0x14,
71 #define PLAT_DDR3_STATUS_LOCKED (1 << 0)
72 #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2)
73 PLAT_PCIE_STATUS
= 0x18,
74 #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0)
75 #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8)
76 #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16)
77 PLAT_FLASH_CTL
= 0x1c,
83 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0
84 #define PLAT_MMCM_DIV_INPUT_SHIFT 8
85 #define PLAT_MMCM_DIV_MUL_SHIFT 16
86 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24
87 PLAT_BUILD_CFG
= 0x34,
88 #define PLAT_BUILD_CFG_IOCU_EN (1 << 0)
89 #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1)
90 #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2)
91 #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3)
93 #define PLAT_DDR_CFG_SIZE (0xf << 0)
94 #define PLAT_DDR_CFG_MHZ (0xfff << 4)
95 PLAT_NOC_PCIE0_ADDR
= 0x3c,
96 PLAT_NOC_PCIE1_ADDR
= 0x40,
97 PLAT_NOC_PCIE2_ADDR
= 0x44,
101 static void boston_lcd_event(void *opaque
, QEMUChrEvent event
)
103 BostonState
*s
= opaque
;
104 if (event
== CHR_EVENT_OPENED
&& !s
->lcd_inited
) {
105 qemu_chr_fe_printf(&s
->lcd_display
, " ");
106 s
->lcd_inited
= true;
110 static uint64_t boston_lcd_read(void *opaque
, hwaddr addr
,
113 BostonState
*s
= opaque
;
118 val
|= (uint64_t)s
->lcd_content
[(addr
+ 7) & 0x7] << 56;
119 val
|= (uint64_t)s
->lcd_content
[(addr
+ 6) & 0x7] << 48;
120 val
|= (uint64_t)s
->lcd_content
[(addr
+ 5) & 0x7] << 40;
121 val
|= (uint64_t)s
->lcd_content
[(addr
+ 4) & 0x7] << 32;
124 val
|= (uint64_t)s
->lcd_content
[(addr
+ 3) & 0x7] << 24;
125 val
|= (uint64_t)s
->lcd_content
[(addr
+ 2) & 0x7] << 16;
128 val
|= (uint64_t)s
->lcd_content
[(addr
+ 1) & 0x7] << 8;
131 val
|= (uint64_t)s
->lcd_content
[(addr
+ 0) & 0x7];
138 static void boston_lcd_write(void *opaque
, hwaddr addr
,
139 uint64_t val
, unsigned size
)
141 BostonState
*s
= opaque
;
145 s
->lcd_content
[(addr
+ 7) & 0x7] = val
>> 56;
146 s
->lcd_content
[(addr
+ 6) & 0x7] = val
>> 48;
147 s
->lcd_content
[(addr
+ 5) & 0x7] = val
>> 40;
148 s
->lcd_content
[(addr
+ 4) & 0x7] = val
>> 32;
151 s
->lcd_content
[(addr
+ 3) & 0x7] = val
>> 24;
152 s
->lcd_content
[(addr
+ 2) & 0x7] = val
>> 16;
155 s
->lcd_content
[(addr
+ 1) & 0x7] = val
>> 8;
158 s
->lcd_content
[(addr
+ 0) & 0x7] = val
;
162 qemu_chr_fe_printf(&s
->lcd_display
,
163 "\r%-8.8s", s
->lcd_content
);
166 static const MemoryRegionOps boston_lcd_ops
= {
167 .read
= boston_lcd_read
,
168 .write
= boston_lcd_write
,
169 .endianness
= DEVICE_NATIVE_ENDIAN
,
172 static uint64_t boston_platreg_read(void *opaque
, hwaddr addr
,
175 BostonState
*s
= opaque
;
176 uint32_t gic_freq
, val
;
179 qemu_log_mask(LOG_UNIMP
, "%uB platform register read\n", size
);
183 switch (addr
& 0xffff) {
184 case PLAT_FPGA_BUILD
:
186 case PLAT_WRAPPER_CL
:
188 case PLAT_DDR3_STATUS
:
189 return PLAT_DDR3_STATUS_LOCKED
| PLAT_DDR3_STATUS_CALIBRATED
;
191 gic_freq
= mips_gictimer_get_freq(s
->cps
.gic
.gic_timer
) / 1000000;
192 val
= gic_freq
<< PLAT_MMCM_DIV_INPUT_SHIFT
;
193 val
|= 1 << PLAT_MMCM_DIV_MUL_SHIFT
;
194 val
|= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT
;
195 val
|= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT
;
198 val
= PLAT_BUILD_CFG_PCIE0_EN
;
199 val
|= PLAT_BUILD_CFG_PCIE1_EN
;
200 val
|= PLAT_BUILD_CFG_PCIE2_EN
;
203 val
= s
->mach
->ram_size
/ GiB
;
204 assert(!(val
& ~PLAT_DDR_CFG_SIZE
));
205 val
|= PLAT_DDR_CFG_MHZ
;
208 qemu_log_mask(LOG_UNIMP
, "Read platform register 0x%" HWADDR_PRIx
"\n",
214 static void boston_platreg_write(void *opaque
, hwaddr addr
,
215 uint64_t val
, unsigned size
)
218 qemu_log_mask(LOG_UNIMP
, "%uB platform register write\n", size
);
222 switch (addr
& 0xffff) {
223 case PLAT_FPGA_BUILD
:
225 case PLAT_WRAPPER_CL
:
226 case PLAT_DDR3_STATUS
:
227 case PLAT_PCIE_STATUS
:
233 case PLAT_SOFTRST_CTL
:
234 if (val
& PLAT_SOFTRST_CTL_SYSRESET
) {
235 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
239 qemu_log_mask(LOG_UNIMP
, "Write platform register 0x%" HWADDR_PRIx
240 " = 0x%" PRIx64
"\n", addr
& 0xffff, val
);
245 static const MemoryRegionOps boston_platreg_ops
= {
246 .read
= boston_platreg_read
,
247 .write
= boston_platreg_write
,
248 .endianness
= DEVICE_NATIVE_ENDIAN
,
251 static const TypeInfo boston_device
= {
252 .name
= TYPE_MIPS_BOSTON
,
253 .parent
= TYPE_SYS_BUS_DEVICE
,
254 .instance_size
= sizeof(BostonState
),
257 static void boston_register_types(void)
259 type_register_static(&boston_device
);
261 type_init(boston_register_types
)
263 static void gen_firmware(uint32_t *p
, hwaddr kernel_entry
, hwaddr fdt_addr
,
266 const uint32_t cm_base
= 0x16100000;
267 const uint32_t gic_base
= 0x16120000;
268 const uint32_t cpc_base
= 0x16200000;
272 stl_p(p
++, 0x40287803); /* dmfc0 $8, CMGCRBase */
273 stl_p(p
++, 0x00084138); /* dsll $8, $8, 4 */
275 stl_p(p
++, 0x40087803); /* mfc0 $8, CMGCRBase */
276 stl_p(p
++, 0x00084100); /* sll $8, $8, 4 */
278 stl_p(p
++, 0x3c09a000); /* lui $9, 0xa000 */
279 stl_p(p
++, 0x01094025); /* or $8, $9 */
280 stl_p(p
++, 0x3c0a0000 | (cm_base
>> 16)); /* lui $10, cm_base >> 16 */
282 stl_p(p
++, 0xfd0a0008); /* sd $10, 0x8($8) */
284 stl_p(p
++, 0xad0a0008); /* sw $10, 0x8($8) */
286 stl_p(p
++, 0x012a4025); /* or $8, $10 */
288 /* Move & enable GIC GCRs */
289 stl_p(p
++, 0x3c090000 | (gic_base
>> 16)); /* lui $9, gic_base >> 16 */
290 stl_p(p
++, 0x35290001); /* ori $9, 0x1 */
292 stl_p(p
++, 0xfd090080); /* sd $9, 0x80($8) */
294 stl_p(p
++, 0xad090080); /* sw $9, 0x80($8) */
297 /* Move & enable CPC GCRs */
298 stl_p(p
++, 0x3c090000 | (cpc_base
>> 16)); /* lui $9, cpc_base >> 16 */
299 stl_p(p
++, 0x35290001); /* ori $9, 0x1 */
301 stl_p(p
++, 0xfd090088); /* sd $9, 0x88($8) */
303 stl_p(p
++, 0xad090088); /* sw $9, 0x88($8) */
307 * Setup argument registers to follow the UHI boot protocol:
310 * a1/$5 = virtual address of FDT
314 stl_p(p
++, 0x2404fffe); /* li $4, -2 */
315 /* lui $5, hi(fdt_addr) */
316 stl_p(p
++, 0x3c050000 | ((fdt_addr
>> 16) & 0xffff));
317 if (fdt_addr
& 0xffff) { /* ori $5, lo(fdt_addr) */
318 stl_p(p
++, 0x34a50000 | (fdt_addr
& 0xffff));
320 stl_p(p
++, 0x34060000); /* li $6, 0 */
321 stl_p(p
++, 0x34070000); /* li $7, 0 */
323 /* Load kernel entry address & jump to it */
324 /* lui $25, hi(kernel_entry) */
325 stl_p(p
++, 0x3c190000 | ((kernel_entry
>> 16) & 0xffff));
326 /* ori $25, lo(kernel_entry) */
327 stl_p(p
++, 0x37390000 | (kernel_entry
& 0xffff));
328 stl_p(p
++, 0x03200009); /* jr $25 */
331 static const void *boston_fdt_filter(void *opaque
, const void *fdt_orig
,
332 const void *match_data
, hwaddr
*load_addr
)
334 BostonState
*s
= BOSTON(opaque
);
335 MachineState
*machine
= s
->mach
;
339 size_t fdt_sz
, ram_low_sz
, ram_high_sz
;
341 fdt_sz
= fdt_totalsize(fdt_orig
) * 2;
342 fdt
= g_malloc0(fdt_sz
);
344 err
= fdt_open_into(fdt_orig
, fdt
, fdt_sz
);
346 fprintf(stderr
, "unable to open FDT\n");
350 cmdline
= (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0])
351 ? machine
->kernel_cmdline
: " ";
352 err
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs", cmdline
);
354 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
358 ram_low_sz
= MIN(256 * MiB
, machine
->ram_size
);
359 ram_high_sz
= machine
->ram_size
- ram_low_sz
;
360 qemu_fdt_setprop_sized_cells(fdt
, "/memory@0", "reg",
361 1, 0x00000000, 1, ram_low_sz
,
362 1, 0x90000000, 1, ram_high_sz
);
364 fdt
= g_realloc(fdt
, fdt_totalsize(fdt
));
365 qemu_fdt_dumpdtb(fdt
, fdt_sz
);
367 s
->fdt_base
= *load_addr
;
372 static const void *boston_kernel_filter(void *opaque
, const void *kernel
,
373 hwaddr
*load_addr
, hwaddr
*entry_addr
)
375 BostonState
*s
= BOSTON(opaque
);
377 s
->kernel_entry
= *entry_addr
;
382 static const struct fit_loader_match boston_matches
[] = {
387 static const struct fit_loader boston_fit_loader
= {
388 .matches
= boston_matches
,
389 .addr_to_phys
= cpu_mips_kseg0_to_phys
,
390 .fdt_filter
= boston_fdt_filter
,
391 .kernel_filter
= boston_kernel_filter
,
394 static inline XilinxPCIEHost
*
395 xilinx_pcie_init(MemoryRegion
*sys_mem
, uint32_t bus_nr
,
396 hwaddr cfg_base
, uint64_t cfg_size
,
397 hwaddr mmio_base
, uint64_t mmio_size
,
398 qemu_irq irq
, bool link_up
)
401 MemoryRegion
*cfg
, *mmio
;
403 dev
= qdev_create(NULL
, TYPE_XILINX_PCIE_HOST
);
405 qdev_prop_set_uint32(dev
, "bus_nr", bus_nr
);
406 qdev_prop_set_uint64(dev
, "cfg_base", cfg_base
);
407 qdev_prop_set_uint64(dev
, "cfg_size", cfg_size
);
408 qdev_prop_set_uint64(dev
, "mmio_base", mmio_base
);
409 qdev_prop_set_uint64(dev
, "mmio_size", mmio_size
);
410 qdev_prop_set_bit(dev
, "link_up", link_up
);
412 qdev_init_nofail(dev
);
414 cfg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
415 memory_region_add_subregion_overlap(sys_mem
, cfg_base
, cfg
, 0);
417 mmio
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
418 memory_region_add_subregion_overlap(sys_mem
, 0, mmio
, 0);
420 qdev_connect_gpio_out_named(dev
, "interrupt_out", 0, irq
);
422 return XILINX_PCIE_HOST(dev
);
425 static void boston_mach_init(MachineState
*machine
)
430 MemoryRegion
*flash
, *ddr_low_alias
, *lcd
, *platreg
;
431 MemoryRegion
*sys_mem
= get_system_memory();
432 XilinxPCIEHost
*pcie2
;
436 int fw_size
, fit_err
;
439 if ((machine
->ram_size
% GiB
) ||
440 (machine
->ram_size
> (2 * GiB
))) {
441 error_report("Memory size must be 1GB or 2GB");
445 dev
= qdev_create(NULL
, TYPE_MIPS_BOSTON
);
446 qdev_init_nofail(dev
);
451 if (!cpu_supports_cps_smp(machine
->cpu_type
)) {
452 error_report("Boston requires CPUs which support CPS");
456 is_64b
= cpu_supports_isa(machine
->cpu_type
, ISA_MIPS64
);
458 sysbus_init_child_obj(OBJECT(machine
), "cps", OBJECT(&s
->cps
),
459 sizeof(s
->cps
), TYPE_MIPS_CPS
);
460 object_property_set_str(OBJECT(&s
->cps
), machine
->cpu_type
, "cpu-type",
462 object_property_set_int(OBJECT(&s
->cps
), machine
->smp
.cpus
, "num-vp", &err
);
463 object_property_set_bool(OBJECT(&s
->cps
), true, "realized", &err
);
466 error_report("%s", error_get_pretty(err
));
470 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s
->cps
), 0, 0, 1);
472 flash
= g_new(MemoryRegion
, 1);
473 memory_region_init_rom(flash
, NULL
, "boston.flash", 128 * MiB
, &err
);
474 memory_region_add_subregion_overlap(sys_mem
, 0x18000000, flash
, 0);
476 memory_region_add_subregion_overlap(sys_mem
, 0x80000000, machine
->ram
, 0);
478 ddr_low_alias
= g_new(MemoryRegion
, 1);
479 memory_region_init_alias(ddr_low_alias
, NULL
, "boston_low.ddr",
481 MIN(machine
->ram_size
, (256 * MiB
)));
482 memory_region_add_subregion_overlap(sys_mem
, 0, ddr_low_alias
, 0);
484 xilinx_pcie_init(sys_mem
, 0,
485 0x10000000, 32 * MiB
,
487 get_cps_irq(&s
->cps
, 2), false);
489 xilinx_pcie_init(sys_mem
, 1,
490 0x12000000, 32 * MiB
,
491 0x20000000, 512 * MiB
,
492 get_cps_irq(&s
->cps
, 1), false);
494 pcie2
= xilinx_pcie_init(sys_mem
, 2,
495 0x14000000, 32 * MiB
,
497 get_cps_irq(&s
->cps
, 0), true);
499 platreg
= g_new(MemoryRegion
, 1);
500 memory_region_init_io(platreg
, NULL
, &boston_platreg_ops
, s
,
501 "boston-platregs", 0x1000);
502 memory_region_add_subregion_overlap(sys_mem
, 0x17ffd000, platreg
, 0);
504 s
->uart
= serial_mm_init(sys_mem
, 0x17ffe000, 2,
505 get_cps_irq(&s
->cps
, 3), 10000000,
506 serial_hd(0), DEVICE_NATIVE_ENDIAN
);
508 lcd
= g_new(MemoryRegion
, 1);
509 memory_region_init_io(lcd
, NULL
, &boston_lcd_ops
, s
, "boston-lcd", 0x8);
510 memory_region_add_subregion_overlap(sys_mem
, 0x17fff000, lcd
, 0);
512 chr
= qemu_chr_new("lcd", "vc:320x240", NULL
);
513 qemu_chr_fe_init(&s
->lcd_display
, chr
, NULL
);
514 qemu_chr_fe_set_handlers(&s
->lcd_display
, NULL
, NULL
,
515 boston_lcd_event
, NULL
, s
, NULL
, true);
517 ahci
= pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2
->root
)->sec_bus
,
519 true, TYPE_ICH9_AHCI
);
520 g_assert(ARRAY_SIZE(hd
) == ahci_get_num_ports(ahci
));
521 ide_drive_get(hd
, ahci_get_num_ports(ahci
));
522 ahci_ide_create_devs(ahci
, hd
);
524 if (machine
->firmware
) {
525 fw_size
= load_image_targphys(machine
->firmware
,
526 0x1fc00000, 4 * MiB
);
528 error_report("unable to load firmware image '%s'",
532 } else if (machine
->kernel_filename
) {
533 fit_err
= load_fit(&boston_fit_loader
, machine
->kernel_filename
, s
);
535 error_report("unable to load FIT image");
539 gen_firmware(memory_region_get_ram_ptr(flash
) + 0x7c00000,
540 s
->kernel_entry
, s
->fdt_base
, is_64b
);
541 } else if (!qtest_enabled()) {
542 error_report("Please provide either a -kernel or -bios argument");
547 static void boston_mach_class_init(MachineClass
*mc
)
549 mc
->desc
= "MIPS Boston";
550 mc
->init
= boston_mach_init
;
551 mc
->block_default_type
= IF_IDE
;
552 mc
->default_ram_size
= 1 * GiB
;
553 mc
->default_ram_id
= "boston.ddr";
555 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("I6400");
558 DEFINE_MACHINE("boston", boston_mach_class_init
)