2 * Xilinx Zynq Baseboard System emulation.
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
22 #include "hw/sysbus.h"
23 #include "hw/arm/boot.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/boards.h"
28 #include "hw/block/flash.h"
29 #include "hw/loader.h"
30 #include "hw/misc/zynq-xadc.h"
31 #include "hw/ssi/ssi.h"
32 #include "hw/usb/chipidea.h"
33 #include "qemu/error-report.h"
34 #include "hw/sd/sdhci.h"
35 #include "hw/char/cadence_uart.h"
36 #include "hw/net/cadence_gem.h"
37 #include "hw/cpu/a9mpcore.h"
38 #include "hw/qdev-clock.h"
39 #include "sysemu/reset.h"
41 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
42 #define ZYNQ_MACHINE(obj) \
43 OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)
45 /* board base frequency: 33.333333 MHz */
46 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
48 #define NUM_SPI_FLASHES 4
49 #define NUM_QSPI_FLASHES 2
50 #define NUM_QSPI_BUSSES 2
52 #define FLASH_SIZE (64 * 1024 * 1024)
53 #define FLASH_SECTOR_SIZE (128 * 1024)
55 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
57 #define MPCORE_PERIPHBASE 0xF8F00000
58 #define ZYNQ_BOARD_MIDR 0x413FC090
60 static const int dma_irqs
[8] = {
61 46, 47, 48, 49, 72, 73, 74, 75
64 #define BOARD_SETUP_ADDR 0x100
66 #define SLCR_LOCK_OFFSET 0x004
67 #define SLCR_UNLOCK_OFFSET 0x008
68 #define SLCR_ARM_PLL_OFFSET 0x100
70 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
71 #define SLCR_XILINX_LOCK_KEY 0x767b
73 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
75 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
76 extract32((x), 12, 4) << 16)
78 /* Write immediate val to address r0 + addr. r0 should contain base offset
79 * of the SLCR block. Clobbers r1.
82 #define SLCR_WRITE(addr, val) \
83 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
84 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
87 typedef struct ZynqMachineState
{
92 static void zynq_write_board_setup(ARMCPU
*cpu
,
93 const struct arm_boot_info
*info
)
96 uint32_t board_setup_blob
[] = {
97 0xe3a004f8, /* mov r0, #0xf8000000 */
98 SLCR_WRITE(SLCR_UNLOCK_OFFSET
, SLCR_XILINX_UNLOCK_KEY
),
99 SLCR_WRITE(SLCR_ARM_PLL_OFFSET
, 0x00014008),
100 SLCR_WRITE(SLCR_LOCK_OFFSET
, SLCR_XILINX_LOCK_KEY
),
101 0xe12fff1e, /* bx lr */
103 for (n
= 0; n
< ARRAY_SIZE(board_setup_blob
); n
++) {
104 board_setup_blob
[n
] = tswap32(board_setup_blob
[n
]);
106 rom_add_blob_fixed("board-setup", board_setup_blob
,
107 sizeof(board_setup_blob
), BOARD_SETUP_ADDR
);
110 static struct arm_boot_info zynq_binfo
= {};
112 static void gem_init(NICInfo
*nd
, uint32_t base
, qemu_irq irq
)
117 dev
= qdev_create(NULL
, TYPE_CADENCE_GEM
);
119 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
120 qdev_set_nic_properties(dev
, nd
);
122 qdev_init_nofail(dev
);
123 s
= SYS_BUS_DEVICE(dev
);
124 sysbus_mmio_map(s
, 0, base
);
125 sysbus_connect_irq(s
, 0, irq
);
128 static inline void zynq_init_spi_flashes(uint32_t base_addr
, qemu_irq irq
,
132 SysBusDevice
*busdev
;
134 DeviceState
*flash_dev
;
136 int num_busses
= is_qspi
? NUM_QSPI_BUSSES
: 1;
137 int num_ss
= is_qspi
? NUM_QSPI_FLASHES
: NUM_SPI_FLASHES
;
139 dev
= qdev_create(NULL
, is_qspi
? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
140 qdev_prop_set_uint8(dev
, "num-txrx-bytes", is_qspi
? 4 : 1);
141 qdev_prop_set_uint8(dev
, "num-ss-bits", num_ss
);
142 qdev_prop_set_uint8(dev
, "num-busses", num_busses
);
143 qdev_init_nofail(dev
);
144 busdev
= SYS_BUS_DEVICE(dev
);
145 sysbus_mmio_map(busdev
, 0, base_addr
);
147 sysbus_mmio_map(busdev
, 1, 0xFC000000);
149 sysbus_connect_irq(busdev
, 0, irq
);
151 for (i
= 0; i
< num_busses
; ++i
) {
155 snprintf(bus_name
, 16, "spi%d", i
);
156 spi
= (SSIBus
*)qdev_get_child_bus(dev
, bus_name
);
158 for (j
= 0; j
< num_ss
; ++j
) {
159 DriveInfo
*dinfo
= drive_get_next(IF_MTD
);
160 flash_dev
= ssi_create_slave_no_init(spi
, "n25q128");
162 qdev_prop_set_drive(flash_dev
, "drive",
163 blk_by_legacy_dinfo(dinfo
), &error_fatal
);
165 qdev_init_nofail(flash_dev
);
167 cs_line
= qdev_get_gpio_in_named(flash_dev
, SSI_GPIO_CS
, 0);
168 sysbus_connect_irq(busdev
, i
* num_ss
+ j
+ 1, cs_line
);
174 static void zynq_init(MachineState
*machine
)
176 ZynqMachineState
*zynq_machine
= ZYNQ_MACHINE(machine
);
178 MemoryRegion
*address_space_mem
= get_system_memory();
179 MemoryRegion
*ocm_ram
= g_new(MemoryRegion
, 1);
180 DeviceState
*dev
, *slcr
;
181 SysBusDevice
*busdev
;
186 if (machine
->ram_size
> 2 * GiB
) {
187 error_report("RAM size more than 2 GiB is not supported");
191 cpu
= ARM_CPU(object_new(machine
->cpu_type
));
193 /* By default A9 CPUs have EL3 enabled. This board does not
194 * currently support EL3 so the CPU EL3 property is disabled before
197 if (object_property_find(OBJECT(cpu
), "has_el3", NULL
)) {
198 object_property_set_bool(OBJECT(cpu
), false, "has_el3", &error_fatal
);
201 object_property_set_int(OBJECT(cpu
), ZYNQ_BOARD_MIDR
, "midr",
203 object_property_set_int(OBJECT(cpu
), MPCORE_PERIPHBASE
, "reset-cbar",
205 object_property_set_bool(OBJECT(cpu
), true, "realized", &error_fatal
);
207 /* DDR remapped to address zero. */
208 memory_region_add_subregion(address_space_mem
, 0, machine
->ram
);
210 /* 256K of on-chip memory */
211 memory_region_init_ram(ocm_ram
, NULL
, "zynq.ocm_ram", 256 * KiB
,
213 memory_region_add_subregion(address_space_mem
, 0xFFFC0000, ocm_ram
);
215 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
218 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE
,
219 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
220 FLASH_SECTOR_SIZE
, 1,
221 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
224 /* Create slcr, keep a pointer to connect clocks */
225 slcr
= qdev_create(NULL
, "xilinx,zynq_slcr");
226 qdev_init_nofail(slcr
);
227 sysbus_mmio_map(SYS_BUS_DEVICE(slcr
), 0, 0xF8000000);
229 /* Create the main clock source, and feed slcr with it */
230 zynq_machine
->ps_clk
= CLOCK(object_new(TYPE_CLOCK
));
231 object_property_add_child(OBJECT(zynq_machine
), "ps_clk",
232 OBJECT(zynq_machine
->ps_clk
));
233 object_unref(OBJECT(zynq_machine
->ps_clk
));
234 clock_set_hz(zynq_machine
->ps_clk
, PS_CLK_FREQUENCY
);
235 qdev_connect_clock_in(slcr
, "ps_clk", zynq_machine
->ps_clk
);
237 dev
= qdev_create(NULL
, TYPE_A9MPCORE_PRIV
);
238 qdev_prop_set_uint32(dev
, "num-cpu", 1);
239 qdev_init_nofail(dev
);
240 busdev
= SYS_BUS_DEVICE(dev
);
241 sysbus_mmio_map(busdev
, 0, MPCORE_PERIPHBASE
);
242 sysbus_connect_irq(busdev
, 0,
243 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
));
245 for (n
= 0; n
< 64; n
++) {
246 pic
[n
] = qdev_get_gpio_in(dev
, n
);
249 zynq_init_spi_flashes(0xE0006000, pic
[58-IRQ_OFFSET
], false);
250 zynq_init_spi_flashes(0xE0007000, pic
[81-IRQ_OFFSET
], false);
251 zynq_init_spi_flashes(0xE000D000, pic
[51-IRQ_OFFSET
], true);
253 sysbus_create_simple(TYPE_CHIPIDEA
, 0xE0002000, pic
[53 - IRQ_OFFSET
]);
254 sysbus_create_simple(TYPE_CHIPIDEA
, 0xE0003000, pic
[76 - IRQ_OFFSET
]);
256 dev
= cadence_uart_create(0xE0000000, pic
[59 - IRQ_OFFSET
], serial_hd(0));
257 qdev_connect_clock_in(dev
, "refclk",
258 qdev_get_clock_out(slcr
, "uart0_ref_clk"));
259 dev
= cadence_uart_create(0xE0001000, pic
[82 - IRQ_OFFSET
], serial_hd(1));
260 qdev_connect_clock_in(dev
, "refclk",
261 qdev_get_clock_out(slcr
, "uart1_ref_clk"));
263 sysbus_create_varargs("cadence_ttc", 0xF8001000,
264 pic
[42-IRQ_OFFSET
], pic
[43-IRQ_OFFSET
], pic
[44-IRQ_OFFSET
], NULL
);
265 sysbus_create_varargs("cadence_ttc", 0xF8002000,
266 pic
[69-IRQ_OFFSET
], pic
[70-IRQ_OFFSET
], pic
[71-IRQ_OFFSET
], NULL
);
268 gem_init(&nd_table
[0], 0xE000B000, pic
[54-IRQ_OFFSET
]);
269 gem_init(&nd_table
[1], 0xE000C000, pic
[77-IRQ_OFFSET
]);
271 for (n
= 0; n
< 2; n
++) {
272 int hci_irq
= n
? 79 : 56;
273 hwaddr hci_addr
= n
? 0xE0101000 : 0xE0100000;
276 DeviceState
*carddev
;
279 * - SD Host Controller Specification Version 2.0 Part A2
280 * - SDIO Specification Version 2.0
281 * - MMC Specification Version 3.31
283 dev
= qdev_create(NULL
, TYPE_SYSBUS_SDHCI
);
284 qdev_prop_set_uint8(dev
, "sd-spec-version", 2);
285 qdev_prop_set_uint64(dev
, "capareg", ZYNQ_SDHCI_CAPABILITIES
);
286 qdev_init_nofail(dev
);
287 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, hci_addr
);
288 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[hci_irq
- IRQ_OFFSET
]);
290 di
= drive_get_next(IF_SD
);
291 blk
= di
? blk_by_legacy_dinfo(di
) : NULL
;
292 carddev
= qdev_create(qdev_get_child_bus(dev
, "sd-bus"), TYPE_SD_CARD
);
293 qdev_prop_set_drive(carddev
, "drive", blk
, &error_fatal
);
294 object_property_set_bool(OBJECT(carddev
), true, "realized",
298 dev
= qdev_create(NULL
, TYPE_ZYNQ_XADC
);
299 qdev_init_nofail(dev
);
300 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xF8007100);
301 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[39-IRQ_OFFSET
]);
303 dev
= qdev_create(NULL
, "pl330");
304 qdev_prop_set_uint8(dev
, "num_chnls", 8);
305 qdev_prop_set_uint8(dev
, "num_periph_req", 4);
306 qdev_prop_set_uint8(dev
, "num_events", 16);
308 qdev_prop_set_uint8(dev
, "data_width", 64);
309 qdev_prop_set_uint8(dev
, "wr_cap", 8);
310 qdev_prop_set_uint8(dev
, "wr_q_dep", 16);
311 qdev_prop_set_uint8(dev
, "rd_cap", 8);
312 qdev_prop_set_uint8(dev
, "rd_q_dep", 16);
313 qdev_prop_set_uint16(dev
, "data_buffer_dep", 256);
315 qdev_init_nofail(dev
);
316 busdev
= SYS_BUS_DEVICE(dev
);
317 sysbus_mmio_map(busdev
, 0, 0xF8003000);
318 sysbus_connect_irq(busdev
, 0, pic
[45-IRQ_OFFSET
]); /* abort irq line */
319 for (n
= 0; n
< ARRAY_SIZE(dma_irqs
); ++n
) { /* event irqs */
320 sysbus_connect_irq(busdev
, n
+ 1, pic
[dma_irqs
[n
] - IRQ_OFFSET
]);
323 dev
= qdev_create(NULL
, "xlnx.ps7-dev-cfg");
324 qdev_init_nofail(dev
);
325 busdev
= SYS_BUS_DEVICE(dev
);
326 sysbus_connect_irq(busdev
, 0, pic
[40 - IRQ_OFFSET
]);
327 sysbus_mmio_map(busdev
, 0, 0xF8007000);
329 zynq_binfo
.ram_size
= machine
->ram_size
;
330 zynq_binfo
.nb_cpus
= 1;
331 zynq_binfo
.board_id
= 0xd32;
332 zynq_binfo
.loader_start
= 0;
333 zynq_binfo
.board_setup_addr
= BOARD_SETUP_ADDR
;
334 zynq_binfo
.write_board_setup
= zynq_write_board_setup
;
336 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &zynq_binfo
);
339 static void zynq_machine_class_init(ObjectClass
*oc
, void *data
)
341 MachineClass
*mc
= MACHINE_CLASS(oc
);
342 mc
->desc
= "Xilinx Zynq Platform Baseboard for Cortex-A9";
343 mc
->init
= zynq_init
;
346 mc
->ignore_memory_transaction_failures
= true;
347 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a9");
348 mc
->default_ram_id
= "zynq.ext_ram";
351 static const TypeInfo zynq_machine_type
= {
352 .name
= TYPE_ZYNQ_MACHINE
,
353 .parent
= TYPE_MACHINE
,
354 .class_init
= zynq_machine_class_init
,
355 .instance_size
= sizeof(ZynqMachineState
),
358 static void zynq_machine_register_types(void)
360 type_register_static(&zynq_machine_type
);
363 type_init(zynq_machine_register_types
)