2 * ARM V2M MPS2 board emulation.
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * We model the following FPGA images:
17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
18 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
20 * Links to the TRM for the board itself and to the various Application
21 * Notes which document the FPGA images can be found here:
22 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/cutils.h"
28 #include "qapi/error.h"
29 #include "qemu/error-report.h"
30 #include "hw/arm/boot.h"
31 #include "hw/arm/armv7m.h"
32 #include "hw/or-irq.h"
33 #include "hw/boards.h"
34 #include "exec/address-spaces.h"
35 #include "sysemu/sysemu.h"
36 #include "hw/misc/unimp.h"
37 #include "hw/char/cmsdk-apb-uart.h"
38 #include "hw/timer/cmsdk-apb-timer.h"
39 #include "hw/timer/cmsdk-apb-dualtimer.h"
40 #include "hw/misc/mps2-scc.h"
41 #include "hw/net/lan9118.h"
44 typedef enum MPS2FPGAType
{
51 MPS2FPGAType fpga_type
;
60 MemoryRegion ssram1_m
;
62 MemoryRegion ssram23_m
;
63 MemoryRegion blockram
;
64 MemoryRegion blockram_m1
;
65 MemoryRegion blockram_m2
;
66 MemoryRegion blockram_m3
;
69 CMSDKAPBDualTimer dualtimer
;
72 #define TYPE_MPS2_MACHINE "mps2"
73 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
74 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
76 #define MPS2_MACHINE(obj) \
77 OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
78 #define MPS2_MACHINE_GET_CLASS(obj) \
79 OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
80 #define MPS2_MACHINE_CLASS(klass) \
81 OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
83 /* Main SYSCLK frequency in Hz */
84 #define SYSCLK_FRQ 25000000
86 /* Initialize the auxiliary RAM region @mr and map it into
87 * the memory map at @base.
89 static void make_ram(MemoryRegion
*mr
, const char *name
,
90 hwaddr base
, hwaddr size
)
92 memory_region_init_ram(mr
, NULL
, name
, size
, &error_fatal
);
93 memory_region_add_subregion(get_system_memory(), base
, mr
);
96 /* Create an alias of an entire original MemoryRegion @orig
97 * located at @base in the memory map.
99 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
100 MemoryRegion
*orig
, hwaddr base
)
102 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
103 memory_region_size(orig
));
104 memory_region_add_subregion(get_system_memory(), base
, mr
);
107 static void mps2_common_init(MachineState
*machine
)
109 MPS2MachineState
*mms
= MPS2_MACHINE(machine
);
110 MPS2MachineClass
*mmc
= MPS2_MACHINE_GET_CLASS(machine
);
111 MemoryRegion
*system_memory
= get_system_memory();
112 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
113 DeviceState
*armv7m
, *sccdev
;
115 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
116 error_report("This board can only be used with CPU %s",
117 mc
->default_cpu_type
);
121 if (machine
->ram_size
!= mc
->default_ram_size
) {
122 char *sz
= size_to_str(mc
->default_ram_size
);
123 error_report("Invalid RAM size, should be %s", sz
);
128 /* The FPGA images have an odd combination of different RAMs,
129 * because in hardware they are different implementations and
130 * connected to different buses, giving varying performance/size
131 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
132 * call the 16MB our "system memory", as it's the largest lump.
134 * Common to both boards:
135 * 0x21000000..0x21ffffff : PSRAM (16MB)
137 * 0x00000000 .. 0x003fffff : ZBT SSRAM1
138 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
139 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
140 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
141 * 0x01000000 .. 0x01003fff : block RAM (16K)
142 * 0x01004000 .. 0x01007fff : mirror of above
143 * 0x01008000 .. 0x0100bfff : mirror of above
144 * 0x0100c000 .. 0x0100ffff : mirror of above
146 * 0x00000000 .. 0x0003ffff : FPGA block RAM
147 * 0x00400000 .. 0x007fffff : ZBT SSRAM1
148 * 0x20000000 .. 0x2001ffff : SRAM
149 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
151 * The AN385 has a feature where the lowest 16K can be mapped
152 * either to the bottom of the ZBT SSRAM1 or to the block RAM.
153 * This is of no use for QEMU so we don't implement it (as if
154 * zbt_boot_ctrl is always zero).
156 memory_region_add_subregion(system_memory
, 0x21000000, machine
->ram
);
158 switch (mmc
->fpga_type
) {
160 make_ram(&mms
->ssram1
, "mps.ssram1", 0x0, 0x400000);
161 make_ram_alias(&mms
->ssram1_m
, "mps.ssram1_m", &mms
->ssram1
, 0x400000);
162 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20000000, 0x400000);
163 make_ram_alias(&mms
->ssram23_m
, "mps.ssram23_m",
164 &mms
->ssram23
, 0x20400000);
165 make_ram(&mms
->blockram
, "mps.blockram", 0x01000000, 0x4000);
166 make_ram_alias(&mms
->blockram_m1
, "mps.blockram_m1",
167 &mms
->blockram
, 0x01004000);
168 make_ram_alias(&mms
->blockram_m2
, "mps.blockram_m2",
169 &mms
->blockram
, 0x01008000);
170 make_ram_alias(&mms
->blockram_m3
, "mps.blockram_m3",
171 &mms
->blockram
, 0x0100c000);
174 make_ram(&mms
->blockram
, "mps.blockram", 0x0, 0x40000);
175 make_ram(&mms
->ssram1
, "mps.ssram1", 0x00400000, 0x00800000);
176 make_ram(&mms
->sram
, "mps.sram", 0x20000000, 0x20000);
177 make_ram(&mms
->ssram23
, "mps.ssram23", 0x20400000, 0x400000);
180 g_assert_not_reached();
183 sysbus_init_child_obj(OBJECT(mms
), "armv7m", &mms
->armv7m
,
184 sizeof(mms
->armv7m
), TYPE_ARMV7M
);
185 armv7m
= DEVICE(&mms
->armv7m
);
186 switch (mmc
->fpga_type
) {
188 qdev_prop_set_uint32(armv7m
, "num-irq", 32);
191 qdev_prop_set_uint32(armv7m
, "num-irq", 64);
194 g_assert_not_reached();
196 qdev_prop_set_string(armv7m
, "cpu-type", machine
->cpu_type
);
197 qdev_prop_set_bit(armv7m
, "enable-bitband", true);
198 object_property_set_link(OBJECT(&mms
->armv7m
), OBJECT(system_memory
),
199 "memory", &error_abort
);
200 object_property_set_bool(OBJECT(&mms
->armv7m
), true, "realized",
203 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
204 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
205 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
206 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
207 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
208 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
209 /* These three ranges all cover multiple devices; we may implement
210 * some of them below (in which case the real device takes precedence
211 * over the unimplemented-region mapping).
213 create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
214 0x40000000, 0x00010000);
215 create_unimplemented_device("CMSDK peripheral region @0x40010000",
216 0x40010000, 0x00010000);
217 create_unimplemented_device("Extra peripheral region @0x40020000",
218 0x40020000, 0x00010000);
219 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
220 create_unimplemented_device("VGA", 0x41000000, 0x0200000);
222 switch (mmc
->fpga_type
) {
225 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
226 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
229 DeviceState
*orgate_dev
;
232 orgate
= object_new(TYPE_OR_IRQ
);
233 object_property_set_int(orgate
, 6, "num-lines", &error_fatal
);
234 object_property_set_bool(orgate
, true, "realized", &error_fatal
);
235 orgate_dev
= DEVICE(orgate
);
236 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
238 for (i
= 0; i
< 5; i
++) {
239 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
240 0x40006000, 0x40007000,
242 /* RX irq number; TX irq is always one greater */
243 static const int uartirq
[] = {0, 2, 4, 18, 20};
244 qemu_irq txovrint
= NULL
, rxovrint
= NULL
;
247 txovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2);
248 rxovrint
= qdev_get_gpio_in(orgate_dev
, i
* 2 + 1);
251 cmsdk_apb_uart_create(uartbase
[i
],
252 qdev_get_gpio_in(armv7m
, uartirq
[i
] + 1),
253 qdev_get_gpio_in(armv7m
, uartirq
[i
]),
256 serial_hd(i
), SYSCLK_FRQ
);
262 /* The overflow IRQs for all UARTs are ORed together.
263 * Tx and Rx IRQs for each UART are ORed together.
266 DeviceState
*orgate_dev
;
269 orgate
= object_new(TYPE_OR_IRQ
);
270 object_property_set_int(orgate
, 10, "num-lines", &error_fatal
);
271 object_property_set_bool(orgate
, true, "realized", &error_fatal
);
272 orgate_dev
= DEVICE(orgate
);
273 qdev_connect_gpio_out(orgate_dev
, 0, qdev_get_gpio_in(armv7m
, 12));
275 for (i
= 0; i
< 5; i
++) {
276 /* system irq numbers for the combined tx/rx for each UART */
277 static const int uart_txrx_irqno
[] = {0, 2, 45, 46, 56};
278 static const hwaddr uartbase
[] = {0x40004000, 0x40005000,
279 0x4002c000, 0x4002d000,
282 DeviceState
*txrx_orgate_dev
;
284 txrx_orgate
= object_new(TYPE_OR_IRQ
);
285 object_property_set_int(txrx_orgate
, 2, "num-lines", &error_fatal
);
286 object_property_set_bool(txrx_orgate
, true, "realized",
288 txrx_orgate_dev
= DEVICE(txrx_orgate
);
289 qdev_connect_gpio_out(txrx_orgate_dev
, 0,
290 qdev_get_gpio_in(armv7m
, uart_txrx_irqno
[i
]));
291 cmsdk_apb_uart_create(uartbase
[i
],
292 qdev_get_gpio_in(txrx_orgate_dev
, 0),
293 qdev_get_gpio_in(txrx_orgate_dev
, 1),
294 qdev_get_gpio_in(orgate_dev
, i
* 2),
295 qdev_get_gpio_in(orgate_dev
, i
* 2 + 1),
297 serial_hd(i
), SYSCLK_FRQ
);
302 g_assert_not_reached();
305 cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m
, 8), SYSCLK_FRQ
);
306 cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m
, 9), SYSCLK_FRQ
);
308 sysbus_init_child_obj(OBJECT(mms
), "dualtimer", &mms
->dualtimer
,
309 sizeof(mms
->dualtimer
), TYPE_CMSDK_APB_DUALTIMER
);
310 qdev_prop_set_uint32(DEVICE(&mms
->dualtimer
), "pclk-frq", SYSCLK_FRQ
);
311 object_property_set_bool(OBJECT(&mms
->dualtimer
), true, "realized",
313 sysbus_connect_irq(SYS_BUS_DEVICE(&mms
->dualtimer
), 0,
314 qdev_get_gpio_in(armv7m
, 10));
315 sysbus_mmio_map(SYS_BUS_DEVICE(&mms
->dualtimer
), 0, 0x40002000);
317 sysbus_init_child_obj(OBJECT(mms
), "scc", &mms
->scc
,
318 sizeof(mms
->scc
), TYPE_MPS2_SCC
);
319 sccdev
= DEVICE(&mms
->scc
);
320 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
321 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
322 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
323 object_property_set_bool(OBJECT(&mms
->scc
), true, "realized",
325 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev
), 0, 0x4002f000);
327 /* In hardware this is a LAN9220; the LAN9118 is software compatible
328 * except that it doesn't support the checksum-offload feature.
330 lan9118_init(&nd_table
[0], 0x40200000,
331 qdev_get_gpio_in(armv7m
,
332 mmc
->fpga_type
== FPGA_AN385
? 13 : 47));
334 system_clock_scale
= NANOSECONDS_PER_SECOND
/ SYSCLK_FRQ
;
336 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
340 static void mps2_class_init(ObjectClass
*oc
, void *data
)
342 MachineClass
*mc
= MACHINE_CLASS(oc
);
344 mc
->init
= mps2_common_init
;
346 mc
->default_ram_size
= 16 * MiB
;
347 mc
->default_ram_id
= "mps.ram";
350 static void mps2_an385_class_init(ObjectClass
*oc
, void *data
)
352 MachineClass
*mc
= MACHINE_CLASS(oc
);
353 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
355 mc
->desc
= "ARM MPS2 with AN385 FPGA image for Cortex-M3";
356 mmc
->fpga_type
= FPGA_AN385
;
357 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
358 mmc
->scc_id
= 0x41043850;
361 static void mps2_an511_class_init(ObjectClass
*oc
, void *data
)
363 MachineClass
*mc
= MACHINE_CLASS(oc
);
364 MPS2MachineClass
*mmc
= MPS2_MACHINE_CLASS(oc
);
366 mc
->desc
= "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
367 mmc
->fpga_type
= FPGA_AN511
;
368 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m3");
369 mmc
->scc_id
= 0x41045110;
372 static const TypeInfo mps2_info
= {
373 .name
= TYPE_MPS2_MACHINE
,
374 .parent
= TYPE_MACHINE
,
376 .instance_size
= sizeof(MPS2MachineState
),
377 .class_size
= sizeof(MPS2MachineClass
),
378 .class_init
= mps2_class_init
,
381 static const TypeInfo mps2_an385_info
= {
382 .name
= TYPE_MPS2_AN385_MACHINE
,
383 .parent
= TYPE_MPS2_MACHINE
,
384 .class_init
= mps2_an385_class_init
,
387 static const TypeInfo mps2_an511_info
= {
388 .name
= TYPE_MPS2_AN511_MACHINE
,
389 .parent
= TYPE_MPS2_MACHINE
,
390 .class_init
= mps2_an511_class_init
,
393 static void mps2_machine_init(void)
395 type_register_static(&mps2_info
);
396 type_register_static(&mps2_an385_info
);
397 type_register_static(&mps2_an511_info
);
400 type_init(mps2_machine_init
);