target/riscv/cpu-qom.h

   1 /*
   2  * QEMU RISC-V CPU QOM header
   3  *
   4  * Copyright (c) 2023 Ventana Micro Systems Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef RISCV_CPU_QOM_H
  20 #define RISCV_CPU_QOM_H
  21
  22 #include "hw/core/cpu.h"
  23 #include "qom/object.h"
  24
  25 #define TYPE_RISCV_CPU "riscv-cpu"
  26 #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
  27
  28 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  29 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  30 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  31
  32 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  33 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  34 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  35 #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
  36 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
  37 #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
  38 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  39 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
  40 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  41 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  42 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  43 #define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
  44 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
  45 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
  46
  47 #if defined(TARGET_RISCV32)
  48 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
  49 #elif defined(TARGET_RISCV64)
  50 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  51 #endif
  52
  53 typedef struct CPUArchState CPURISCVState;
  54
  55 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
  56
  57 /**
  58  * RISCVCPUClass:
  59  * @parent_realize: The parent class' realize handler.
  60  * @parent_phases: The parent class' reset phase handlers.
  61  *
  62  * A RISCV CPU model.
  63  */
  64 struct RISCVCPUClass {
  65     /*< private >*/
  66     CPUClass parent_class;
  67     /*< public >*/
  68     DeviceRealize parent_realize;
  69     ResettablePhases parent_phases;
  70 };
  71 #endif /* RISCV_CPU_QOM_H */