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nbd/server: Add FLAG_PAYLOAD support to CMD_BLOCK_STATUS
[qemu/ericb.git] / hw / i386 / acpi-build.c
blobbb12b0ad4301ef47795c3a599cbad5a3b7853f0a
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/erst.h"
47 #include "hw/acpi/piix4.h"
48 #include "sysemu/tpm_backend.h"
49 #include "hw/rtc/mc146818rtc_regs.h"
50 #include "migration/vmstate.h"
51 #include "hw/mem/memory-device.h"
52 #include "hw/mem/nvdimm.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "hw/hyperv/vmbus-bridge.h"
56
57 /* Supported chipsets: */
58 #include "hw/southbridge/ich9.h"
59 #include "hw/southbridge/piix.h"
60 #include "hw/acpi/pcihp.h"
61 #include "hw/i386/fw_cfg.h"
62 #include "hw/i386/pc.h"
63 #include "hw/pci/pci_bus.h"
64 #include "hw/pci-host/i440fx.h"
65 #include "hw/pci-host/q35.h"
66 #include "hw/i386/x86-iommu.h"
67
68 #include "hw/acpi/aml-build.h"
69 #include "hw/acpi/utils.h"
70 #include "hw/acpi/pci.h"
71 #include "hw/acpi/cxl.h"
72
73 #include "qom/qom-qobject.h"
74 #include "hw/i386/amd_iommu.h"
75 #include "hw/i386/intel_iommu.h"
76 #include "hw/virtio/virtio-iommu.h"
77
78 #include "hw/acpi/hmat.h"
79 #include "hw/acpi/viot.h"
80
81 #include CONFIG_DEVICES
82
83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
85 * a little bit, there should be plenty of free space since the DSDT
86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
87 */
88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
89 #define ACPI_BUILD_ALIGN_SIZE 0x1000
90
91 #define ACPI_BUILD_TABLE_SIZE 0x20000
92
93 /* #define DEBUG_ACPI_BUILD */
94 #ifdef DEBUG_ACPI_BUILD
95 #define ACPI_BUILD_DPRINTF(fmt, ...) \
96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
97 #else
98 #define ACPI_BUILD_DPRINTF(fmt, ...)
99 #endif
100
101 typedef struct AcpiPmInfo {
102 bool s3_disabled;
103 bool s4_disabled;
104 bool pcihp_bridge_en;
105 bool smi_on_cpuhp;
106 bool smi_on_cpu_unplug;
107 bool pcihp_root_en;
108 uint8_t s4_val;
109 AcpiFadtData fadt;
110 uint16_t cpu_hp_io_base;
111 uint16_t pcihp_io_base;
112 uint16_t pcihp_io_len;
113 } AcpiPmInfo;
114
115 typedef struct AcpiMiscInfo {
116 bool has_hpet;
117 #ifdef CONFIG_TPM
118 TPMVersion tpm_version;
119 #endif
120 } AcpiMiscInfo;
121
122 typedef struct FwCfgTPMConfig {
123 uint32_t tpmppi_address;
124 uint8_t tpm_version;
125 uint8_t tpmppi_version;
126 } QEMU_PACKED FwCfgTPMConfig;
127
128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
129
130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
131 .space_id = AML_AS_SYSTEM_IO,
132 .address = NVDIMM_ACPI_IO_BASE,
133 .bit_width = NVDIMM_ACPI_IO_LEN << 3
134 };
135
136 static void init_common_fadt_data(MachineState *ms, Object *o,
137 AcpiFadtData *data)
138 {
139 X86MachineState *x86ms = X86_MACHINE(ms);
140 /*
141 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
142 * behavior for compatibility irrelevant to smm_enabled, which doesn't
143 * comforms to ACPI spec.
144 */
145 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
146 true : x86_machine_is_smm_enabled(x86ms);
147 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
148 AmlAddressSpace as = AML_AS_SYSTEM_IO;
149 AcpiFadtData fadt = {
150 .rev = 3,
151 .flags =
152 (1 << ACPI_FADT_F_WBINVD) |
153 (1 << ACPI_FADT_F_PROC_C1) |
154 (1 << ACPI_FADT_F_SLP_BUTTON) |
155 (1 << ACPI_FADT_F_RTC_S4) |
156 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
157 /* APIC destination mode ("Flat Logical") has an upper limit of 8
158 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
159 * used
160 */
161 ((ms->smp.max_cpus > 8) ?
162 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
163 .int_model = 1 /* Multiple APIC */,
164 .rtc_century = RTC_CENTURY,
165 .plvl2_lat = 0xfff /* C2 state not supported */,
166 .plvl3_lat = 0xfff /* C3 state not supported */,
167 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
168 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
169 .acpi_enable_cmd =
170 smm_enabled ?
171 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
172 0,
173 .acpi_disable_cmd =
174 smm_enabled ?
175 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
176 0,
177 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
178 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
179 .address = io + 0x04 },
180 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
181 .gpe0_blk = { .space_id = as, .bit_width =
182 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
183 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
184 },
185 };
186
187 /*
188 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
189 * Flags, bit offset 1 - 8042.
190 */
191 fadt.iapc_boot_arch = iapc_boot_arch_8042();
192
193 *data = fadt;
194 }
195
196 static Object *object_resolve_type_unambiguous(const char *typename)
197 {
198 bool ambig;
199 Object *o = object_resolve_path_type("", typename, &ambig);
200
201 if (ambig || !o) {
202 return NULL;
203 }
204 return o;
205 }
206
207 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
208 {
209 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
210 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
211 Object *obj = piix ? piix : lpc;
212 QObject *o;
213 pm->cpu_hp_io_base = 0;
214 pm->pcihp_io_base = 0;
215 pm->pcihp_io_len = 0;
216 pm->smi_on_cpuhp = false;
217 pm->smi_on_cpu_unplug = false;
218
219 assert(obj);
220 init_common_fadt_data(machine, obj, &pm->fadt);
221 if (piix) {
222 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
223 pm->fadt.rev = 1;
224 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
225 }
226 if (lpc) {
227 uint64_t smi_features = object_property_get_uint(lpc,
228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
231 pm->fadt.reset_reg = r;
232 pm->fadt.reset_val = 0xf;
233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
235 pm->smi_on_cpuhp =
236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
237 pm->smi_on_cpu_unplug =
238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
239 }
240 pm->pcihp_io_base =
241 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
242 pm->pcihp_io_len =
243 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
244
245 /* The above need not be conditional on machine type because the reset port
246 * happens to be the same on PIIX (pc) and ICH9 (q35). */
247 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
248
249 /* Fill in optional s3/s4 related properties */
250 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
251 if (o) {
252 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
253 } else {
254 pm->s3_disabled = false;
255 }
256 qobject_unref(o);
257 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
258 if (o) {
259 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
260 } else {
261 pm->s4_disabled = false;
262 }
263 qobject_unref(o);
264 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
265 if (o) {
266 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
267 } else {
268 pm->s4_val = false;
269 }
270 qobject_unref(o);
271
272 pm->pcihp_bridge_en =
273 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
274 NULL);
275 pm->pcihp_root_en =
276 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
277 NULL);
278 }
279
280 static void acpi_get_misc_info(AcpiMiscInfo *info)
281 {
282 info->has_hpet = hpet_find();
283 #ifdef CONFIG_TPM
284 info->tpm_version = tpm_get_version(tpm_find());
285 #endif
286 }
287
288 /*
289 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
290 * On i386 arch we only have two pci hosts, so we can look only for them.
291 */
292 Object *acpi_get_i386_pci_host(void)
293 {
294 PCIHostState *host;
295
296 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
297 if (!host) {
298 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
299 }
300
301 return OBJECT(host);
302 }
303
304 static void acpi_get_pci_holes(Range *hole, Range *hole64)
305 {
306 Object *pci_host;
307
308 pci_host = acpi_get_i386_pci_host();
309
310 if (!pci_host) {
311 return;
312 }
313
314 range_set_bounds1(hole,
315 object_property_get_uint(pci_host,
316 PCI_HOST_PROP_PCI_HOLE_START,
317 NULL),
318 object_property_get_uint(pci_host,
319 PCI_HOST_PROP_PCI_HOLE_END,
320 NULL));
321 range_set_bounds1(hole64,
322 object_property_get_uint(pci_host,
323 PCI_HOST_PROP_PCI_HOLE64_START,
324 NULL),
325 object_property_get_uint(pci_host,
326 PCI_HOST_PROP_PCI_HOLE64_END,
327 NULL));
328 }
329
330 static void acpi_align_size(GArray *blob, unsigned align)
331 {
332 /* Align size to multiple of given size. This reduces the chance
333 * we need to change size in the future (breaking cross version migration).
334 */
335 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
336 }
337
338 /*
339 * ACPI spec 1.0b,
340 * 5.2.6 Firmware ACPI Control Structure
341 */
342 static void
343 build_facs(GArray *table_data)
344 {
345 const char *sig = "FACS";
346 const uint8_t reserved[40] = {};
347
348 g_array_append_vals(table_data, sig, 4); /* Signature */
349 build_append_int_noprefix(table_data, 64, 4); /* Length */
350 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
351 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
352 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
353 build_append_int_noprefix(table_data, 0, 4); /* Flags */
354 g_array_append_vals(table_data, reserved, 40); /* Reserved */
355 }
356
357 Aml *aml_pci_device_dsm(void)
358 {
359 Aml *method;
360
361 method = aml_method("_DSM", 4, AML_SERIALIZED);
362 {
363 Aml *params = aml_local(0);
364 Aml *pkg = aml_package(2);
365 aml_append(pkg, aml_int(0));
366 aml_append(pkg, aml_int(0));
367 aml_append(method, aml_store(pkg, params));
368 aml_append(method,
369 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0))));
370 aml_append(method,
371 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1))));
372 aml_append(method,
373 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
374 aml_arg(2), aml_arg(3), params))
375 );
376 }
377 return method;
378 }
379
380 static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar)
381 {
382 Aml *UUID, *ifctx1;
383 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
384
385 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar));
386 /*
387 * PCI Firmware Specification 3.1
388 * 4.6. _DSM Definitions for PCI
389 */
390 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
391 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
392 {
393 /* call is for unsupported UUID, bail out */
394 aml_append(ifctx1, aml_return(retvar));
395 }
396 aml_append(ctx, ifctx1);
397
398 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2)));
399 {
400 /* call is for unsupported REV, bail out */
401 aml_append(ifctx1, aml_return(retvar));
402 }
403 aml_append(ctx, ifctx1);
404 }
405
406 static Aml *aml_pci_edsm(void)
407 {
408 Aml *method, *ifctx;
409 Aml *zero = aml_int(0);
410 Aml *func = aml_arg(2);
411 Aml *ret = aml_local(0);
412 Aml *aidx = aml_local(1);
413 Aml *params = aml_arg(4);
414
415 method = aml_method("EDSM", 5, AML_SERIALIZED);
416
417 /* get supported functions */
418 ifctx = aml_if(aml_equal(func, zero));
419 {
420 /* 1: have supported functions */
421 /* 7: support for function 7 */
422 const uint8_t caps = 1 | BIT(7);
423 build_append_pci_dsm_func0_common(ifctx, ret);
424 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero)));
425 aml_append(ifctx, aml_return(ret));
426 }
427 aml_append(method, ifctx);
428
429 /* handle specific functions requests */
430 /*
431 * PCI Firmware Specification 3.1
432 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
433 * Operating Systems
434 */
435 ifctx = aml_if(aml_equal(func, aml_int(7)));
436 {
437 Aml *pkg = aml_package(2);
438 aml_append(pkg, zero);
439 /* optional, if not impl. should return null string */
440 aml_append(pkg, aml_string("%s", ""));
441 aml_append(ifctx, aml_store(pkg, ret));
442
443 /*
444 * IASL is fine when initializing Package with computational data,
445 * however it makes guest unhappy /it fails to process such AML/.
446 * So use runtime assignment to set acpi-index after initializer
447 * to make OSPM happy.
448 */
449 aml_append(ifctx,
450 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx));
451 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero)));
452 aml_append(ifctx, aml_return(ret));
453 }
454 aml_append(method, ifctx);
455
456 return method;
457 }
458
459 static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev)
460 {
461 Aml *method;
462
463 g_assert(pdev->acpi_index != 0);
464 method = aml_method("_DSM", 4, AML_SERIALIZED);
465 {
466 Aml *params = aml_local(0);
467 Aml *pkg = aml_package(1);
468 aml_append(pkg, aml_int(pdev->acpi_index));
469 aml_append(method, aml_store(pkg, params));
470 aml_append(method,
471 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
472 aml_arg(2), aml_arg(3), params))
473 );
474 }
475 return method;
476 }
477
478 static void build_append_pcihp_notify_entry(Aml *method, int slot)
479 {
480 Aml *if_ctx;
481 int32_t devfn = PCI_DEVFN(slot, 0);
482
483 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
484 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
485 aml_append(method, if_ctx);
486 }
487
488 static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
489 {
490 const PCIDevice *pdev = bus->devices[devfn];
491
492 if (PCI_FUNC(devfn)) {
493 if (IS_PCI_BRIDGE(pdev)) {
494 /*
495 * Ignore only hotplugged PCI bridges on !0 functions, but
496 * allow describing cold plugged bridges on all functions
497 */
498 if (DEVICE(pdev)->hotplugged) {
499 return true;
500 }
501 }
502 }
503 return false;
504 }
505
506 static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
507 {
508 PCIDevice *pdev = bus->devices[devfn];
509 if (pdev) {
510 return is_devfn_ignored_generic(devfn, bus) ||
511 !DEVICE_GET_CLASS(pdev)->hotpluggable ||
512 /* Cold plugged bridges aren't themselves hot-pluggable */
513 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
514 } else { /* non populated slots */
515 /*
516 * hotplug is supported only for non-multifunction device
517 * so generate device description only for function 0
518 */
519 if (PCI_FUNC(devfn) ||
520 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
521 return true;
522 }
523 }
524 return false;
525 }
526
527 void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus)
528 {
529 int devfn;
530 Aml *dev, *notify_method = NULL, *method;
531 QObject *bsel = object_property_get_qobject(OBJECT(bus),
532 ACPI_PCIHP_PROP_BSEL, NULL);
533 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
534 qobject_unref(bsel);
535
536 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
537 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
538
539 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
540 int slot = PCI_SLOT(devfn);
541 int adr = slot << 16 | PCI_FUNC(devfn);
542
543 if (is_devfn_ignored_hotplug(devfn, bus)) {
544 continue;
545 }
546
547 if (bus->devices[devfn]) {
548 dev = aml_scope("S%.02X", devfn);
549 } else {
550 dev = aml_device("S%.02X", devfn);
551 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
552 }
553
554 /*
555 * Can't declare _SUN here for every device as it changes 'slot'
556 * enumeration order in linux kernel, so use another variable for it
557 */
558 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
559 aml_append(dev, aml_pci_device_dsm());
560
561 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
562 /* add _EJ0 to make slot hotpluggable */
563 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
564 aml_append(method,
565 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
566 );
567 aml_append(dev, method);
568
569 build_append_pcihp_notify_entry(notify_method, slot);
570
571 /* device descriptor has been composed, add it into parent context */
572 aml_append(parent_scope, dev);
573 }
574 aml_append(parent_scope, notify_method);
575 }
576
577 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
578 {
579 int devfn;
580 Aml *dev;
581
582 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
583 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
584 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
585 PCIDevice *pdev = bus->devices[devfn];
586
587 if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
588 continue;
589 }
590
591 /* start to compose PCI device descriptor */
592 dev = aml_device("S%.02X", devfn);
593 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
594
595 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
596 /* add _DSM if device has acpi-index set */
597 if (pdev->acpi_index &&
598 !object_property_get_bool(OBJECT(pdev), "hotpluggable",
599 &error_abort)) {
600 aml_append(dev, aml_pci_static_endpoint_dsm(pdev));
601 }
602
603 /* device descriptor has been composed, add it into parent context */
604 aml_append(parent_scope, dev);
605 }
606 }
607
608 static bool build_append_notfication_callback(Aml *parent_scope,
609 const PCIBus *bus)
610 {
611 Aml *method;
612 PCIBus *sec;
613 QObject *bsel;
614 int nr_notifiers = 0;
615 GQueue *pcnt_bus_list = g_queue_new();
616
617 QLIST_FOREACH(sec, &bus->child, sibling) {
618 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
619 if (pci_bus_is_root(sec)) {
620 continue;
621 }
622 nr_notifiers = nr_notifiers +
623 build_append_notfication_callback(br_scope, sec);
624 /*
625 * add new child scope to parent
626 * and keep track of bus that have PCNT,
627 * bus list is used later to call children PCNTs from this level PCNT
628 */
629 if (nr_notifiers) {
630 g_queue_push_tail(pcnt_bus_list, sec);
631 aml_append(parent_scope, br_scope);
632 }
633 }
634
635 /*
636 * Append PCNT method to notify about events on local and child buses.
637 * ps: hostbridge might not have hotplug (bsel) enabled but might have
638 * child bridges that do have bsel.
639 */
640 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
641
642 /* If bus supports hotplug select it and notify about local events */
643 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
644 if (bsel) {
645 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
646
647 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
648 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
649 aml_int(1))); /* Device Check */
650 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
651 aml_int(3))); /* Eject Request */
652 nr_notifiers++;
653 }
654
655 /* Notify about child bus events in any case */
656 while ((sec = g_queue_pop_head(pcnt_bus_list))) {
657 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
658 }
659
660 aml_append(parent_scope, method);
661 qobject_unref(bsel);
662 g_queue_free(pcnt_bus_list);
663 return !!nr_notifiers;
664 }
665
666 static Aml *aml_pci_pdsm(void)
667 {
668 Aml *method, *ifctx, *ifctx1;
669 Aml *ret = aml_local(0);
670 Aml *caps = aml_local(1);
671 Aml *acpi_index = aml_local(2);
672 Aml *zero = aml_int(0);
673 Aml *one = aml_int(1);
674 Aml *func = aml_arg(2);
675 Aml *params = aml_arg(4);
676 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
677 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
678
679 method = aml_method("PDSM", 5, AML_SERIALIZED);
680
681 /* get supported functions */
682 ifctx = aml_if(aml_equal(func, zero));
683 {
684 build_append_pci_dsm_func0_common(ifctx, ret);
685
686 aml_append(ifctx, aml_store(zero, caps));
687 aml_append(ifctx,
688 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
689 /*
690 * advertise function 7 if device has acpi-index
691 * acpi_index values:
692 * 0: not present (default value)
693 * FFFFFFFF: not supported (old QEMU without PIDX reg)
694 * other: device's acpi-index
695 */
696 ifctx1 = aml_if(aml_lnot(
697 aml_or(aml_equal(acpi_index, zero),
698 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
699 ));
700 {
701 /* have supported functions */
702 aml_append(ifctx1, aml_or(caps, one, caps));
703 /* support for function 7 */
704 aml_append(ifctx1,
705 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
706 }
707 aml_append(ifctx, ifctx1);
708
709 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
710 aml_append(ifctx, aml_return(ret));
711 }
712 aml_append(method, ifctx);
713
714 /* handle specific functions requests */
715 /*
716 * PCI Firmware Specification 3.1
717 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
718 * Operating Systems
719 */
720 ifctx = aml_if(aml_equal(func, aml_int(7)));
721 {
722 Aml *pkg = aml_package(2);
723
724 aml_append(pkg, zero);
725 /*
726 * optional, if not impl. should return null string
727 */
728 aml_append(pkg, aml_string("%s", ""));
729 aml_append(ifctx, aml_store(pkg, ret));
730
731 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
732 /*
733 * update acpi-index to actual value
734 */
735 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
736 aml_append(ifctx, aml_return(ret));
737 }
738
739 aml_append(method, ifctx);
740 return method;
741 }
742
743 /**
744 * build_prt_entry:
745 * @link_name: link name for PCI route entry
746 *
747 * build AML package containing a PCI route entry for @link_name
748 */
749 static Aml *build_prt_entry(const char *link_name)
750 {
751 Aml *a_zero = aml_int(0);
752 Aml *pkg = aml_package(4);
753 aml_append(pkg, a_zero);
754 aml_append(pkg, a_zero);
755 aml_append(pkg, aml_name("%s", link_name));
756 aml_append(pkg, a_zero);
757 return pkg;
758 }
759
760 /*
761 * initialize_route - Initialize the interrupt routing rule
762 * through a specific LINK:
763 * if (lnk_idx == idx)
764 * route using link 'link_name'
765 */
766 static Aml *initialize_route(Aml *route, const char *link_name,
767 Aml *lnk_idx, int idx)
768 {
769 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
770 Aml *pkg = build_prt_entry(link_name);
771
772 aml_append(if_ctx, aml_store(pkg, route));
773
774 return if_ctx;
775 }
776
777 /*
778 * build_prt - Define interrupt rounting rules
779 *
780 * Returns an array of 128 routes, one for each device,
781 * based on device location.
782 * The main goal is to equaly distribute the interrupts
783 * over the 4 existing ACPI links (works only for i440fx).
784 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
785 *
786 */
787 static Aml *build_prt(bool is_pci0_prt)
788 {
789 Aml *method, *while_ctx, *pin, *res;
790
791 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
792 res = aml_local(0);
793 pin = aml_local(1);
794 aml_append(method, aml_store(aml_package(128), res));
795 aml_append(method, aml_store(aml_int(0), pin));
796
797 /* while (pin < 128) */
798 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
799 {
800 Aml *slot = aml_local(2);
801 Aml *lnk_idx = aml_local(3);
802 Aml *route = aml_local(4);
803
804 /* slot = pin >> 2 */
805 aml_append(while_ctx,
806 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
807 /* lnk_idx = (slot + pin) & 3 */
808 aml_append(while_ctx,
809 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
810 lnk_idx));
811
812 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
813 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
814 if (is_pci0_prt) {
815 Aml *if_device_1, *if_pin_4, *else_pin_4;
816
817 /* device 1 is the power-management device, needs SCI */
818 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
819 {
820 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
821 {
822 aml_append(if_pin_4,
823 aml_store(build_prt_entry("LNKS"), route));
824 }
825 aml_append(if_device_1, if_pin_4);
826 else_pin_4 = aml_else();
827 {
828 aml_append(else_pin_4,
829 aml_store(build_prt_entry("LNKA"), route));
830 }
831 aml_append(if_device_1, else_pin_4);
832 }
833 aml_append(while_ctx, if_device_1);
834 } else {
835 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
836 }
837 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
838 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
839
840 /* route[0] = 0x[slot]FFFF */
841 aml_append(while_ctx,
842 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
843 NULL),
844 aml_index(route, aml_int(0))));
845 /* route[1] = pin & 3 */
846 aml_append(while_ctx,
847 aml_store(aml_and(pin, aml_int(3), NULL),
848 aml_index(route, aml_int(1))));
849 /* res[pin] = route */
850 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
851 /* pin++ */
852 aml_append(while_ctx, aml_increment(pin));
853 }
854 aml_append(method, while_ctx);
855 /* return res*/
856 aml_append(method, aml_return(res));
857
858 return method;
859 }
860
861 static void build_hpet_aml(Aml *table)
862 {
863 Aml *crs;
864 Aml *field;
865 Aml *method;
866 Aml *if_ctx;
867 Aml *scope = aml_scope("_SB");
868 Aml *dev = aml_device("HPET");
869 Aml *zero = aml_int(0);
870 Aml *id = aml_local(0);
871 Aml *period = aml_local(1);
872
873 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
874 aml_append(dev, aml_name_decl("_UID", zero));
875
876 aml_append(dev,
877 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
878 HPET_LEN));
879 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
880 aml_append(field, aml_named_field("VEND", 32));
881 aml_append(field, aml_named_field("PRD", 32));
882 aml_append(dev, field);
883
884 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
885 aml_append(method, aml_store(aml_name("VEND"), id));
886 aml_append(method, aml_store(aml_name("PRD"), period));
887 aml_append(method, aml_shiftright(id, aml_int(16), id));
888 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
889 aml_equal(id, aml_int(0xffff))));
890 {
891 aml_append(if_ctx, aml_return(zero));
892 }
893 aml_append(method, if_ctx);
894
895 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
896 aml_lgreater(period, aml_int(100000000))));
897 {
898 aml_append(if_ctx, aml_return(zero));
899 }
900 aml_append(method, if_ctx);
901
902 aml_append(method, aml_return(aml_int(0x0F)));
903 aml_append(dev, method);
904
905 crs = aml_resource_template();
906 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
907 aml_append(dev, aml_name_decl("_CRS", crs));
908
909 aml_append(scope, dev);
910 aml_append(table, scope);
911 }
912
913 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
914 {
915 Aml *dev;
916 Aml *method;
917 Aml *crs;
918
919 dev = aml_device("VMBS");
920 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
921 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
922 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
923 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
924
925 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
926 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
927 aml_name("STA")));
928 aml_append(dev, method);
929
930 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
931 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
932 aml_name("STA")));
933 aml_append(dev, method);
934
935 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
936 aml_append(method, aml_return(aml_name("STA")));
937 aml_append(dev, method);
938
939 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
940
941 crs = aml_resource_template();
942 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
943 aml_append(dev, aml_name_decl("_CRS", crs));
944
945 return dev;
946 }
947
948 static void build_dbg_aml(Aml *table)
949 {
950 Aml *field;
951 Aml *method;
952 Aml *while_ctx;
953 Aml *scope = aml_scope("\\");
954 Aml *buf = aml_local(0);
955 Aml *len = aml_local(1);
956 Aml *idx = aml_local(2);
957
958 aml_append(scope,
959 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
960 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
961 aml_append(field, aml_named_field("DBGB", 8));
962 aml_append(scope, field);
963
964 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
965
966 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
967 aml_append(method, aml_to_buffer(buf, buf));
968 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
969 aml_append(method, aml_store(aml_int(0), idx));
970
971 while_ctx = aml_while(aml_lless(idx, len));
972 aml_append(while_ctx,
973 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
974 aml_append(while_ctx, aml_increment(idx));
975 aml_append(method, while_ctx);
976
977 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
978 aml_append(scope, method);
979
980 aml_append(table, scope);
981 }
982
983 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
984 {
985 Aml *dev;
986 Aml *crs;
987 Aml *method;
988 uint32_t irqs[] = {5, 10, 11};
989
990 dev = aml_device("%s", name);
991 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
992 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
993
994 crs = aml_resource_template();
995 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
996 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
997 aml_append(dev, aml_name_decl("_PRS", crs));
998
999 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1000 aml_append(method, aml_return(aml_call1("IQST", reg)));
1001 aml_append(dev, method);
1002
1003 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1004 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1005 aml_append(dev, method);
1006
1007 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1008 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1009 aml_append(dev, method);
1010
1011 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1012 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1013 aml_append(method, aml_store(aml_name("PRRI"), reg));
1014 aml_append(dev, method);
1015
1016 return dev;
1017 }
1018
1019 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1020 {
1021 Aml *dev;
1022 Aml *crs;
1023 Aml *method;
1024 uint32_t irqs;
1025
1026 dev = aml_device("%s", name);
1027 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1028 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1029
1030 crs = aml_resource_template();
1031 irqs = gsi;
1032 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1033 AML_SHARED, &irqs, 1));
1034 aml_append(dev, aml_name_decl("_PRS", crs));
1035
1036 aml_append(dev, aml_name_decl("_CRS", crs));
1037
1038 /*
1039 * _DIS can be no-op because the interrupt cannot be disabled.
1040 */
1041 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1042 aml_append(dev, method);
1043
1044 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1045 aml_append(dev, method);
1046
1047 return dev;
1048 }
1049
1050 /* _CRS method - get current settings */
1051 static Aml *build_iqcr_method(bool is_piix4)
1052 {
1053 Aml *if_ctx;
1054 uint32_t irqs;
1055 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1056 Aml *crs = aml_resource_template();
1057
1058 irqs = 0;
1059 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1060 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1061 aml_append(method, aml_name_decl("PRR0", crs));
1062
1063 aml_append(method,
1064 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1065
1066 if (is_piix4) {
1067 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1068 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1069 aml_append(method, if_ctx);
1070 } else {
1071 aml_append(method,
1072 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1073 aml_name("PRRI")));
1074 }
1075
1076 aml_append(method, aml_return(aml_name("PRR0")));
1077 return method;
1078 }
1079
1080 /* _STA method - get status */
1081 static Aml *build_irq_status_method(void)
1082 {
1083 Aml *if_ctx;
1084 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1085
1086 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1087 aml_append(if_ctx, aml_return(aml_int(0x09)));
1088 aml_append(method, if_ctx);
1089 aml_append(method, aml_return(aml_int(0x0B)));
1090 return method;
1091 }
1092
1093 static void build_piix4_pci0_int(Aml *table)
1094 {
1095 Aml *dev;
1096 Aml *crs;
1097 Aml *method;
1098 uint32_t irqs;
1099 Aml *sb_scope = aml_scope("_SB");
1100 Aml *pci0_scope = aml_scope("PCI0");
1101
1102 aml_append(pci0_scope, build_prt(true));
1103 aml_append(sb_scope, pci0_scope);
1104
1105 aml_append(sb_scope, build_irq_status_method());
1106 aml_append(sb_scope, build_iqcr_method(true));
1107
1108 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1109 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1110 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1111 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1112
1113 dev = aml_device("LNKS");
1114 {
1115 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1116 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1117
1118 crs = aml_resource_template();
1119 irqs = 9;
1120 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1121 AML_ACTIVE_HIGH, AML_SHARED,
1122 &irqs, 1));
1123 aml_append(dev, aml_name_decl("_PRS", crs));
1124
1125 /* The SCI cannot be disabled and is always attached to GSI 9,
1126 * so these are no-ops. We only need this link to override the
1127 * polarity to active high and match the content of the MADT.
1128 */
1129 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1130 aml_append(method, aml_return(aml_int(0x0b)));
1131 aml_append(dev, method);
1132
1133 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1134 aml_append(dev, method);
1135
1136 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1137 aml_append(method, aml_return(aml_name("_PRS")));
1138 aml_append(dev, method);
1139
1140 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1141 aml_append(dev, method);
1142 }
1143 aml_append(sb_scope, dev);
1144
1145 aml_append(table, sb_scope);
1146 }
1147
1148 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1149 {
1150 int i;
1151 int head;
1152 Aml *pkg;
1153 char base = name[3] < 'E' ? 'A' : 'E';
1154 char *s = g_strdup(name);
1155 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1156
1157 assert(strlen(s) == 4);
1158
1159 head = name[3] - base;
1160 for (i = 0; i < 4; i++) {
1161 if (head + i > 3) {
1162 head = i * -1;
1163 }
1164 s[3] = base + head + i;
1165 pkg = aml_package(4);
1166 aml_append(pkg, a_nr);
1167 aml_append(pkg, aml_int(i));
1168 aml_append(pkg, aml_name("%s", s));
1169 aml_append(pkg, aml_int(0));
1170 aml_append(ctx, pkg);
1171 }
1172 g_free(s);
1173 }
1174
1175 static Aml *build_q35_routing_table(const char *str)
1176 {
1177 int i;
1178 Aml *pkg;
1179 char *name = g_strdup_printf("%s ", str);
1180
1181 pkg = aml_package(128);
1182 for (i = 0; i < 0x18; i++) {
1183 name[3] = 'E' + (i & 0x3);
1184 append_q35_prt_entry(pkg, i, name);
1185 }
1186
1187 name[3] = 'E';
1188 append_q35_prt_entry(pkg, 0x18, name);
1189
1190 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1191 for (i = 0x0019; i < 0x1e; i++) {
1192 name[3] = 'A';
1193 append_q35_prt_entry(pkg, i, name);
1194 }
1195
1196 /* PCIe->PCI bridge. use PIRQ[E-H] */
1197 name[3] = 'E';
1198 append_q35_prt_entry(pkg, 0x1e, name);
1199 name[3] = 'A';
1200 append_q35_prt_entry(pkg, 0x1f, name);
1201
1202 g_free(name);
1203 return pkg;
1204 }
1205
1206 static void build_q35_pci0_int(Aml *table)
1207 {
1208 Aml *method;
1209 Aml *sb_scope = aml_scope("_SB");
1210 Aml *pci0_scope = aml_scope("PCI0");
1211
1212 /* Zero => PIC mode, One => APIC Mode */
1213 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1214 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1215 {
1216 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1217 }
1218 aml_append(table, method);
1219
1220 aml_append(pci0_scope,
1221 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1222 aml_append(pci0_scope,
1223 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1224
1225 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1226 {
1227 Aml *if_ctx;
1228 Aml *else_ctx;
1229
1230 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1231 section 6.2.8.1 */
1232 /* Note: we provide the same info as the PCI routing
1233 table of the Bochs BIOS */
1234 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1235 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1236 aml_append(method, if_ctx);
1237 else_ctx = aml_else();
1238 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1239 aml_append(method, else_ctx);
1240 }
1241 aml_append(pci0_scope, method);
1242 aml_append(sb_scope, pci0_scope);
1243
1244 aml_append(sb_scope, build_irq_status_method());
1245 aml_append(sb_scope, build_iqcr_method(false));
1246
1247 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1248 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1249 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1250 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1251 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1252 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1253 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1254 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1255
1256 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1257 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1258 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1259 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1260 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1261 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1262 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1263 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1264
1265 aml_append(table, sb_scope);
1266 }
1267
1268 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1269 {
1270 Aml *dev;
1271 Aml *resource_template;
1272
1273 /* DRAM controller */
1274 dev = aml_device("DRAC");
1275 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1276
1277 resource_template = aml_resource_template();
1278 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1279 aml_append(resource_template,
1280 aml_qword_memory(AML_POS_DECODE,
1281 AML_MIN_FIXED,
1282 AML_MAX_FIXED,
1283 AML_NON_CACHEABLE,
1284 AML_READ_WRITE,
1285 0x0000000000000000,
1286 mcfg->base,
1287 mcfg->base + mcfg->size - 1,
1288 0x0000000000000000,
1289 mcfg->size));
1290 } else {
1291 aml_append(resource_template,
1292 aml_dword_memory(AML_POS_DECODE,
1293 AML_MIN_FIXED,
1294 AML_MAX_FIXED,
1295 AML_NON_CACHEABLE,
1296 AML_READ_WRITE,
1297 0x0000000000000000,
1298 mcfg->base,
1299 mcfg->base + mcfg->size - 1,
1300 0x0000000000000000,
1301 mcfg->size));
1302 }
1303 aml_append(dev, aml_name_decl("_CRS", resource_template));
1304
1305 return dev;
1306 }
1307
1308 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1309 {
1310 Aml *scope;
1311 Aml *field;
1312 Aml *method;
1313
1314 scope = aml_scope("_SB.PCI0");
1315
1316 aml_append(scope,
1317 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1318 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1319 aml_append(field, aml_named_field("PCIU", 32));
1320 aml_append(field, aml_named_field("PCID", 32));
1321 aml_append(scope, field);
1322
1323 aml_append(scope,
1324 aml_operation_region("SEJ", AML_SYSTEM_IO,
1325 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1326 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1327 aml_append(field, aml_named_field("B0EJ", 32));
1328 aml_append(scope, field);
1329
1330 aml_append(scope,
1331 aml_operation_region("BNMR", AML_SYSTEM_IO,
1332 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1333 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1334 aml_append(field, aml_named_field("BNUM", 32));
1335 aml_append(field, aml_named_field("PIDX", 32));
1336 aml_append(scope, field);
1337
1338 aml_append(scope, aml_mutex("BLCK", 0));
1339
1340 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1341 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1342 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1343 aml_append(method,
1344 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1345 aml_append(method, aml_release(aml_name("BLCK")));
1346 aml_append(method, aml_return(aml_int(0)));
1347 aml_append(scope, method);
1348
1349 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1350 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1351 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1352 aml_append(method,
1353 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1354 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1355 aml_append(method, aml_release(aml_name("BLCK")));
1356 aml_append(method, aml_return(aml_local(0)));
1357 aml_append(scope, method);
1358
1359 aml_append(scope, aml_pci_pdsm());
1360
1361 aml_append(table, scope);
1362 }
1363
1364 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1365 {
1366 Aml *if_ctx;
1367 Aml *if_ctx2;
1368 Aml *else_ctx;
1369 Aml *method;
1370 Aml *a_cwd1 = aml_name("CDW1");
1371 Aml *a_ctrl = aml_local(0);
1372
1373 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1374 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1375
1376 if_ctx = aml_if(aml_equal(
1377 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1378 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1379 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1380
1381 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1382
1383 /*
1384 * Always allow native PME, AER (no dependencies)
1385 * Allow SHPC (PCI bridges can have SHPC controller)
1386 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1387 */
1388 aml_append(if_ctx, aml_and(a_ctrl,
1389 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1390
1391 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1392 /* Unknown revision */
1393 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1394 aml_append(if_ctx, if_ctx2);
1395
1396 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1397 /* Capabilities bits were masked */
1398 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1399 aml_append(if_ctx, if_ctx2);
1400
1401 /* Update DWORD3 in the buffer */
1402 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1403 aml_append(method, if_ctx);
1404
1405 else_ctx = aml_else();
1406 /* Unrecognized UUID */
1407 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1408 aml_append(method, else_ctx);
1409
1410 aml_append(method, aml_return(aml_arg(3)));
1411 return method;
1412 }
1413
1414 static void build_acpi0017(Aml *table)
1415 {
1416 Aml *dev, *scope, *method;
1417
1418 scope = aml_scope("_SB");
1419 dev = aml_device("CXLM");
1420 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1421
1422 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1423 aml_append(method, aml_return(aml_int(0x01)));
1424 aml_append(dev, method);
1425
1426 aml_append(scope, dev);
1427 aml_append(table, scope);
1428 }
1429
1430 static void
1431 build_dsdt(GArray *table_data, BIOSLinker *linker,
1432 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1433 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1434 {
1435 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE);
1436 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE);
1437 CrsRangeEntry *entry;
1438 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1439 CrsRangeSet crs_range_set;
1440 PCMachineState *pcms = PC_MACHINE(machine);
1441 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1442 X86MachineState *x86ms = X86_MACHINE(machine);
1443 AcpiMcfgInfo mcfg;
1444 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1445 uint32_t nr_mem = machine->ram_slots;
1446 int root_bus_limit = 0xFF;
1447 PCIBus *bus = NULL;
1448 #ifdef CONFIG_TPM
1449 TPMIf *tpm = tpm_find();
1450 #endif
1451 bool cxl_present = false;
1452 int i;
1453 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1454 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1455 .oem_table_id = x86ms->oem_table_id };
1456
1457 assert(!!i440fx != !!q35);
1458
1459 acpi_table_begin(&table, table_data);
1460 dsdt = init_aml_allocator();
1461
1462 build_dbg_aml(dsdt);
1463 if (i440fx) {
1464 sb_scope = aml_scope("_SB");
1465 dev = aml_device("PCI0");
1466 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1467 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1468 aml_append(dev, aml_pci_edsm());
1469 aml_append(sb_scope, dev);
1470 aml_append(dsdt, sb_scope);
1471
1472 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1473 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1474 }
1475 build_piix4_pci0_int(dsdt);
1476 } else if (q35) {
1477 sb_scope = aml_scope("_SB");
1478 dev = aml_device("PCI0");
1479 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1480 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1481 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1482 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1483 aml_append(dev, aml_pci_edsm());
1484 aml_append(sb_scope, dev);
1485 if (mcfg_valid) {
1486 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1487 }
1488
1489 if (pm->smi_on_cpuhp) {
1490 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1491 dev = aml_device("PCI0.SMI0");
1492 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1493 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1494 crs = aml_resource_template();
1495 aml_append(crs,
1496 aml_io(
1497 AML_DECODE16,
1498 ACPI_PORT_SMI_CMD,
1499 ACPI_PORT_SMI_CMD,
1500 1,
1501 2)
1502 );
1503 aml_append(dev, aml_name_decl("_CRS", crs));
1504 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1505 aml_int(ACPI_PORT_SMI_CMD), 2));
1506 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1507 AML_WRITE_AS_ZEROS);
1508 aml_append(field, aml_named_field("SMIC", 8));
1509 aml_append(field, aml_reserved_field(8));
1510 aml_append(dev, field);
1511 aml_append(sb_scope, dev);
1512 }
1513
1514 aml_append(dsdt, sb_scope);
1515
1516 if (pm->pcihp_bridge_en) {
1517 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1518 }
1519 build_q35_pci0_int(dsdt);
1520 }
1521
1522 if (misc->has_hpet) {
1523 build_hpet_aml(dsdt);
1524 }
1525
1526 if (vmbus_bridge) {
1527 sb_scope = aml_scope("_SB");
1528 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1529 aml_append(dsdt, sb_scope);
1530 }
1531
1532 scope = aml_scope("_GPE");
1533 {
1534 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1535 if (machine->nvdimms_state->is_enabled) {
1536 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1537 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1538 aml_int(0x80)));
1539 aml_append(scope, method);
1540 }
1541 }
1542 aml_append(dsdt, scope);
1543
1544 if (pcmc->legacy_cpu_hotplug) {
1545 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1546 } else {
1547 CPUHotplugFeatures opts = {
1548 .acpi_1_compatible = true, .has_legacy_cphp = true,
1549 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1550 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1551 };
1552 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1553 "\\_SB.PCI0", "\\_GPE._E02");
1554 }
1555
1556 if (pcms->memhp_io_base && nr_mem) {
1557 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1558 "\\_GPE._E03", AML_SYSTEM_IO,
1559 pcms->memhp_io_base);
1560 }
1561
1562 crs_range_set_init(&crs_range_set);
1563 bus = PC_MACHINE(machine)->bus;
1564 if (bus) {
1565 QLIST_FOREACH(bus, &bus->child, sibling) {
1566 uint8_t bus_num = pci_bus_num(bus);
1567 uint8_t numa_node = pci_bus_numa_node(bus);
1568
1569 /* look only for expander root buses */
1570 if (!pci_bus_is_root(bus)) {
1571 continue;
1572 }
1573
1574 if (bus_num < root_bus_limit) {
1575 root_bus_limit = bus_num - 1;
1576 }
1577
1578 scope = aml_scope("\\_SB");
1579
1580 if (pci_bus_is_cxl(bus)) {
1581 dev = aml_device("CL%.02X", bus_num);
1582 } else {
1583 dev = aml_device("PC%.02X", bus_num);
1584 }
1585 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1586 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1587 if (pci_bus_is_cxl(bus)) {
1588 struct Aml *pkg = aml_package(2);
1589
1590 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1591 aml_append(pkg, aml_eisaid("PNP0A08"));
1592 aml_append(pkg, aml_eisaid("PNP0A03"));
1593 aml_append(dev, aml_name_decl("_CID", pkg));
1594 build_cxl_osc_method(dev);
1595 } else if (pci_bus_is_express(bus)) {
1596 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1597 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1598
1599 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1600 aml_append(dev, build_q35_osc_method(true));
1601 } else {
1602 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1603 }
1604
1605 if (numa_node != NUMA_NODE_UNASSIGNED) {
1606 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1607 }
1608
1609 aml_append(dev, build_prt(false));
1610 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1611 0, 0, 0, 0);
1612 aml_append(dev, aml_name_decl("_CRS", crs));
1613 aml_append(scope, dev);
1614 aml_append(dsdt, scope);
1615
1616 /* Handle the ranges for the PXB expanders */
1617 if (pci_bus_is_cxl(bus)) {
1618 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1619 uint64_t base = mr->addr;
1620
1621 cxl_present = true;
1622 crs_range_insert(crs_range_set.mem_ranges, base,
1623 base + memory_region_size(mr) - 1);
1624 }
1625 }
1626 }
1627
1628 if (cxl_present) {
1629 build_acpi0017(dsdt);
1630 }
1631
1632 /*
1633 * At this point crs_range_set has all the ranges used by pci
1634 * busses *other* than PCI0. These ranges will be excluded from
1635 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1636 * too.
1637 */
1638 if (mcfg_valid) {
1639 crs_range_insert(crs_range_set.mem_ranges,
1640 mcfg.base, mcfg.base + mcfg.size - 1);
1641 }
1642
1643 scope = aml_scope("\\_SB.PCI0");
1644 /* build PCI0._CRS */
1645 crs = aml_resource_template();
1646 aml_append(crs,
1647 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1648 0x0000, 0x0, root_bus_limit,
1649 0x0000, root_bus_limit + 1));
1650 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1651
1652 aml_append(crs,
1653 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1654 AML_POS_DECODE, AML_ENTIRE_RANGE,
1655 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1656
1657 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1658 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1659 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1660 aml_append(crs,
1661 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1662 AML_POS_DECODE, AML_ENTIRE_RANGE,
1663 0x0000, entry->base, entry->limit,
1664 0x0000, entry->limit - entry->base + 1));
1665 }
1666
1667 aml_append(crs,
1668 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1669 AML_CACHEABLE, AML_READ_WRITE,
1670 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1671
1672 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1673 range_lob(pci_hole),
1674 range_upb(pci_hole));
1675 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1676 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1677 aml_append(crs,
1678 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1679 AML_NON_CACHEABLE, AML_READ_WRITE,
1680 0, entry->base, entry->limit,
1681 0, entry->limit - entry->base + 1));
1682 }
1683
1684 if (!range_is_empty(pci_hole64)) {
1685 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1686 range_lob(pci_hole64),
1687 range_upb(pci_hole64));
1688 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1689 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1690 aml_append(crs,
1691 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1692 AML_MAX_FIXED,
1693 AML_CACHEABLE, AML_READ_WRITE,
1694 0, entry->base, entry->limit,
1695 0, entry->limit - entry->base + 1));
1696 }
1697 }
1698
1699 #ifdef CONFIG_TPM
1700 if (TPM_IS_TIS_ISA(tpm_find())) {
1701 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1702 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1703 }
1704 #endif
1705 aml_append(scope, aml_name_decl("_CRS", crs));
1706
1707 /* reserve GPE0 block resources */
1708 dev = aml_device("GPE0");
1709 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1710 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1711 /* device present, functioning, decoding, not shown in UI */
1712 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1713 crs = aml_resource_template();
1714 aml_append(crs,
1715 aml_io(
1716 AML_DECODE16,
1717 pm->fadt.gpe0_blk.address,
1718 pm->fadt.gpe0_blk.address,
1719 1,
1720 pm->fadt.gpe0_blk.bit_width / 8)
1721 );
1722 aml_append(dev, aml_name_decl("_CRS", crs));
1723 aml_append(scope, dev);
1724
1725 crs_range_set_free(&crs_range_set);
1726
1727 /* reserve PCIHP resources */
1728 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1729 dev = aml_device("PHPR");
1730 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1731 aml_append(dev,
1732 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1733 /* device present, functioning, decoding, not shown in UI */
1734 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1735 crs = aml_resource_template();
1736 aml_append(crs,
1737 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1738 pm->pcihp_io_len)
1739 );
1740 aml_append(dev, aml_name_decl("_CRS", crs));
1741 aml_append(scope, dev);
1742 }
1743 aml_append(dsdt, scope);
1744
1745 /* create S3_ / S4_ / S5_ packages if necessary */
1746 scope = aml_scope("\\");
1747 if (!pm->s3_disabled) {
1748 pkg = aml_package(4);
1749 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1750 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1751 aml_append(pkg, aml_int(0)); /* reserved */
1752 aml_append(pkg, aml_int(0)); /* reserved */
1753 aml_append(scope, aml_name_decl("_S3", pkg));
1754 }
1755
1756 if (!pm->s4_disabled) {
1757 pkg = aml_package(4);
1758 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1759 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1760 aml_append(pkg, aml_int(pm->s4_val));
1761 aml_append(pkg, aml_int(0)); /* reserved */
1762 aml_append(pkg, aml_int(0)); /* reserved */
1763 aml_append(scope, aml_name_decl("_S4", pkg));
1764 }
1765
1766 pkg = aml_package(4);
1767 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1768 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1769 aml_append(pkg, aml_int(0)); /* reserved */
1770 aml_append(pkg, aml_int(0)); /* reserved */
1771 aml_append(scope, aml_name_decl("_S5", pkg));
1772 aml_append(dsdt, scope);
1773
1774 /* create fw_cfg node, unconditionally */
1775 {
1776 scope = aml_scope("\\_SB.PCI0");
1777 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1778 aml_append(dsdt, scope);
1779 }
1780
1781 sb_scope = aml_scope("\\_SB");
1782 {
1783 Object *pci_host = acpi_get_i386_pci_host();
1784
1785 if (pci_host) {
1786 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
1787 Aml *scope = aml_scope("PCI0");
1788 /* Scan all PCI buses. Generate tables to support hotplug. */
1789 build_append_pci_bus_devices(scope, bus);
1790 if (object_property_find(OBJECT(bus), ACPI_PCIHP_PROP_BSEL)) {
1791 build_append_pcihp_slots(scope, bus);
1792 }
1793 aml_append(sb_scope, scope);
1794 }
1795 }
1796
1797 #ifdef CONFIG_TPM
1798 if (TPM_IS_CRB(tpm)) {
1799 dev = aml_device("TPM");
1800 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1801 aml_append(dev, aml_name_decl("_STR",
1802 aml_string("TPM 2.0 Device")));
1803 crs = aml_resource_template();
1804 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1805 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1806 aml_append(dev, aml_name_decl("_CRS", crs));
1807
1808 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1809 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1810
1811 tpm_build_ppi_acpi(tpm, dev);
1812
1813 aml_append(sb_scope, dev);
1814 }
1815 #endif
1816
1817 if (pcms->sgx_epc.size != 0) {
1818 uint64_t epc_base = pcms->sgx_epc.base;
1819 uint64_t epc_size = pcms->sgx_epc.size;
1820
1821 dev = aml_device("EPC");
1822 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1823 aml_append(dev, aml_name_decl("_STR",
1824 aml_unicode("Enclave Page Cache 1.0")));
1825 crs = aml_resource_template();
1826 aml_append(crs,
1827 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1828 AML_MAX_FIXED, AML_NON_CACHEABLE,
1829 AML_READ_WRITE, 0, epc_base,
1830 epc_base + epc_size - 1, 0, epc_size));
1831 aml_append(dev, aml_name_decl("_CRS", crs));
1832
1833 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1834 aml_append(method, aml_return(aml_int(0x0f)));
1835 aml_append(dev, method);
1836
1837 aml_append(sb_scope, dev);
1838 }
1839 aml_append(dsdt, sb_scope);
1840
1841 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1842 bool has_pcnt;
1843
1844 Object *pci_host = acpi_get_i386_pci_host();
1845 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
1846
1847 scope = aml_scope("\\_SB.PCI0");
1848 has_pcnt = build_append_notfication_callback(scope, bus);
1849 if (has_pcnt) {
1850 aml_append(dsdt, scope);
1851 }
1852
1853 scope = aml_scope("_GPE");
1854 {
1855 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1856 if (has_pcnt) {
1857 aml_append(method,
1858 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1859 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1860 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1861 }
1862 aml_append(scope, method);
1863 }
1864 aml_append(dsdt, scope);
1865 }
1866
1867 /* copy AML table into ACPI tables blob and patch header there */
1868 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1869 acpi_table_end(linker, &table);
1870 free_aml_allocator();
1871 }
1872
1873 /*
1874 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1875 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1876 */
1877 static void
1878 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1879 const char *oem_table_id)
1880 {
1881 AcpiTable table = { .sig = "HPET", .rev = 1,
1882 .oem_id = oem_id, .oem_table_id = oem_table_id };
1883
1884 acpi_table_begin(&table, table_data);
1885 /* Note timer_block_id value must be kept in sync with value advertised by
1886 * emulated hpet
1887 */
1888 /* Event Timer Block ID */
1889 build_append_int_noprefix(table_data, 0x8086a201, 4);
1890 /* BASE_ADDRESS */
1891 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1892 /* HPET Number */
1893 build_append_int_noprefix(table_data, 0, 1);
1894 /* Main Counter Minimum Clock_tick in Periodic Mode */
1895 build_append_int_noprefix(table_data, 0, 2);
1896 /* Page Protection And OEM Attribute */
1897 build_append_int_noprefix(table_data, 0, 1);
1898 acpi_table_end(linker, &table);
1899 }
1900
1901 #ifdef CONFIG_TPM
1902 /*
1903 * TCPA Description Table
1904 *
1905 * Following Level 00, Rev 00.37 of specs:
1906 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1907 * 7.1.2 ACPI Table Layout
1908 */
1909 static void
1910 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1911 const char *oem_id, const char *oem_table_id)
1912 {
1913 unsigned log_addr_offset;
1914 AcpiTable table = { .sig = "TCPA", .rev = 2,
1915 .oem_id = oem_id, .oem_table_id = oem_table_id };
1916
1917 acpi_table_begin(&table, table_data);
1918 /* Platform Class */
1919 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1920 /* Log Area Minimum Length (LAML) */
1921 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1922 /* Log Area Start Address (LASA) */
1923 log_addr_offset = table_data->len;
1924 build_append_int_noprefix(table_data, 0, 8);
1925
1926 /* allocate/reserve space for TPM log area */
1927 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1928 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1929 false /* high memory */);
1930 /* log area start address to be filled by Guest linker */
1931 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1932 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1933
1934 acpi_table_end(linker, &table);
1935 }
1936 #endif
1937
1938 #define HOLE_640K_START (640 * KiB)
1939 #define HOLE_640K_END (1 * MiB)
1940
1941 /*
1942 * ACPI spec, Revision 3.0
1943 * 5.2.15 System Resource Affinity Table (SRAT)
1944 */
1945 static void
1946 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1947 {
1948 int i;
1949 int numa_mem_start, slots;
1950 uint64_t mem_len, mem_base, next_base;
1951 MachineClass *mc = MACHINE_GET_CLASS(machine);
1952 X86MachineState *x86ms = X86_MACHINE(machine);
1953 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1954 int nb_numa_nodes = machine->numa_state->num_nodes;
1955 NodeInfo *numa_info = machine->numa_state->nodes;
1956 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1957 .oem_table_id = x86ms->oem_table_id };
1958
1959 acpi_table_begin(&table, table_data);
1960 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1961 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1962
1963 for (i = 0; i < apic_ids->len; i++) {
1964 int node_id = apic_ids->cpus[i].props.node_id;
1965 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1966
1967 if (apic_id < 255) {
1968 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1969 build_append_int_noprefix(table_data, 0, 1); /* Type */
1970 build_append_int_noprefix(table_data, 16, 1); /* Length */
1971 /* Proximity Domain [7:0] */
1972 build_append_int_noprefix(table_data, node_id, 1);
1973 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1974 /* Flags, Table 5-36 */
1975 build_append_int_noprefix(table_data, 1, 4);
1976 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1977 /* Proximity Domain [31:8] */
1978 build_append_int_noprefix(table_data, 0, 3);
1979 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1980 } else {
1981 /*
1982 * ACPI spec, Revision 4.0
1983 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1984 */
1985 build_append_int_noprefix(table_data, 2, 1); /* Type */
1986 build_append_int_noprefix(table_data, 24, 1); /* Length */
1987 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1988 /* Proximity Domain */
1989 build_append_int_noprefix(table_data, node_id, 4);
1990 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1991 /* Flags, Table 5-39 */
1992 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1993 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1994 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1995 }
1996 }
1997
1998 /* the memory map is a bit tricky, it contains at least one hole
1999 * from 640k-1M and possibly another one from 3.5G-4G.
2000 */
2001 next_base = 0;
2002 numa_mem_start = table_data->len;
2003
2004 for (i = 1; i < nb_numa_nodes + 1; ++i) {
2005 mem_base = next_base;
2006 mem_len = numa_info[i - 1].node_mem;
2007 next_base = mem_base + mem_len;
2008
2009 /* Cut out the 640K hole */
2010 if (mem_base <= HOLE_640K_START &&
2011 next_base > HOLE_640K_START) {
2012 mem_len -= next_base - HOLE_640K_START;
2013 if (mem_len > 0) {
2014 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2015 MEM_AFFINITY_ENABLED);
2016 }
2017
2018 /* Check for the rare case: 640K < RAM < 1M */
2019 if (next_base <= HOLE_640K_END) {
2020 next_base = HOLE_640K_END;
2021 continue;
2022 }
2023 mem_base = HOLE_640K_END;
2024 mem_len = next_base - HOLE_640K_END;
2025 }
2026
2027 /* Cut out the ACPI_PCI hole */
2028 if (mem_base <= x86ms->below_4g_mem_size &&
2029 next_base > x86ms->below_4g_mem_size) {
2030 mem_len -= next_base - x86ms->below_4g_mem_size;
2031 if (mem_len > 0) {
2032 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2033 MEM_AFFINITY_ENABLED);
2034 }
2035 mem_base = x86ms->above_4g_mem_start;
2036 mem_len = next_base - x86ms->below_4g_mem_size;
2037 next_base = mem_base + mem_len;
2038 }
2039
2040 if (mem_len > 0) {
2041 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2042 MEM_AFFINITY_ENABLED);
2043 }
2044 }
2045
2046 if (machine->nvdimms_state->is_enabled) {
2047 nvdimm_build_srat(table_data);
2048 }
2049
2050 sgx_epc_build_srat(table_data);
2051
2052 /*
2053 * TODO: this part is not in ACPI spec and current linux kernel boots fine
2054 * without these entries. But I recall there were issues the last time I
2055 * tried to remove it with some ancient guest OS, however I can't remember
2056 * what that was so keep this around for now
2057 */
2058 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
2059 for (; slots < nb_numa_nodes + 2; slots++) {
2060 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2061 }
2062
2063 /*
2064 * Entry is required for Windows to enable memory hotplug in OS
2065 * and for Linux to enable SWIOTLB when booted with less than
2066 * 4G of RAM. Windows works better if the entry sets proximity
2067 * to the highest NUMA node in the machine.
2068 * Memory devices may override proximity set by this entry,
2069 * providing _PXM method if necessary.
2070 */
2071 if (machine->device_memory) {
2072 build_srat_memory(table_data, machine->device_memory->base,
2073 memory_region_size(&machine->device_memory->mr),
2074 nb_numa_nodes - 1,
2075 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2076 }
2077
2078 acpi_table_end(linker, &table);
2079 }
2080
2081 /*
2082 * Insert DMAR scope for PCI bridges and endpoint devcie
2083 */
2084 static void
2085 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2086 {
2087 const size_t device_scope_size = 6 /* device scope structure */ +
2088 2 /* 1 path entry */;
2089 GArray *scope_blob = opaque;
2090
2091 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2092 /* Dmar Scope Type: 0x02 for PCI Bridge */
2093 build_append_int_noprefix(scope_blob, 0x02, 1);
2094 } else {
2095 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2096 build_append_int_noprefix(scope_blob, 0x01, 1);
2097 }
2098
2099 /* length */
2100 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2101 /* reserved */
2102 build_append_int_noprefix(scope_blob, 0, 2);
2103 /* enumeration_id */
2104 build_append_int_noprefix(scope_blob, 0, 1);
2105 /* bus */
2106 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2107 /* device */
2108 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2109 /* function */
2110 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2111 }
2112
2113 /* For a given PCI host bridge, walk and insert DMAR scope */
2114 static int
2115 dmar_host_bridges(Object *obj, void *opaque)
2116 {
2117 GArray *scope_blob = opaque;
2118
2119 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2120 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2121
2122 if (bus && !pci_bus_bypass_iommu(bus)) {
2123 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2124 }
2125 }
2126
2127 return 0;
2128 }
2129
2130 /*
2131 * Intel ® Virtualization Technology for Directed I/O
2132 * Architecture Specification. Revision 3.3
2133 * 8.1 DMA Remapping Reporting Structure
2134 */
2135 static void
2136 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2137 const char *oem_table_id)
2138 {
2139 uint8_t dmar_flags = 0;
2140 uint8_t rsvd10[10] = {};
2141 /* Root complex IOAPIC uses one path only */
2142 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2143 2 /* 1 path entry */;
2144 X86IOMMUState *iommu = x86_iommu_get_default();
2145 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2146 GArray *scope_blob = g_array_new(false, true, 1);
2147
2148 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2149 .oem_table_id = oem_table_id };
2150
2151 /*
2152 * A PCI bus walk, for each PCI host bridge.
2153 * Insert scope for each PCI bridge and endpoint device which
2154 * is attached to a bus with iommu enabled.
2155 */
2156 object_child_foreach_recursive(object_get_root(),
2157 dmar_host_bridges, scope_blob);
2158
2159 assert(iommu);
2160 if (x86_iommu_ir_supported(iommu)) {
2161 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2162 }
2163
2164 acpi_table_begin(&table, table_data);
2165 /* Host Address Width */
2166 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2167 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2168 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2169
2170 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2171 build_append_int_noprefix(table_data, 0, 2); /* Type */
2172 /* Length */
2173 build_append_int_noprefix(table_data,
2174 16 + ioapic_scope_size + scope_blob->len, 2);
2175 /* Flags */
2176 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2177 1);
2178 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2179 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2180 /* Register Base Address */
2181 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2182
2183 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2184 * 8.3.1 (version Oct. 2014 or later). */
2185 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2186 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2187 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2188 /* Enumeration ID */
2189 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2190 /* Start Bus Number */
2191 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2192 /* Path, {Device, Function} pair */
2193 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2194 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2195
2196 /* Add scope found above */
2197 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2198 g_array_free(scope_blob, true);
2199
2200 if (iommu->dt_supported) {
2201 /* 8.5 Root Port ATS Capability Reporting Structure */
2202 build_append_int_noprefix(table_data, 2, 2); /* Type */
2203 build_append_int_noprefix(table_data, 8, 2); /* Length */
2204 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2205 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2206 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2207 }
2208
2209 acpi_table_end(linker, &table);
2210 }
2211
2212 /*
2213 * Windows ACPI Emulated Devices Table
2214 * (Version 1.0 - April 6, 2009)
2215 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2216 *
2217 * Helpful to speedup Windows guests and ignored by others.
2218 */
2219 static void
2220 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2221 const char *oem_table_id)
2222 {
2223 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2224 .oem_table_id = oem_table_id };
2225
2226 acpi_table_begin(&table, table_data);
2227 /*
2228 * Set "ACPI PM timer good" flag.
2229 *
2230 * Tells Windows guests that our ACPI PM timer is reliable in the
2231 * sense that guest can read it only once to obtain a reliable value.
2232 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2233 */
2234 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2235 acpi_table_end(linker, &table);
2236 }
2237
2238 /*
2239 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2240 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2241 */
2242 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2243
2244 /*
2245 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2246 * necessary for the PCI topology.
2247 */
2248 static void
2249 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2250 {
2251 GArray *table_data = opaque;
2252 uint32_t entry;
2253
2254 /* "Select" IVHD entry, type 0x2 */
2255 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2256 build_append_int_noprefix(table_data, entry, 4);
2257
2258 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2259 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2260 uint8_t sec = pci_bus_num(sec_bus);
2261 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2262
2263 if (pci_bus_is_express(sec_bus)) {
2264 /*
2265 * Walk the bus if there are subordinates, otherwise use a range
2266 * to cover an entire leaf bus. We could potentially also use a
2267 * range for traversed buses, but we'd need to take care not to
2268 * create both Select and Range entries covering the same device.
2269 * This is easier and potentially more compact.
2270 *
2271 * An example bare metal system seems to use Select entries for
2272 * root ports without a slot (ie. built-ins) and Range entries
2273 * when there is a slot. The same system also only hard-codes
2274 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2275 * making no effort to support nested bridges. We attempt to
2276 * be more thorough here.
2277 */
2278 if (sec == sub) { /* leaf bus */
2279 /* "Start of Range" IVHD entry, type 0x3 */
2280 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2281 build_append_int_noprefix(table_data, entry, 4);
2282 /* "End of Range" IVHD entry, type 0x4 */
2283 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2284 build_append_int_noprefix(table_data, entry, 4);
2285 } else {
2286 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2287 }
2288 } else {
2289 /*
2290 * If the secondary bus is conventional, then we need to create an
2291 * Alias range for everything downstream. The range covers the
2292 * first devfn on the secondary bus to the last devfn on the
2293 * subordinate bus. The alias target depends on legacy versus
2294 * express bridges, just as in pci_device_iommu_address_space().
2295 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2296 */
2297 uint16_t dev_id_a, dev_id_b;
2298
2299 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2300
2301 if (pci_is_express(dev) &&
2302 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2303 dev_id_b = dev_id_a;
2304 } else {
2305 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2306 }
2307
2308 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2309 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2310 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2311
2312 /* "End of Range" IVHD entry, type 0x4 */
2313 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2314 build_append_int_noprefix(table_data, entry, 4);
2315 }
2316 }
2317 }
2318
2319 /* For all PCI host bridges, walk and insert IVHD entries */
2320 static int
2321 ivrs_host_bridges(Object *obj, void *opaque)
2322 {
2323 GArray *ivhd_blob = opaque;
2324
2325 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2326 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2327
2328 if (bus && !pci_bus_bypass_iommu(bus)) {
2329 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2330 }
2331 }
2332
2333 return 0;
2334 }
2335
2336 static void
2337 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2338 const char *oem_table_id)
2339 {
2340 int ivhd_table_len = 24;
2341 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2342 GArray *ivhd_blob = g_array_new(false, true, 1);
2343 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2344 .oem_table_id = oem_table_id };
2345
2346 acpi_table_begin(&table, table_data);
2347 /* IVinfo - IO virtualization information common to all
2348 * IOMMU units in a system
2349 */
2350 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2351 /* reserved */
2352 build_append_int_noprefix(table_data, 0, 8);
2353
2354 /* IVHD definition - type 10h */
2355 build_append_int_noprefix(table_data, 0x10, 1);
2356 /* virtualization flags */
2357 build_append_int_noprefix(table_data,
2358 (1UL << 0) | /* HtTunEn */
2359 (1UL << 4) | /* iotblSup */
2360 (1UL << 6) | /* PrefSup */
2361 (1UL << 7), /* PPRSup */
2362 1);
2363
2364 /*
2365 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2366 * complete set of IVHD entries. Do this into a separate blob so that we
2367 * can calculate the total IVRS table length here and then append the new
2368 * blob further below. Fall back to an entry covering all devices, which
2369 * is sufficient when no aliases are present.
2370 */
2371 object_child_foreach_recursive(object_get_root(),
2372 ivrs_host_bridges, ivhd_blob);
2373
2374 if (!ivhd_blob->len) {
2375 /*
2376 * Type 1 device entry reporting all devices
2377 * These are 4-byte device entries currently reporting the range of
2378 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2379 */
2380 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2381 }
2382
2383 ivhd_table_len += ivhd_blob->len;
2384
2385 /*
2386 * When interrupt remapping is supported, we add a special IVHD device
2387 * for type IO-APIC.
2388 */
2389 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2390 ivhd_table_len += 8;
2391 }
2392
2393 /* IVHD length */
2394 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2395 /* DeviceID */
2396 build_append_int_noprefix(table_data,
2397 object_property_get_int(OBJECT(&s->pci), "addr",
2398 &error_abort), 2);
2399 /* Capability offset */
2400 build_append_int_noprefix(table_data, s->pci.capab_offset, 2);
2401 /* IOMMU base address */
2402 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2403 /* PCI Segment Group */
2404 build_append_int_noprefix(table_data, 0, 2);
2405 /* IOMMU info */
2406 build_append_int_noprefix(table_data, 0, 2);
2407 /* IOMMU Feature Reporting */
2408 build_append_int_noprefix(table_data,
2409 (48UL << 30) | /* HATS */
2410 (48UL << 28) | /* GATS */
2411 (1UL << 2) | /* GTSup */
2412 (1UL << 6), /* GASup */
2413 4);
2414
2415 /* IVHD entries as found above */
2416 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2417 g_array_free(ivhd_blob, TRUE);
2418
2419 /*
2420 * Add a special IVHD device type.
2421 * Refer to spec - Table 95: IVHD device entry type codes
2422 *
2423 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2424 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2425 */
2426 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2427 build_append_int_noprefix(table_data,
2428 (0x1ull << 56) | /* type IOAPIC */
2429 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2430 0x48, /* special device */
2431 8);
2432 }
2433 acpi_table_end(linker, &table);
2434 }
2435
2436 typedef
2437 struct AcpiBuildState {
2438 /* Copy of table in RAM (for patching). */
2439 MemoryRegion *table_mr;
2440 /* Is table patched? */
2441 uint8_t patched;
2442 void *rsdp;
2443 MemoryRegion *rsdp_mr;
2444 MemoryRegion *linker_mr;
2445 } AcpiBuildState;
2446
2447 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2448 {
2449 Object *pci_host;
2450 QObject *o;
2451
2452 pci_host = acpi_get_i386_pci_host();
2453 if (!pci_host) {
2454 return false;
2455 }
2456
2457 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2458 if (!o) {
2459 return false;
2460 }
2461 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2462 qobject_unref(o);
2463 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2464 return false;
2465 }
2466
2467 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2468 assert(o);
2469 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2470 qobject_unref(o);
2471 return true;
2472 }
2473
2474 static
2475 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2476 {
2477 PCMachineState *pcms = PC_MACHINE(machine);
2478 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2479 X86MachineState *x86ms = X86_MACHINE(machine);
2480 DeviceState *iommu = pcms->iommu;
2481 GArray *table_offsets;
2482 unsigned facs, dsdt, rsdt, fadt;
2483 AcpiPmInfo pm;
2484 AcpiMiscInfo misc;
2485 AcpiMcfgInfo mcfg;
2486 Range pci_hole = {}, pci_hole64 = {};
2487 uint8_t *u;
2488 size_t aml_len = 0;
2489 GArray *tables_blob = tables->table_data;
2490 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2491 Object *vmgenid_dev;
2492 char *oem_id;
2493 char *oem_table_id;
2494
2495 acpi_get_pm_info(machine, &pm);
2496 acpi_get_misc_info(&misc);
2497 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2498 acpi_get_slic_oem(&slic_oem);
2499
2500 if (slic_oem.id) {
2501 oem_id = slic_oem.id;
2502 } else {
2503 oem_id = x86ms->oem_id;
2504 }
2505
2506 if (slic_oem.table_id) {
2507 oem_table_id = slic_oem.table_id;
2508 } else {
2509 oem_table_id = x86ms->oem_table_id;
2510 }
2511
2512 table_offsets = g_array_new(false, true /* clear */,
2513 sizeof(uint32_t));
2514 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2515
2516 bios_linker_loader_alloc(tables->linker,
2517 ACPI_BUILD_TABLE_FILE, tables_blob,
2518 64 /* Ensure FACS is aligned */,
2519 false /* high memory */);
2520
2521 /*
2522 * FACS is pointed to by FADT.
2523 * We place it first since it's the only table that has alignment
2524 * requirements.
2525 */
2526 facs = tables_blob->len;
2527 build_facs(tables_blob);
2528
2529 /* DSDT is pointed to by FADT */
2530 dsdt = tables_blob->len;
2531 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2532 &pci_hole, &pci_hole64, machine);
2533
2534 /* Count the size of the DSDT and SSDT, we will need it for legacy
2535 * sizing of ACPI tables.
2536 */
2537 aml_len += tables_blob->len - dsdt;
2538
2539 /* ACPI tables pointed to by RSDT */
2540 fadt = tables_blob->len;
2541 acpi_add_table(table_offsets, tables_blob);
2542 pm.fadt.facs_tbl_offset = &facs;
2543 pm.fadt.dsdt_tbl_offset = &dsdt;
2544 pm.fadt.xdsdt_tbl_offset = &dsdt;
2545 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2546 aml_len += tables_blob->len - fadt;
2547
2548 acpi_add_table(table_offsets, tables_blob);
2549 acpi_build_madt(tables_blob, tables->linker, x86ms,
2550 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2551 x86ms->oem_table_id);
2552
2553 #ifdef CONFIG_ACPI_ERST
2554 {
2555 Object *erst_dev;
2556 erst_dev = find_erst_dev();
2557 if (erst_dev) {
2558 acpi_add_table(table_offsets, tables_blob);
2559 build_erst(tables_blob, tables->linker, erst_dev,
2560 x86ms->oem_id, x86ms->oem_table_id);
2561 }
2562 }
2563 #endif
2564
2565 vmgenid_dev = find_vmgenid_dev();
2566 if (vmgenid_dev) {
2567 acpi_add_table(table_offsets, tables_blob);
2568 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2569 tables->vmgenid, tables->linker, x86ms->oem_id);
2570 }
2571
2572 if (misc.has_hpet) {
2573 acpi_add_table(table_offsets, tables_blob);
2574 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2575 x86ms->oem_table_id);
2576 }
2577 #ifdef CONFIG_TPM
2578 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2579 if (misc.tpm_version == TPM_VERSION_1_2) {
2580 acpi_add_table(table_offsets, tables_blob);
2581 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2582 x86ms->oem_id, x86ms->oem_table_id);
2583 } else { /* TPM_VERSION_2_0 */
2584 acpi_add_table(table_offsets, tables_blob);
2585 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2586 x86ms->oem_id, x86ms->oem_table_id);
2587 }
2588 }
2589 #endif
2590 if (machine->numa_state->num_nodes) {
2591 acpi_add_table(table_offsets, tables_blob);
2592 build_srat(tables_blob, tables->linker, machine);
2593 if (machine->numa_state->have_numa_distance) {
2594 acpi_add_table(table_offsets, tables_blob);
2595 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2596 x86ms->oem_table_id);
2597 }
2598 if (machine->numa_state->hmat_enabled) {
2599 acpi_add_table(table_offsets, tables_blob);
2600 build_hmat(tables_blob, tables->linker, machine->numa_state,
2601 x86ms->oem_id, x86ms->oem_table_id);
2602 }
2603 }
2604 if (acpi_get_mcfg(&mcfg)) {
2605 acpi_add_table(table_offsets, tables_blob);
2606 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2607 x86ms->oem_table_id);
2608 }
2609 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2610 acpi_add_table(table_offsets, tables_blob);
2611 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2612 x86ms->oem_table_id);
2613 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2614 acpi_add_table(table_offsets, tables_blob);
2615 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2616 x86ms->oem_table_id);
2617 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2618 PCIDevice *pdev = PCI_DEVICE(iommu);
2619
2620 acpi_add_table(table_offsets, tables_blob);
2621 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2622 x86ms->oem_id, x86ms->oem_table_id);
2623 }
2624 if (machine->nvdimms_state->is_enabled) {
2625 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2626 machine->nvdimms_state, machine->ram_slots,
2627 x86ms->oem_id, x86ms->oem_table_id);
2628 }
2629 if (pcms->cxl_devices_state.is_enabled) {
2630 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2631 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2632 }
2633
2634 acpi_add_table(table_offsets, tables_blob);
2635 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2636
2637 /* Add tables supplied by user (if any) */
2638 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2639 unsigned len = acpi_table_len(u);
2640
2641 acpi_add_table(table_offsets, tables_blob);
2642 g_array_append_vals(tables_blob, u, len);
2643 }
2644
2645 /* RSDT is pointed to by RSDP */
2646 rsdt = tables_blob->len;
2647 build_rsdt(tables_blob, tables->linker, table_offsets,
2648 oem_id, oem_table_id);
2649
2650 /* RSDP is in FSEG memory, so allocate it separately */
2651 {
2652 AcpiRsdpData rsdp_data = {
2653 .revision = 0,
2654 .oem_id = x86ms->oem_id,
2655 .xsdt_tbl_offset = NULL,
2656 .rsdt_tbl_offset = &rsdt,
2657 };
2658 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2659 if (!pcmc->rsdp_in_ram) {
2660 /* We used to allocate some extra space for RSDP revision 2 but
2661 * only used the RSDP revision 0 space. The extra bytes were
2662 * zeroed out and not used.
2663 * Here we continue wasting those extra 16 bytes to make sure we
2664 * don't break migration for machine types 2.2 and older due to
2665 * RSDP blob size mismatch.
2666 */
2667 build_append_int_noprefix(tables->rsdp, 0, 16);
2668 }
2669 }
2670
2671 /* We'll expose it all to Guest so we want to reduce
2672 * chance of size changes.
2673 *
2674 * We used to align the tables to 4k, but of course this would
2675 * too simple to be enough. 4k turned out to be too small an
2676 * alignment very soon, and in fact it is almost impossible to
2677 * keep the table size stable for all (max_cpus, max_memory_slots)
2678 * combinations. So the table size is always 64k for pc-i440fx-2.1
2679 * and we give an error if the table grows beyond that limit.
2680 *
2681 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2682 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2683 * than 2.0 and we can always pad the smaller tables with zeros. We can
2684 * then use the exact size of the 2.0 tables.
2685 *
2686 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2687 */
2688 if (pcmc->legacy_acpi_table_size) {
2689 /* Subtracting aml_len gives the size of fixed tables. Then add the
2690 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2691 */
2692 int legacy_aml_len =
2693 pcmc->legacy_acpi_table_size +
2694 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2695 int legacy_table_size =
2696 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2697 ACPI_BUILD_ALIGN_SIZE);
2698 if ((tables_blob->len > legacy_table_size) &&
2699 !pcmc->resizable_acpi_blob) {
2700 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2701 warn_report("ACPI table size %u exceeds %d bytes,"
2702 " migration may not work",
2703 tables_blob->len, legacy_table_size);
2704 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2705 " or PCI bridges.");
2706 }
2707 g_array_set_size(tables_blob, legacy_table_size);
2708 } else {
2709 /* Make sure we have a buffer in case we need to resize the tables. */
2710 if ((tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) &&
2711 !pcmc->resizable_acpi_blob) {
2712 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2713 warn_report("ACPI table size %u exceeds %d bytes,"
2714 " migration may not work",
2715 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2716 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2717 " or PCI bridges.");
2718 }
2719 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2720 }
2721
2722 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2723
2724 /* Cleanup memory that's no longer used. */
2725 g_array_free(table_offsets, true);
2726 g_free(slic_oem.id);
2727 g_free(slic_oem.table_id);
2728 }
2729
2730 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2731 {
2732 uint32_t size = acpi_data_len(data);
2733
2734 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2735 memory_region_ram_resize(mr, size, &error_abort);
2736
2737 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2738 memory_region_set_dirty(mr, 0, size);
2739 }
2740
2741 static void acpi_build_update(void *build_opaque)
2742 {
2743 AcpiBuildState *build_state = build_opaque;
2744 AcpiBuildTables tables;
2745
2746 /* No state to update or already patched? Nothing to do. */
2747 if (!build_state || build_state->patched) {
2748 return;
2749 }
2750 build_state->patched = 1;
2751
2752 acpi_build_tables_init(&tables);
2753
2754 acpi_build(&tables, MACHINE(qdev_get_machine()));
2755
2756 acpi_ram_update(build_state->table_mr, tables.table_data);
2757
2758 if (build_state->rsdp) {
2759 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2760 } else {
2761 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2762 }
2763
2764 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2765 acpi_build_tables_cleanup(&tables, true);
2766 }
2767
2768 static void acpi_build_reset(void *build_opaque)
2769 {
2770 AcpiBuildState *build_state = build_opaque;
2771 build_state->patched = 0;
2772 }
2773
2774 static const VMStateDescription vmstate_acpi_build = {
2775 .name = "acpi_build",
2776 .version_id = 1,
2777 .minimum_version_id = 1,
2778 .fields = (VMStateField[]) {
2779 VMSTATE_UINT8(patched, AcpiBuildState),
2780 VMSTATE_END_OF_LIST()
2781 },
2782 };
2783
2784 void acpi_setup(void)
2785 {
2786 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2787 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2788 X86MachineState *x86ms = X86_MACHINE(pcms);
2789 AcpiBuildTables tables;
2790 AcpiBuildState *build_state;
2791 Object *vmgenid_dev;
2792 #ifdef CONFIG_TPM
2793 TPMIf *tpm;
2794 static FwCfgTPMConfig tpm_config;
2795 #endif
2796
2797 if (!x86ms->fw_cfg) {
2798 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2799 return;
2800 }
2801
2802 if (!pcms->acpi_build_enabled) {
2803 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2804 return;
2805 }
2806
2807 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2808 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2809 return;
2810 }
2811
2812 build_state = g_malloc0(sizeof *build_state);
2813
2814 acpi_build_tables_init(&tables);
2815 acpi_build(&tables, MACHINE(pcms));
2816
2817 /* Now expose it all to Guest */
2818 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2819 build_state, tables.table_data,
2820 ACPI_BUILD_TABLE_FILE);
2821 assert(build_state->table_mr != NULL);
2822
2823 build_state->linker_mr =
2824 acpi_add_rom_blob(acpi_build_update, build_state,
2825 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2826
2827 #ifdef CONFIG_TPM
2828 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2829 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2830
2831 tpm = tpm_find();
2832 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2833 tpm_config = (FwCfgTPMConfig) {
2834 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2835 .tpm_version = tpm_get_version(tpm),
2836 .tpmppi_version = TPM_PPI_VERSION_1_30
2837 };
2838 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2839 &tpm_config, sizeof tpm_config);
2840 }
2841 #endif
2842
2843 vmgenid_dev = find_vmgenid_dev();
2844 if (vmgenid_dev) {
2845 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2846 tables.vmgenid);
2847 }
2848
2849 if (!pcmc->rsdp_in_ram) {
2850 /*
2851 * Keep for compatibility with old machine types.
2852 * Though RSDP is small, its contents isn't immutable, so
2853 * we'll update it along with the rest of tables on guest access.
2854 */
2855 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2856
2857 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2858 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2859 acpi_build_update, NULL, build_state,
2860 build_state->rsdp, rsdp_size, true);
2861 build_state->rsdp_mr = NULL;
2862 } else {
2863 build_state->rsdp = NULL;
2864 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2865 build_state, tables.rsdp,
2866 ACPI_BUILD_RSDP_FILE);
2867 }
2868
2869 qemu_register_reset(acpi_build_reset, build_state);
2870 acpi_build_reset(build_state);
2871 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2872
2873 /* Cleanup tables but don't free the memory: we track it
2874 * in build_state.
2875 */
2876 acpi_build_tables_cleanup(&tables, false);
2877 }
Eric Blake's pending patches to qemu