4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Generate inline load/store functions for all MMU modes (typically
21 * at least _user and _kernel) as well as _data versions, for all data
24 * Used by target op helpers.
26 * The syntax for the accessors is:
28 * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
30 * store: cpu_st{sign}{size}_{mmusuffix}(env, ptr, val)
33 * (empty): for 32 and 64 bit sizes
43 * mmusuffix is one of the generic suffixes "data" or "code", or
44 * (for softmmu configs) a target-specific MMU mode suffix as defined
50 #if defined(CONFIG_USER_ONLY)
51 /* sparc32plus has 64bit long but 32bit space address
52 * this can make bad result with g2h() and h2g()
54 #if TARGET_VIRT_ADDR_SPACE_BITS <= 32
55 typedef uint32_t abi_ptr
;
56 #define TARGET_ABI_FMT_ptr "%x"
58 typedef uint64_t abi_ptr
;
59 #define TARGET_ABI_FMT_ptr "%"PRIx64
62 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
63 #define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + guest_base))
65 #define guest_addr_valid(x) ((x) <= GUEST_ADDR_MAX)
66 #define h2g_valid(x) guest_addr_valid((unsigned long)(x) - guest_base)
68 static inline int guest_range_valid(unsigned long start
, unsigned long len
)
70 return len
- 1 <= GUEST_ADDR_MAX
&& start
<= GUEST_ADDR_MAX
- len
+ 1;
73 #define h2g_nocheck(x) ({ \
74 unsigned long __ret = (unsigned long)(x) - guest_base; \
79 /* Check if given address fits target address space */ \
80 assert(h2g_valid(x)); \
84 typedef target_ulong abi_ptr
;
85 #define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
88 #if defined(CONFIG_USER_ONLY)
90 extern __thread
uintptr_t helper_retaddr
;
92 /* In user-only mode we provide only the _code and _data accessors. */
94 #define MEMSUFFIX _data
96 #include "exec/cpu_ldst_useronly_template.h"
99 #include "exec/cpu_ldst_useronly_template.h"
102 #include "exec/cpu_ldst_useronly_template.h"
105 #include "exec/cpu_ldst_useronly_template.h"
108 #define MEMSUFFIX _code
111 #include "exec/cpu_ldst_useronly_template.h"
114 #include "exec/cpu_ldst_useronly_template.h"
117 #include "exec/cpu_ldst_useronly_template.h"
120 #include "exec/cpu_ldst_useronly_template.h"
126 /* The memory helpers for tcg-generated code need tcg_target_long etc. */
129 static inline target_ulong
tlb_addr_write(const CPUTLBEntry
*entry
)
131 #if TCG_OVERSIZED_GUEST
132 return entry
->addr_write
;
134 return atomic_read(&entry
->addr_write
);
138 /* Find the TLB index corresponding to the mmu_idx + address pair. */
139 static inline uintptr_t tlb_index(CPUArchState
*env
, uintptr_t mmu_idx
,
142 uintptr_t size_mask
= env
->tlb_mask
[mmu_idx
] >> CPU_TLB_ENTRY_BITS
;
144 return (addr
>> TARGET_PAGE_BITS
) & size_mask
;
147 static inline size_t tlb_n_entries(CPUArchState
*env
, uintptr_t mmu_idx
)
149 return (env
->tlb_mask
[mmu_idx
] >> CPU_TLB_ENTRY_BITS
) + 1;
152 /* Find the TLB entry corresponding to the mmu_idx + address pair. */
153 static inline CPUTLBEntry
*tlb_entry(CPUArchState
*env
, uintptr_t mmu_idx
,
156 return &env
->tlb_table
[mmu_idx
][tlb_index(env
, mmu_idx
, addr
)];
159 #ifdef MMU_MODE0_SUFFIX
160 #define CPU_MMU_INDEX 0
161 #define MEMSUFFIX MMU_MODE0_SUFFIX
163 #include "exec/cpu_ldst_template.h"
166 #include "exec/cpu_ldst_template.h"
169 #include "exec/cpu_ldst_template.h"
172 #include "exec/cpu_ldst_template.h"
177 #if (NB_MMU_MODES >= 2) && defined(MMU_MODE1_SUFFIX)
178 #define CPU_MMU_INDEX 1
179 #define MEMSUFFIX MMU_MODE1_SUFFIX
181 #include "exec/cpu_ldst_template.h"
184 #include "exec/cpu_ldst_template.h"
187 #include "exec/cpu_ldst_template.h"
190 #include "exec/cpu_ldst_template.h"
195 #if (NB_MMU_MODES >= 3) && defined(MMU_MODE2_SUFFIX)
197 #define CPU_MMU_INDEX 2
198 #define MEMSUFFIX MMU_MODE2_SUFFIX
200 #include "exec/cpu_ldst_template.h"
203 #include "exec/cpu_ldst_template.h"
206 #include "exec/cpu_ldst_template.h"
209 #include "exec/cpu_ldst_template.h"
212 #endif /* (NB_MMU_MODES >= 3) */
214 #if (NB_MMU_MODES >= 4) && defined(MMU_MODE3_SUFFIX)
216 #define CPU_MMU_INDEX 3
217 #define MEMSUFFIX MMU_MODE3_SUFFIX
219 #include "exec/cpu_ldst_template.h"
222 #include "exec/cpu_ldst_template.h"
225 #include "exec/cpu_ldst_template.h"
228 #include "exec/cpu_ldst_template.h"
231 #endif /* (NB_MMU_MODES >= 4) */
233 #if (NB_MMU_MODES >= 5) && defined(MMU_MODE4_SUFFIX)
235 #define CPU_MMU_INDEX 4
236 #define MEMSUFFIX MMU_MODE4_SUFFIX
238 #include "exec/cpu_ldst_template.h"
241 #include "exec/cpu_ldst_template.h"
244 #include "exec/cpu_ldst_template.h"
247 #include "exec/cpu_ldst_template.h"
250 #endif /* (NB_MMU_MODES >= 5) */
252 #if (NB_MMU_MODES >= 6) && defined(MMU_MODE5_SUFFIX)
254 #define CPU_MMU_INDEX 5
255 #define MEMSUFFIX MMU_MODE5_SUFFIX
257 #include "exec/cpu_ldst_template.h"
260 #include "exec/cpu_ldst_template.h"
263 #include "exec/cpu_ldst_template.h"
266 #include "exec/cpu_ldst_template.h"
269 #endif /* (NB_MMU_MODES >= 6) */
271 #if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
273 #define CPU_MMU_INDEX 6
274 #define MEMSUFFIX MMU_MODE6_SUFFIX
276 #include "exec/cpu_ldst_template.h"
279 #include "exec/cpu_ldst_template.h"
282 #include "exec/cpu_ldst_template.h"
285 #include "exec/cpu_ldst_template.h"
288 #endif /* (NB_MMU_MODES >= 7) */
290 #if (NB_MMU_MODES >= 8) && defined(MMU_MODE7_SUFFIX)
292 #define CPU_MMU_INDEX 7
293 #define MEMSUFFIX MMU_MODE7_SUFFIX
295 #include "exec/cpu_ldst_template.h"
298 #include "exec/cpu_ldst_template.h"
301 #include "exec/cpu_ldst_template.h"
304 #include "exec/cpu_ldst_template.h"
307 #endif /* (NB_MMU_MODES >= 8) */
309 #if (NB_MMU_MODES >= 9) && defined(MMU_MODE8_SUFFIX)
311 #define CPU_MMU_INDEX 8
312 #define MEMSUFFIX MMU_MODE8_SUFFIX
314 #include "exec/cpu_ldst_template.h"
317 #include "exec/cpu_ldst_template.h"
320 #include "exec/cpu_ldst_template.h"
323 #include "exec/cpu_ldst_template.h"
326 #endif /* (NB_MMU_MODES >= 9) */
328 #if (NB_MMU_MODES >= 10) && defined(MMU_MODE9_SUFFIX)
330 #define CPU_MMU_INDEX 9
331 #define MEMSUFFIX MMU_MODE9_SUFFIX
333 #include "exec/cpu_ldst_template.h"
336 #include "exec/cpu_ldst_template.h"
339 #include "exec/cpu_ldst_template.h"
342 #include "exec/cpu_ldst_template.h"
345 #endif /* (NB_MMU_MODES >= 10) */
347 #if (NB_MMU_MODES >= 11) && defined(MMU_MODE10_SUFFIX)
349 #define CPU_MMU_INDEX 10
350 #define MEMSUFFIX MMU_MODE10_SUFFIX
352 #include "exec/cpu_ldst_template.h"
355 #include "exec/cpu_ldst_template.h"
358 #include "exec/cpu_ldst_template.h"
361 #include "exec/cpu_ldst_template.h"
364 #endif /* (NB_MMU_MODES >= 11) */
366 #if (NB_MMU_MODES >= 12) && defined(MMU_MODE11_SUFFIX)
368 #define CPU_MMU_INDEX 11
369 #define MEMSUFFIX MMU_MODE11_SUFFIX
371 #include "exec/cpu_ldst_template.h"
374 #include "exec/cpu_ldst_template.h"
377 #include "exec/cpu_ldst_template.h"
380 #include "exec/cpu_ldst_template.h"
383 #endif /* (NB_MMU_MODES >= 12) */
385 #if (NB_MMU_MODES > 12)
386 #error "NB_MMU_MODES > 12 is not supported for now"
387 #endif /* (NB_MMU_MODES > 12) */
389 /* these access are slower, they must be as rare as possible */
390 #define CPU_MMU_INDEX (cpu_mmu_index(env, false))
391 #define MEMSUFFIX _data
393 #include "exec/cpu_ldst_template.h"
396 #include "exec/cpu_ldst_template.h"
399 #include "exec/cpu_ldst_template.h"
402 #include "exec/cpu_ldst_template.h"
406 #define CPU_MMU_INDEX (cpu_mmu_index(env, true))
407 #define MEMSUFFIX _code
408 #define SOFTMMU_CODE_ACCESS
411 #include "exec/cpu_ldst_template.h"
414 #include "exec/cpu_ldst_template.h"
417 #include "exec/cpu_ldst_template.h"
420 #include "exec/cpu_ldst_template.h"
424 #undef SOFTMMU_CODE_ACCESS
426 #endif /* defined(CONFIG_USER_ONLY) */
431 * @addr: guest virtual address to look up
432 * @access_type: 0 for read, 1 for write, 2 for execute
433 * @mmu_idx: MMU index to use for lookup
435 * Look up the specified guest virtual index in the TCG softmmu TLB.
436 * If the TLB contains a host virtual address suitable for direct RAM
437 * access, then return it. Otherwise (TLB miss, TLB entry is for an
438 * I/O access, etc) return NULL.
440 * This is the equivalent of the initial fast-path code used by
441 * TCG backends for guest load and store accesses.
443 static inline void *tlb_vaddr_to_host(CPUArchState
*env
, abi_ptr addr
,
444 int access_type
, int mmu_idx
)
446 #if defined(CONFIG_USER_ONLY)
449 CPUTLBEntry
*tlbentry
= tlb_entry(env
, mmu_idx
, addr
);
453 switch (access_type
) {
455 tlb_addr
= tlbentry
->addr_read
;
458 tlb_addr
= tlb_addr_write(tlbentry
);
461 tlb_addr
= tlbentry
->addr_code
;
464 g_assert_not_reached();
467 if (!tlb_hit(tlb_addr
, addr
)) {
468 /* TLB entry is for a different page */
472 if (tlb_addr
& ~TARGET_PAGE_MASK
) {
477 haddr
= addr
+ tlbentry
->addend
;
478 return (void *)haddr
;
479 #endif /* defined(CONFIG_USER_ONLY) */
482 #endif /* CPU_LDST_H */