2 * QEMU PowerPC 4xx embedded processors shared devices emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "sysemu/reset.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/ppc4xx.h"
32 #include "hw/intc/ppc-uic.h"
33 #include "hw/qdev-properties.h"
35 #include "exec/address-spaces.h"
36 #include "qemu/error-report.h"
37 #include "qapi/error.h"
40 static void ppc4xx_reset(void *opaque
)
42 PowerPCCPU
*cpu
= opaque
;
47 /*****************************************************************************/
48 /* Generic PowerPC 4xx processor instantiation */
49 PowerPCCPU
*ppc4xx_init(const char *cpu_type
,
50 clk_setup_t
*cpu_clk
, clk_setup_t
*tb_clk
,
57 cpu
= POWERPC_CPU(cpu_create(cpu_type
));
60 cpu_clk
->cb
= NULL
; /* We don't care about CPU clock frequency changes */
61 cpu_clk
->opaque
= env
;
62 /* Set time-base frequency to sysclk */
63 tb_clk
->cb
= ppc_40x_timers_init(env
, sysclk
, PPC_INTERRUPT_PIT
);
65 ppc_dcr_init(env
, NULL
, NULL
);
66 /* Register qemu callbacks */
67 qemu_register_reset(ppc4xx_reset
, cpu
);
72 /*****************************************************************************/
73 /* SDRAM controller */
74 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t
;
75 struct ppc4xx_sdram_t
{
78 MemoryRegion containers
[4]; /* used for clipping */
79 MemoryRegion
*ram_memories
;
97 SDRAM0_CFGADDR
= 0x010,
98 SDRAM0_CFGDATA
= 0x011,
101 /* XXX: TOFIX: some patches have made this code become inconsistent:
102 * there are type inconsistencies, mixing hwaddr, target_ulong
105 static uint32_t sdram_bcr (hwaddr ram_base
,
133 qemu_log_mask(LOG_GUEST_ERROR
,
134 "%s: invalid RAM size 0x%" HWADDR_PRIx
"\n", __func__
,
138 bcr
|= ram_base
& 0xFF800000;
144 static inline hwaddr
sdram_base(uint32_t bcr
)
146 return bcr
& 0xFF800000;
149 static target_ulong
sdram_size (uint32_t bcr
)
154 sh
= (bcr
>> 17) & 0x7;
158 size
= (4 * MiB
) << sh
;
163 static void sdram_set_bcr(ppc4xx_sdram_t
*sdram
, int i
,
164 uint32_t bcr
, int enabled
)
166 if (sdram
->bcr
[i
] & 0x00000001) {
168 trace_ppc4xx_sdram_unmap(sdram_base(sdram
->bcr
[i
]),
169 sdram_size(sdram
->bcr
[i
]));
170 memory_region_del_subregion(get_system_memory(),
171 &sdram
->containers
[i
]);
172 memory_region_del_subregion(&sdram
->containers
[i
],
173 &sdram
->ram_memories
[i
]);
174 object_unparent(OBJECT(&sdram
->containers
[i
]));
176 sdram
->bcr
[i
] = bcr
& 0xFFDEE001;
177 if (enabled
&& (bcr
& 0x00000001)) {
178 trace_ppc4xx_sdram_unmap(sdram_base(bcr
), sdram_size(bcr
));
179 memory_region_init(&sdram
->containers
[i
], NULL
, "sdram-containers",
181 memory_region_add_subregion(&sdram
->containers
[i
], 0,
182 &sdram
->ram_memories
[i
]);
183 memory_region_add_subregion(get_system_memory(),
185 &sdram
->containers
[i
]);
189 static void sdram_map_bcr (ppc4xx_sdram_t
*sdram
)
193 for (i
= 0; i
< sdram
->nbanks
; i
++) {
194 if (sdram
->ram_sizes
[i
] != 0) {
195 sdram_set_bcr(sdram
, i
, sdram_bcr(sdram
->ram_bases
[i
],
196 sdram
->ram_sizes
[i
]), 1);
198 sdram_set_bcr(sdram
, i
, 0x00000000, 0);
203 static void sdram_unmap_bcr (ppc4xx_sdram_t
*sdram
)
207 for (i
= 0; i
< sdram
->nbanks
; i
++) {
208 trace_ppc4xx_sdram_unmap(sdram_base(sdram
->bcr
[i
]),
209 sdram_size(sdram
->bcr
[i
]));
210 memory_region_del_subregion(get_system_memory(),
211 &sdram
->ram_memories
[i
]);
215 static uint32_t dcr_read_sdram (void *opaque
, int dcrn
)
217 ppc4xx_sdram_t
*sdram
;
226 switch (sdram
->addr
) {
227 case 0x00: /* SDRAM_BESR0 */
230 case 0x08: /* SDRAM_BESR1 */
233 case 0x10: /* SDRAM_BEAR */
236 case 0x20: /* SDRAM_CFG */
239 case 0x24: /* SDRAM_STATUS */
242 case 0x30: /* SDRAM_RTR */
245 case 0x34: /* SDRAM_PMIT */
248 case 0x40: /* SDRAM_B0CR */
251 case 0x44: /* SDRAM_B1CR */
254 case 0x48: /* SDRAM_B2CR */
257 case 0x4C: /* SDRAM_B3CR */
260 case 0x80: /* SDRAM_TR */
263 case 0x94: /* SDRAM_ECCCFG */
266 case 0x98: /* SDRAM_ECCESR */
275 /* Avoid gcc warning */
283 static void dcr_write_sdram (void *opaque
, int dcrn
, uint32_t val
)
285 ppc4xx_sdram_t
*sdram
;
293 switch (sdram
->addr
) {
294 case 0x00: /* SDRAM_BESR0 */
295 sdram
->besr0
&= ~val
;
297 case 0x08: /* SDRAM_BESR1 */
298 sdram
->besr1
&= ~val
;
300 case 0x10: /* SDRAM_BEAR */
303 case 0x20: /* SDRAM_CFG */
305 if (!(sdram
->cfg
& 0x80000000) && (val
& 0x80000000)) {
306 trace_ppc4xx_sdram_enable("enable");
307 /* validate all RAM mappings */
308 sdram_map_bcr(sdram
);
309 sdram
->status
&= ~0x80000000;
310 } else if ((sdram
->cfg
& 0x80000000) && !(val
& 0x80000000)) {
311 trace_ppc4xx_sdram_enable("disable");
312 /* invalidate all RAM mappings */
313 sdram_unmap_bcr(sdram
);
314 sdram
->status
|= 0x80000000;
316 if (!(sdram
->cfg
& 0x40000000) && (val
& 0x40000000))
317 sdram
->status
|= 0x40000000;
318 else if ((sdram
->cfg
& 0x40000000) && !(val
& 0x40000000))
319 sdram
->status
&= ~0x40000000;
322 case 0x24: /* SDRAM_STATUS */
323 /* Read-only register */
325 case 0x30: /* SDRAM_RTR */
326 sdram
->rtr
= val
& 0x3FF80000;
328 case 0x34: /* SDRAM_PMIT */
329 sdram
->pmit
= (val
& 0xF8000000) | 0x07C00000;
331 case 0x40: /* SDRAM_B0CR */
332 sdram_set_bcr(sdram
, 0, val
, sdram
->cfg
& 0x80000000);
334 case 0x44: /* SDRAM_B1CR */
335 sdram_set_bcr(sdram
, 1, val
, sdram
->cfg
& 0x80000000);
337 case 0x48: /* SDRAM_B2CR */
338 sdram_set_bcr(sdram
, 2, val
, sdram
->cfg
& 0x80000000);
340 case 0x4C: /* SDRAM_B3CR */
341 sdram_set_bcr(sdram
, 3, val
, sdram
->cfg
& 0x80000000);
343 case 0x80: /* SDRAM_TR */
344 sdram
->tr
= val
& 0x018FC01F;
346 case 0x94: /* SDRAM_ECCCFG */
347 sdram
->ecccfg
= val
& 0x00F00000;
349 case 0x98: /* SDRAM_ECCESR */
351 if (sdram
->eccesr
== 0 && val
!= 0)
352 qemu_irq_raise(sdram
->irq
);
353 else if (sdram
->eccesr
!= 0 && val
== 0)
354 qemu_irq_lower(sdram
->irq
);
364 static void sdram_reset (void *opaque
)
366 ppc4xx_sdram_t
*sdram
;
369 sdram
->addr
= 0x00000000;
370 sdram
->bear
= 0x00000000;
371 sdram
->besr0
= 0x00000000; /* No error */
372 sdram
->besr1
= 0x00000000; /* No error */
373 sdram
->cfg
= 0x00000000;
374 sdram
->ecccfg
= 0x00000000; /* No ECC */
375 sdram
->eccesr
= 0x00000000; /* No error */
376 sdram
->pmit
= 0x07C00000;
377 sdram
->rtr
= 0x05F00000;
378 sdram
->tr
= 0x00854009;
379 /* We pre-initialize RAM banks */
380 sdram
->status
= 0x00000000;
381 sdram
->cfg
= 0x00800000;
384 void ppc4xx_sdram_init (CPUPPCState
*env
, qemu_irq irq
, int nbanks
,
385 MemoryRegion
*ram_memories
,
390 ppc4xx_sdram_t
*sdram
;
392 sdram
= g_malloc0(sizeof(ppc4xx_sdram_t
));
394 sdram
->nbanks
= nbanks
;
395 sdram
->ram_memories
= ram_memories
;
396 memset(sdram
->ram_bases
, 0, 4 * sizeof(hwaddr
));
397 memcpy(sdram
->ram_bases
, ram_bases
,
398 nbanks
* sizeof(hwaddr
));
399 memset(sdram
->ram_sizes
, 0, 4 * sizeof(hwaddr
));
400 memcpy(sdram
->ram_sizes
, ram_sizes
,
401 nbanks
* sizeof(hwaddr
));
402 qemu_register_reset(&sdram_reset
, sdram
);
403 ppc_dcr_register(env
, SDRAM0_CFGADDR
,
404 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
405 ppc_dcr_register(env
, SDRAM0_CFGDATA
,
406 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
408 sdram_map_bcr(sdram
);
412 * Split RAM between SDRAM banks.
414 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
415 * and must be 0-terminated.
417 * The 4xx SDRAM controller supports a small number of banks, and each bank
418 * must be one of a small set of sizes. The number of banks and the supported
419 * sizes varies by SoC.
421 void ppc4xx_sdram_banks(MemoryRegion
*ram
, int nr_banks
,
422 MemoryRegion ram_memories
[],
423 hwaddr ram_bases
[], hwaddr ram_sizes
[],
424 const ram_addr_t sdram_bank_sizes
[])
426 ram_addr_t size_left
= memory_region_size(ram
);
428 ram_addr_t bank_size
;
432 for (i
= 0; i
< nr_banks
; i
++) {
433 for (j
= 0; sdram_bank_sizes
[j
] != 0; j
++) {
434 bank_size
= sdram_bank_sizes
[j
];
435 if (bank_size
<= size_left
) {
439 ram_sizes
[i
] = bank_size
;
441 size_left
-= bank_size
;
442 snprintf(name
, sizeof(name
), "ppc4xx.sdram%d", i
);
443 memory_region_init_alias(&ram_memories
[i
], NULL
, name
, ram
,
444 ram_bases
[i
], ram_sizes
[i
]);
449 /* No need to use the remaining banks. */
455 ram_addr_t used_size
= memory_region_size(ram
) - size_left
;
456 GString
*s
= g_string_new(NULL
);
458 for (i
= 0; sdram_bank_sizes
[i
]; i
++) {
459 g_string_append_printf(s
, "%" PRIi64
"%s",
460 sdram_bank_sizes
[i
] / MiB
,
461 sdram_bank_sizes
[i
+ 1] ? ", " : "");
463 error_report("at most %d bank%s of %s MiB each supported",
464 nr_banks
, nr_banks
== 1 ? "" : "s", s
->str
);
465 error_printf("Possible valid RAM size: %" PRIi64
" MiB \n",
466 used_size
? used_size
/ MiB
: sdram_bank_sizes
[i
- 1] / MiB
);
468 g_string_free(s
, true);
473 /*****************************************************************************/
482 MAL0_TXEOBISR
= 0x186,
486 MAL0_RXEOBISR
= 0x192,
488 MAL0_TXCTP0R
= 0x1A0,
489 MAL0_RXCTP0R
= 0x1C0,
494 typedef struct ppc4xx_mal_t ppc4xx_mal_t
;
495 struct ppc4xx_mal_t
{
515 static void ppc4xx_mal_reset(void *opaque
)
520 mal
->cfg
= 0x0007C000;
521 mal
->esr
= 0x00000000;
522 mal
->ier
= 0x00000000;
523 mal
->rxcasr
= 0x00000000;
524 mal
->rxdeir
= 0x00000000;
525 mal
->rxeobisr
= 0x00000000;
526 mal
->txcasr
= 0x00000000;
527 mal
->txdeir
= 0x00000000;
528 mal
->txeobisr
= 0x00000000;
531 static uint32_t dcr_read_mal(void *opaque
, int dcrn
)
575 if (dcrn
>= MAL0_TXCTP0R
&& dcrn
< MAL0_TXCTP0R
+ mal
->txcnum
) {
576 ret
= mal
->txctpr
[dcrn
- MAL0_TXCTP0R
];
578 if (dcrn
>= MAL0_RXCTP0R
&& dcrn
< MAL0_RXCTP0R
+ mal
->rxcnum
) {
579 ret
= mal
->rxctpr
[dcrn
- MAL0_RXCTP0R
];
581 if (dcrn
>= MAL0_RCBS0
&& dcrn
< MAL0_RCBS0
+ mal
->rxcnum
) {
582 ret
= mal
->rcbs
[dcrn
- MAL0_RCBS0
];
588 static void dcr_write_mal(void *opaque
, int dcrn
, uint32_t val
)
595 if (val
& 0x80000000) {
596 ppc4xx_mal_reset(mal
);
598 mal
->cfg
= val
& 0x00FFC087;
605 mal
->ier
= val
& 0x0000001F;
608 mal
->txcasr
= val
& 0xF0000000;
611 mal
->txcarr
= val
& 0xF0000000;
615 mal
->txeobisr
&= ~val
;
622 mal
->rxcasr
= val
& 0xC0000000;
625 mal
->rxcarr
= val
& 0xC0000000;
629 mal
->rxeobisr
&= ~val
;
636 if (dcrn
>= MAL0_TXCTP0R
&& dcrn
< MAL0_TXCTP0R
+ mal
->txcnum
) {
637 mal
->txctpr
[dcrn
- MAL0_TXCTP0R
] = val
;
639 if (dcrn
>= MAL0_RXCTP0R
&& dcrn
< MAL0_RXCTP0R
+ mal
->rxcnum
) {
640 mal
->rxctpr
[dcrn
- MAL0_RXCTP0R
] = val
;
642 if (dcrn
>= MAL0_RCBS0
&& dcrn
< MAL0_RCBS0
+ mal
->rxcnum
) {
643 mal
->rcbs
[dcrn
- MAL0_RCBS0
] = val
& 0x000000FF;
647 void ppc4xx_mal_init(CPUPPCState
*env
, uint8_t txcnum
, uint8_t rxcnum
,
653 assert(txcnum
<= 32 && rxcnum
<= 32);
654 mal
= g_malloc0(sizeof(*mal
));
655 mal
->txcnum
= txcnum
;
656 mal
->rxcnum
= rxcnum
;
657 mal
->txctpr
= g_new0(uint32_t, txcnum
);
658 mal
->rxctpr
= g_new0(uint32_t, rxcnum
);
659 mal
->rcbs
= g_new0(uint32_t, rxcnum
);
660 for (i
= 0; i
< 4; i
++) {
661 mal
->irqs
[i
] = irqs
[i
];
663 qemu_register_reset(&ppc4xx_mal_reset
, mal
);
664 ppc_dcr_register(env
, MAL0_CFG
,
665 mal
, &dcr_read_mal
, &dcr_write_mal
);
666 ppc_dcr_register(env
, MAL0_ESR
,
667 mal
, &dcr_read_mal
, &dcr_write_mal
);
668 ppc_dcr_register(env
, MAL0_IER
,
669 mal
, &dcr_read_mal
, &dcr_write_mal
);
670 ppc_dcr_register(env
, MAL0_TXCASR
,
671 mal
, &dcr_read_mal
, &dcr_write_mal
);
672 ppc_dcr_register(env
, MAL0_TXCARR
,
673 mal
, &dcr_read_mal
, &dcr_write_mal
);
674 ppc_dcr_register(env
, MAL0_TXEOBISR
,
675 mal
, &dcr_read_mal
, &dcr_write_mal
);
676 ppc_dcr_register(env
, MAL0_TXDEIR
,
677 mal
, &dcr_read_mal
, &dcr_write_mal
);
678 ppc_dcr_register(env
, MAL0_RXCASR
,
679 mal
, &dcr_read_mal
, &dcr_write_mal
);
680 ppc_dcr_register(env
, MAL0_RXCARR
,
681 mal
, &dcr_read_mal
, &dcr_write_mal
);
682 ppc_dcr_register(env
, MAL0_RXEOBISR
,
683 mal
, &dcr_read_mal
, &dcr_write_mal
);
684 ppc_dcr_register(env
, MAL0_RXDEIR
,
685 mal
, &dcr_read_mal
, &dcr_write_mal
);
686 for (i
= 0; i
< txcnum
; i
++) {
687 ppc_dcr_register(env
, MAL0_TXCTP0R
+ i
,
688 mal
, &dcr_read_mal
, &dcr_write_mal
);
690 for (i
= 0; i
< rxcnum
; i
++) {
691 ppc_dcr_register(env
, MAL0_RXCTP0R
+ i
,
692 mal
, &dcr_read_mal
, &dcr_write_mal
);
694 for (i
= 0; i
< rxcnum
; i
++) {
695 ppc_dcr_register(env
, MAL0_RCBS0
+ i
,
696 mal
, &dcr_read_mal
, &dcr_write_mal
);