hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/arm/arm.h"
  30 #include "hw/arm/primecell.h"
  31 #include "hw/devices.h"
  32 #include "net/net.h"
  33 #include "sysemu/sysemu.h"
  34 #include "hw/boards.h"
  35 #include "hw/loader.h"
  36 #include "exec/address-spaces.h"
  37 #include "sysemu/block-backend.h"
  38 #include "hw/block/flash.h"
  39 #include "sysemu/device_tree.h"
  40 #include "qemu/error-report.h"
  41 #include <libfdt.h>
  42 #include "hw/char/pl011.h"
  43 #include "hw/cpu/a9mpcore.h"
  44 #include "hw/cpu/a15mpcore.h"
  45
  46 #define VEXPRESS_BOARD_ID 0x8e0
  47 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  48 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  49
  50 /* Number of virtio transports to create (0..8; limited by
  51  * number of available IRQ lines).
  52  */
  53 #define NUM_VIRTIO_TRANSPORTS 4
  54
  55 /* Address maps for peripherals:
  56  * the Versatile Express motherboard has two possible maps,
  57  * the "legacy" one (used for A9) and the "Cortex-A Series"
  58  * map (used for newer cores).
  59  * Individual daughterboards can also have different maps for
  60  * their peripherals.
  61  */
  62
  63 enum {
  64     VE_SYSREGS,
  65     VE_SP810,
  66     VE_SERIALPCI,
  67     VE_PL041,
  68     VE_MMCI,
  69     VE_KMI0,
  70     VE_KMI1,
  71     VE_UART0,
  72     VE_UART1,
  73     VE_UART2,
  74     VE_UART3,
  75     VE_WDT,
  76     VE_TIMER01,
  77     VE_TIMER23,
  78     VE_SERIALDVI,
  79     VE_RTC,
  80     VE_COMPACTFLASH,
  81     VE_CLCD,
  82     VE_NORFLASH0,
  83     VE_NORFLASH1,
  84     VE_NORFLASHALIAS,
  85     VE_SRAM,
  86     VE_VIDEORAM,
  87     VE_ETHERNET,
  88     VE_USB,
  89     VE_DAPROM,
  90     VE_VIRTIO,
  91 };
  92
  93 static hwaddr motherboard_legacy_map[] = {
  94     [VE_NORFLASHALIAS] = 0,
  95     /* CS7: 0x10000000 .. 0x10020000 */
  96     [VE_SYSREGS] = 0x10000000,
  97     [VE_SP810] = 0x10001000,
  98     [VE_SERIALPCI] = 0x10002000,
  99     [VE_PL041] = 0x10004000,
 100     [VE_MMCI] = 0x10005000,
 101     [VE_KMI0] = 0x10006000,
 102     [VE_KMI1] = 0x10007000,
 103     [VE_UART0] = 0x10009000,
 104     [VE_UART1] = 0x1000a000,
 105     [VE_UART2] = 0x1000b000,
 106     [VE_UART3] = 0x1000c000,
 107     [VE_WDT] = 0x1000f000,
 108     [VE_TIMER01] = 0x10011000,
 109     [VE_TIMER23] = 0x10012000,
 110     [VE_VIRTIO] = 0x10013000,
 111     [VE_SERIALDVI] = 0x10016000,
 112     [VE_RTC] = 0x10017000,
 113     [VE_COMPACTFLASH] = 0x1001a000,
 114     [VE_CLCD] = 0x1001f000,
 115     /* CS0: 0x40000000 .. 0x44000000 */
 116     [VE_NORFLASH0] = 0x40000000,
 117     /* CS1: 0x44000000 .. 0x48000000 */
 118     [VE_NORFLASH1] = 0x44000000,
 119     /* CS2: 0x48000000 .. 0x4a000000 */
 120     [VE_SRAM] = 0x48000000,
 121     /* CS3: 0x4c000000 .. 0x50000000 */
 122     [VE_VIDEORAM] = 0x4c000000,
 123     [VE_ETHERNET] = 0x4e000000,
 124     [VE_USB] = 0x4f000000,
 125 };
 126
 127 static hwaddr motherboard_aseries_map[] = {
 128     [VE_NORFLASHALIAS] = 0,
 129     /* CS0: 0x08000000 .. 0x0c000000 */
 130     [VE_NORFLASH0] = 0x08000000,
 131     /* CS4: 0x0c000000 .. 0x10000000 */
 132     [VE_NORFLASH1] = 0x0c000000,
 133     /* CS5: 0x10000000 .. 0x14000000 */
 134     /* CS1: 0x14000000 .. 0x18000000 */
 135     [VE_SRAM] = 0x14000000,
 136     /* CS2: 0x18000000 .. 0x1c000000 */
 137     [VE_VIDEORAM] = 0x18000000,
 138     [VE_ETHERNET] = 0x1a000000,
 139     [VE_USB] = 0x1b000000,
 140     /* CS3: 0x1c000000 .. 0x20000000 */
 141     [VE_DAPROM] = 0x1c000000,
 142     [VE_SYSREGS] = 0x1c010000,
 143     [VE_SP810] = 0x1c020000,
 144     [VE_SERIALPCI] = 0x1c030000,
 145     [VE_PL041] = 0x1c040000,
 146     [VE_MMCI] = 0x1c050000,
 147     [VE_KMI0] = 0x1c060000,
 148     [VE_KMI1] = 0x1c070000,
 149     [VE_UART0] = 0x1c090000,
 150     [VE_UART1] = 0x1c0a0000,
 151     [VE_UART2] = 0x1c0b0000,
 152     [VE_UART3] = 0x1c0c0000,
 153     [VE_WDT] = 0x1c0f0000,
 154     [VE_TIMER01] = 0x1c110000,
 155     [VE_TIMER23] = 0x1c120000,
 156     [VE_VIRTIO] = 0x1c130000,
 157     [VE_SERIALDVI] = 0x1c160000,
 158     [VE_RTC] = 0x1c170000,
 159     [VE_COMPACTFLASH] = 0x1c1a0000,
 160     [VE_CLCD] = 0x1c1f0000,
 161 };
 162
 163 /* Structure defining the peculiarities of a specific daughterboard */
 164
 165 typedef struct VEDBoardInfo VEDBoardInfo;
 166
 167 typedef struct {
 168     MachineClass parent;
 169     VEDBoardInfo *daughterboard;
 170 } VexpressMachineClass;
 171
 172 typedef struct {
 173     MachineState parent;
 174     bool secure;
 175 } VexpressMachineState;
 176
 177 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 178 #define TYPE_VEXPRESS_A9_MACHINE   MACHINE_TYPE_NAME("vexpress-a9")
 179 #define TYPE_VEXPRESS_A15_MACHINE   MACHINE_TYPE_NAME("vexpress-a15")
 180 #define VEXPRESS_MACHINE(obj) \
 181     OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
 182 #define VEXPRESS_MACHINE_GET_CLASS(obj) \
 183     OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
 184 #define VEXPRESS_MACHINE_CLASS(klass) \
 185     OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
 186
 187 typedef void DBoardInitFn(const VexpressMachineState *machine,
 188                           ram_addr_t ram_size,
 189                           const char *cpu_type,
 190                           qemu_irq *pic);
 191
 192 struct VEDBoardInfo {
 193     struct arm_boot_info bootinfo;
 194     const hwaddr *motherboard_map;
 195     hwaddr loader_start;
 196     const hwaddr gic_cpu_if_addr;
 197     uint32_t proc_id;
 198     uint32_t num_voltage_sensors;
 199     const uint32_t *voltages;
 200     uint32_t num_clocks;
 201     const uint32_t *clocks;
 202     DBoardInitFn *init;
 203 };
 204
 205 static void init_cpus(const char *cpu_type, const char *privdev,
 206                       hwaddr periphbase, qemu_irq *pic, bool secure)
 207 {
 208     DeviceState *dev;
 209     SysBusDevice *busdev;
 210     int n;
 211
 212     /* Create the actual CPUs */
 213     for (n = 0; n < smp_cpus; n++) {
 214         Object *cpuobj = object_new(cpu_type);
 215
 216         if (!secure) {
 217             object_property_set_bool(cpuobj, false, "has_el3", NULL);
 218         }
 219
 220         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 221             object_property_set_int(cpuobj, periphbase,
 222                                     "reset-cbar", &error_abort);
 223         }
 224         object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 225     }
 226
 227     /* Create the private peripheral devices (including the GIC);
 228      * this must happen after the CPUs are created because a15mpcore_priv
 229      * wires itself up to the CPU's generic_timer gpio out lines.
 230      */
 231     dev = qdev_create(NULL, privdev);
 232     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 233     qdev_init_nofail(dev);
 234     busdev = SYS_BUS_DEVICE(dev);
 235     sysbus_mmio_map(busdev, 0, periphbase);
 236
 237     /* Interrupts [42:0] are from the motherboard;
 238      * [47:43] are reserved; [63:48] are daughterboard
 239      * peripherals. Note that some documentation numbers
 240      * external interrupts starting from 32 (because there
 241      * are internal interrupts 0..31).
 242      */
 243     for (n = 0; n < 64; n++) {
 244         pic[n] = qdev_get_gpio_in(dev, n);
 245     }
 246
 247     /* Connect the CPUs to the GIC */
 248     for (n = 0; n < smp_cpus; n++) {
 249         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 250
 251         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 252         sysbus_connect_irq(busdev, n + smp_cpus,
 253                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 254     }
 255 }
 256
 257 static void a9_daughterboard_init(const VexpressMachineState *vms,
 258                                   ram_addr_t ram_size,
 259                                   const char *cpu_type,
 260                                   qemu_irq *pic)
 261 {
 262     MemoryRegion *sysmem = get_system_memory();
 263     MemoryRegion *ram = g_new(MemoryRegion, 1);
 264     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 265     ram_addr_t low_ram_size;
 266
 267     if (ram_size > 0x40000000) {
 268         /* 1GB is the maximum the address space permits */
 269         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 270         exit(1);
 271     }
 272
 273     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 274                                          ram_size);
 275     low_ram_size = ram_size;
 276     if (low_ram_size > 0x4000000) {
 277         low_ram_size = 0x4000000;
 278     }
 279     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 280      * address space should in theory be remappable to various
 281      * things including ROM or RAM; we always map the RAM there.
 282      */
 283     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 284     memory_region_add_subregion(sysmem, 0x0, lowram);
 285     memory_region_add_subregion(sysmem, 0x60000000, ram);
 286
 287     /* 0x1e000000 A9MPCore (SCU) private memory region */
 288     init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
 289
 290     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 291
 292     /* 0x10020000 PL111 CLCD (daughterboard) */
 293     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 294
 295     /* 0x10060000 AXI RAM */
 296     /* 0x100e0000 PL341 Dynamic Memory Controller */
 297     /* 0x100e1000 PL354 Static Memory Controller */
 298     /* 0x100e2000 System Configuration Controller */
 299
 300     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 301     /* 0x100e5000 SP805 Watchdog module */
 302     /* 0x100e6000 BP147 TrustZone Protection Controller */
 303     /* 0x100e9000 PL301 'Fast' AXI matrix */
 304     /* 0x100ea000 PL301 'Slow' AXI matrix */
 305     /* 0x100ec000 TrustZone Address Space Controller */
 306     /* 0x10200000 CoreSight debug APB */
 307     /* 0x1e00a000 PL310 L2 Cache Controller */
 308     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 309 }
 310
 311 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 312  * values are in microvolts.
 313  */
 314 static const uint32_t a9_voltages[] = {
 315     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 316     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 317     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 318     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 319     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 320     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 321 };
 322
 323 /* Reset values for daughterboard oscillators (in Hz) */
 324 static const uint32_t a9_clocks[] = {
 325     45000000, /* AMBA AXI ACLK: 45MHz */
 326     23750000, /* daughterboard CLCD clock: 23.75MHz */
 327     66670000, /* Test chip reference clock: 66.67MHz */
 328 };
 329
 330 static VEDBoardInfo a9_daughterboard = {
 331     .motherboard_map = motherboard_legacy_map,
 332     .loader_start = 0x60000000,
 333     .gic_cpu_if_addr = 0x1e000100,
 334     .proc_id = 0x0c000191,
 335     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 336     .voltages = a9_voltages,
 337     .num_clocks = ARRAY_SIZE(a9_clocks),
 338     .clocks = a9_clocks,
 339     .init = a9_daughterboard_init,
 340 };
 341
 342 static void a15_daughterboard_init(const VexpressMachineState *vms,
 343                                    ram_addr_t ram_size,
 344                                    const char *cpu_type,
 345                                    qemu_irq *pic)
 346 {
 347     MemoryRegion *sysmem = get_system_memory();
 348     MemoryRegion *ram = g_new(MemoryRegion, 1);
 349     MemoryRegion *sram = g_new(MemoryRegion, 1);
 350
 351     {
 352         /* We have to use a separate 64 bit variable here to avoid the gcc
 353          * "comparison is always false due to limited range of data type"
 354          * warning if we are on a host where ram_addr_t is 32 bits.
 355          */
 356         uint64_t rsz = ram_size;
 357         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 358             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 359             exit(1);
 360         }
 361     }
 362
 363     memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
 364                                          ram_size);
 365     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 366     memory_region_add_subregion(sysmem, 0x80000000, ram);
 367
 368     /* 0x2c000000 A15MPCore private memory region (GIC) */
 369     init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
 370
 371     /* A15 daughterboard peripherals: */
 372
 373     /* 0x20000000: CoreSight interfaces: not modelled */
 374     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 375     /* 0x2a420000: SCC: not modelled */
 376     /* 0x2a430000: system counter: not modelled */
 377     /* 0x2b000000: HDLCD controller: not modelled */
 378     /* 0x2b060000: SP805 watchdog: not modelled */
 379     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 380     /* 0x2e000000: system SRAM */
 381     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 382                            &error_fatal);
 383     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 384
 385     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 386     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 387 }
 388
 389 static const uint32_t a15_voltages[] = {
 390     900000, /* Vcore: 0.9V : CPU core voltage */
 391 };
 392
 393 static const uint32_t a15_clocks[] = {
 394     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 395     0, /* OSCCLK1: reserved */
 396     0, /* OSCCLK2: reserved */
 397     0, /* OSCCLK3: reserved */
 398     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 399     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 400     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 401     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 402     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 403 };
 404
 405 static VEDBoardInfo a15_daughterboard = {
 406     .motherboard_map = motherboard_aseries_map,
 407     .loader_start = 0x80000000,
 408     .gic_cpu_if_addr = 0x2c002000,
 409     .proc_id = 0x14000237,
 410     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 411     .voltages = a15_voltages,
 412     .num_clocks = ARRAY_SIZE(a15_clocks),
 413     .clocks = a15_clocks,
 414     .init = a15_daughterboard_init,
 415 };
 416
 417 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 418                                 hwaddr addr, hwaddr size, uint32_t intc,
 419                                 int irq)
 420 {
 421     /* Add a virtio_mmio node to the device tree blob:
 422      *   virtio_mmio@ADDRESS {
 423      *       compatible = "virtio,mmio";
 424      *       reg = <ADDRESS, SIZE>;
 425      *       interrupt-parent = <&intc>;
 426      *       interrupts = <0, irq, 1>;
 427      *   }
 428      * (Note that the format of the interrupts property is dependent on the
 429      * interrupt controller that interrupt-parent points to; these are for
 430      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 431      */
 432     int rc;
 433     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 434
 435     rc = qemu_fdt_add_subnode(fdt, nodename);
 436     rc |= qemu_fdt_setprop_string(fdt, nodename,
 437                                   "compatible", "virtio,mmio");
 438     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 439                                        acells, addr, scells, size);
 440     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 441     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 442     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 443     g_free(nodename);
 444     if (rc) {
 445         return -1;
 446     }
 447     return 0;
 448 }
 449
 450 static uint32_t find_int_controller(void *fdt)
 451 {
 452     /* Find the FDT node corresponding to the interrupt controller
 453      * for virtio-mmio devices. We do this by scanning the fdt for
 454      * a node with the right compatibility, since we know there is
 455      * only one GIC on a vexpress board.
 456      * We return the phandle of the node, or 0 if none was found.
 457      */
 458     const char *compat = "arm,cortex-a9-gic";
 459     int offset;
 460
 461     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 462     if (offset >= 0) {
 463         return fdt_get_phandle(fdt, offset);
 464     }
 465     return 0;
 466 }
 467
 468 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 469 {
 470     uint32_t acells, scells, intc;
 471     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 472
 473     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
 474                                    NULL, &error_fatal);
 475     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
 476                                    NULL, &error_fatal);
 477     intc = find_int_controller(fdt);
 478     if (!intc) {
 479         /* Not fatal, we just won't provide virtio. This will
 480          * happen with older device tree blobs.
 481          */
 482         warn_report("couldn't find interrupt controller in "
 483                     "dtb; will not include virtio-mmio devices in the dtb");
 484     } else {
 485         int i;
 486         const hwaddr *map = daughterboard->motherboard_map;
 487
 488         /* We iterate backwards here because adding nodes
 489          * to the dtb puts them in last-first.
 490          */
 491         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 492             add_virtio_mmio_node(fdt, acells, scells,
 493                                  map[VE_VIRTIO] + 0x200 * i,
 494                                  0x200, intc, 40 + i);
 495         }
 496     }
 497 }
 498
 499
 500 /* Open code a private version of pflash registration since we
 501  * need to set non-default device width for VExpress platform.
 502  */
 503 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 504                                           DriveInfo *di)
 505 {
 506     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 507
 508     if (di) {
 509         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
 510                             &error_abort);
 511     }
 512
 513     qdev_prop_set_uint32(dev, "num-blocks",
 514                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 515     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 516     qdev_prop_set_uint8(dev, "width", 4);
 517     qdev_prop_set_uint8(dev, "device-width", 2);
 518     qdev_prop_set_bit(dev, "big-endian", false);
 519     qdev_prop_set_uint16(dev, "id0", 0x89);
 520     qdev_prop_set_uint16(dev, "id1", 0x18);
 521     qdev_prop_set_uint16(dev, "id2", 0x00);
 522     qdev_prop_set_uint16(dev, "id3", 0x00);
 523     qdev_prop_set_string(dev, "name", name);
 524     qdev_init_nofail(dev);
 525
 526     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 527     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 528 }
 529
 530 static void vexpress_common_init(MachineState *machine)
 531 {
 532     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 533     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 534     VEDBoardInfo *daughterboard = vmc->daughterboard;
 535     DeviceState *dev, *sysctl, *pl041;
 536     qemu_irq pic[64];
 537     uint32_t sys_id;
 538     DriveInfo *dinfo;
 539     pflash_t *pflash0;
 540     ram_addr_t vram_size, sram_size;
 541     MemoryRegion *sysmem = get_system_memory();
 542     MemoryRegion *vram = g_new(MemoryRegion, 1);
 543     MemoryRegion *sram = g_new(MemoryRegion, 1);
 544     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 545     MemoryRegion *flash0mem;
 546     const hwaddr *map = daughterboard->motherboard_map;
 547     int i;
 548
 549     daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
 550
 551     /*
 552      * If a bios file was provided, attempt to map it into memory
 553      */
 554     if (bios_name) {
 555         char *fn;
 556         int image_size;
 557
 558         if (drive_get(IF_PFLASH, 0, 0)) {
 559             error_report("The contents of the first flash device may be "
 560                          "specified with -bios or with -drive if=pflash... "
 561                          "but you cannot use both options at once");
 562             exit(1);
 563         }
 564         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 565         if (!fn) {
 566             error_report("Could not find ROM image '%s'", bios_name);
 567             exit(1);
 568         }
 569         image_size = load_image_targphys(fn, map[VE_NORFLASH0],
 570                                          VEXPRESS_FLASH_SIZE);
 571         g_free(fn);
 572         if (image_size < 0) {
 573             error_report("Could not load ROM image '%s'", bios_name);
 574             exit(1);
 575         }
 576     }
 577
 578     /* Motherboard peripherals: the wiring is the same but the
 579      * addresses vary between the legacy and A-Series memory maps.
 580      */
 581
 582     sys_id = 0x1190f500;
 583
 584     sysctl = qdev_create(NULL, "realview_sysctl");
 585     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 586     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 587     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 588                          daughterboard->num_voltage_sensors);
 589     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 590         char *propname = g_strdup_printf("db-voltage[%d]", i);
 591         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 592         g_free(propname);
 593     }
 594     qdev_prop_set_uint32(sysctl, "len-db-clock",
 595                          daughterboard->num_clocks);
 596     for (i = 0; i < daughterboard->num_clocks; i++) {
 597         char *propname = g_strdup_printf("db-clock[%d]", i);
 598         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 599         g_free(propname);
 600     }
 601     qdev_init_nofail(sysctl);
 602     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 603
 604     /* VE_SP810: not modelled */
 605     /* VE_SERIALPCI: not modelled */
 606
 607     pl041 = qdev_create(NULL, "pl041");
 608     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 609     qdev_init_nofail(pl041);
 610     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 611     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 612
 613     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 614     /* Wire up MMC card detect and read-only signals */
 615     qdev_connect_gpio_out(dev, 0,
 616                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 617     qdev_connect_gpio_out(dev, 1,
 618                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 619
 620     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 621     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 622
 623     pl011_create(map[VE_UART0], pic[5], serial_hds[0]);
 624     pl011_create(map[VE_UART1], pic[6], serial_hds[1]);
 625     pl011_create(map[VE_UART2], pic[7], serial_hds[2]);
 626     pl011_create(map[VE_UART3], pic[8], serial_hds[3]);
 627
 628     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 629     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 630
 631     /* VE_SERIALDVI: not modelled */
 632
 633     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 634
 635     /* VE_COMPACTFLASH: not modelled */
 636
 637     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 638
 639     dinfo = drive_get_next(IF_PFLASH);
 640     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 641                                        dinfo);
 642     if (!pflash0) {
 643         fprintf(stderr, "vexpress: error registering flash 0.\n");
 644         exit(1);
 645     }
 646
 647     if (map[VE_NORFLASHALIAS] != -1) {
 648         /* Map flash 0 as an alias into low memory */
 649         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 650         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 651                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 652         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 653     }
 654
 655     dinfo = drive_get_next(IF_PFLASH);
 656     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 657                                   dinfo)) {
 658         fprintf(stderr, "vexpress: error registering flash 1.\n");
 659         exit(1);
 660     }
 661
 662     sram_size = 0x2000000;
 663     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 664                            &error_fatal);
 665     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 666
 667     vram_size = 0x800000;
 668     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 669                            &error_fatal);
 670     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 671
 672     /* 0x4e000000 LAN9118 Ethernet */
 673     if (nd_table[0].used) {
 674         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 675     }
 676
 677     /* VE_USB: not modelled */
 678
 679     /* VE_DAPROM: not modelled */
 680
 681     /* Create mmio transports, so the user can create virtio backends
 682      * (which will be automatically plugged in to the transports). If
 683      * no backend is created the transport will just sit harmlessly idle.
 684      */
 685     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 686         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 687                              pic[40 + i]);
 688     }
 689
 690     daughterboard->bootinfo.ram_size = machine->ram_size;
 691     daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
 692     daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
 693     daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
 694     daughterboard->bootinfo.nb_cpus = smp_cpus;
 695     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 696     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 697     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 698     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 699     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 700     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 701     /* Indicate that when booting Linux we should be in secure state */
 702     daughterboard->bootinfo.secure_boot = true;
 703     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 704 }
 705
 706 static bool vexpress_get_secure(Object *obj, Error **errp)
 707 {
 708     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 709
 710     return vms->secure;
 711 }
 712
 713 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 714 {
 715     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 716
 717     vms->secure = value;
 718 }
 719
 720 static void vexpress_instance_init(Object *obj)
 721 {
 722     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 723
 724     /* EL3 is enabled by default on vexpress */
 725     vms->secure = true;
 726     object_property_add_bool(obj, "secure", vexpress_get_secure,
 727                              vexpress_set_secure, NULL);
 728     object_property_set_description(obj, "secure",
 729                                     "Set on/off to enable/disable the ARM "
 730                                     "Security Extensions (TrustZone)",
 731                                     NULL);
 732 }
 733
 734 static void vexpress_class_init(ObjectClass *oc, void *data)
 735 {
 736     MachineClass *mc = MACHINE_CLASS(oc);
 737
 738     mc->desc = "ARM Versatile Express";
 739     mc->init = vexpress_common_init;
 740     mc->max_cpus = 4;
 741     mc->ignore_memory_transaction_failures = true;
 742 }
 743
 744 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 745 {
 746     MachineClass *mc = MACHINE_CLASS(oc);
 747     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 748
 749     mc->desc = "ARM Versatile Express for Cortex-A9";
 750     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 751
 752     vmc->daughterboard = &a9_daughterboard;
 753 }
 754
 755 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 756 {
 757     MachineClass *mc = MACHINE_CLASS(oc);
 758     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 759
 760     mc->desc = "ARM Versatile Express for Cortex-A15";
 761     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
 762
 763     vmc->daughterboard = &a15_daughterboard;
 764 }
 765
 766 static const TypeInfo vexpress_info = {
 767     .name = TYPE_VEXPRESS_MACHINE,
 768     .parent = TYPE_MACHINE,
 769     .abstract = true,
 770     .instance_size = sizeof(VexpressMachineState),
 771     .instance_init = vexpress_instance_init,
 772     .class_size = sizeof(VexpressMachineClass),
 773     .class_init = vexpress_class_init,
 774 };
 775
 776 static const TypeInfo vexpress_a9_info = {
 777     .name = TYPE_VEXPRESS_A9_MACHINE,
 778     .parent = TYPE_VEXPRESS_MACHINE,
 779     .class_init = vexpress_a9_class_init,
 780 };
 781
 782 static const TypeInfo vexpress_a15_info = {
 783     .name = TYPE_VEXPRESS_A15_MACHINE,
 784     .parent = TYPE_VEXPRESS_MACHINE,
 785     .class_init = vexpress_a15_class_init,
 786 };
 787
 788 static void vexpress_machine_init(void)
 789 {
 790     type_register_static(&vexpress_info);
 791     type_register_static(&vexpress_a9_info);
 792     type_register_static(&vexpress_a15_info);
 793 }
 794
 795 type_init(vexpress_machine_init);