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chardev: remove many local variables in qemu_chr_parse_socket
[qemu/ericb.git] / hw / net / eepro100.c
blobe761daf55181b39bb1a303270db5aa00ff14e808
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include "qemu/osdep.h"
44 #include "qemu/units.h"
45 #include "hw/hw.h"
46 #include "hw/pci/pci.h"
47 #include "net/net.h"
48 #include "net/eth.h"
49 #include "hw/nvram/eeprom93xx.h"
50 #include "sysemu/sysemu.h"
51 #include "sysemu/dma.h"
52 #include "qemu/bitops.h"
53 #include "qapi/error.h"
54
55 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
56 * Such frames are rejected by real nics and their emulations.
57 * To avoid this behaviour, other nic emulations pad received
58 * frames. The following definition enables this padding for
59 * eepro100, too. We keep the define around in case it might
60 * become useful the future if the core networking is ever
61 * changed to pad short packets itself. */
62 #define CONFIG_PAD_RECEIVED_FRAMES
63
64 /* Debug EEPRO100 card. */
65 #if 0
66 # define DEBUG_EEPRO100
67 #endif
68
69 #ifdef DEBUG_EEPRO100
70 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
71 #else
72 #define logout(fmt, ...) ((void)0)
73 #endif
74
75 /* Set flags to 0 to disable debug output. */
76 #define INT 1 /* interrupt related actions */
77 #define MDI 1 /* mdi related actions */
78 #define OTHER 1
79 #define RXTX 1
80 #define EEPROM 1 /* eeprom related actions */
81
82 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
83
84 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
85
86 #define MAX_ETH_FRAME_SIZE 1514
87
88 /* This driver supports several different devices which are declared here. */
89 #define i82550 0x82550
90 #define i82551 0x82551
91 #define i82557A 0x82557a
92 #define i82557B 0x82557b
93 #define i82557C 0x82557c
94 #define i82558A 0x82558a
95 #define i82558B 0x82558b
96 #define i82559A 0x82559a
97 #define i82559B 0x82559b
98 #define i82559C 0x82559c
99 #define i82559ER 0x82559e
100 #define i82562 0x82562
101 #define i82801 0x82801
102
103 /* Use 64 word EEPROM. TODO: could be a runtime option. */
104 #define EEPROM_SIZE 64
105
106 #define PCI_MEM_SIZE (4 * KiB)
107 #define PCI_IO_SIZE 64
108 #define PCI_FLASH_SIZE (128 * KiB)
109
110 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
111
112 /* The SCB accepts the following controls for the Tx and Rx units: */
113 #define CU_NOP 0x0000 /* No operation. */
114 #define CU_START 0x0010 /* CU start. */
115 #define CU_RESUME 0x0020 /* CU resume. */
116 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
117 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
118 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
119 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
120 #define CU_SRESUME 0x00a0 /* CU static resume. */
121
122 #define RU_NOP 0x0000
123 #define RX_START 0x0001
124 #define RX_RESUME 0x0002
125 #define RU_ABORT 0x0004
126 #define RX_ADDR_LOAD 0x0006
127 #define RX_RESUMENR 0x0007
128 #define INT_MASK 0x0100
129 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
130
131 typedef struct {
132 const char *name;
133 const char *desc;
134 uint16_t device_id;
135 uint8_t revision;
136 uint16_t subsystem_vendor_id;
137 uint16_t subsystem_id;
138
139 uint32_t device;
140 uint8_t stats_size;
141 bool has_extended_tcb_support;
142 bool power_management;
143 } E100PCIDeviceInfo;
144
145 /* Offsets to the various registers.
146 All accesses need not be longword aligned. */
147 typedef enum {
148 SCBStatus = 0, /* Status Word. */
149 SCBAck = 1,
150 SCBCmd = 2, /* Rx/Command Unit command and status. */
151 SCBIntmask = 3,
152 SCBPointer = 4, /* General purpose pointer. */
153 SCBPort = 8, /* Misc. commands and operands. */
154 SCBflash = 12, /* Flash memory control. */
155 SCBeeprom = 14, /* EEPROM control. */
156 SCBCtrlMDI = 16, /* MDI interface control. */
157 SCBEarlyRx = 20, /* Early receive byte count. */
158 SCBFlow = 24, /* Flow Control. */
159 SCBpmdr = 27, /* Power Management Driver. */
160 SCBgctrl = 28, /* General Control. */
161 SCBgstat = 29, /* General Status. */
162 } E100RegisterOffset;
163
164 /* A speedo3 transmit buffer descriptor with two buffers... */
165 typedef struct {
166 uint16_t status;
167 uint16_t command;
168 uint32_t link; /* void * */
169 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
170 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
171 uint8_t tx_threshold; /* transmit threshold */
172 uint8_t tbd_count; /* TBD number */
173 #if 0
174 /* This constitutes two "TBD" entries: hdr and data */
175 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
176 int32_t tx_buf_size0; /* Length of Tx hdr. */
177 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
178 int32_t tx_buf_size1; /* Length of Tx data. */
179 #endif
180 } eepro100_tx_t;
181
182 /* Receive frame descriptor. */
183 typedef struct {
184 int16_t status;
185 uint16_t command;
186 uint32_t link; /* struct RxFD * */
187 uint32_t rx_buf_addr; /* void * */
188 uint16_t count;
189 uint16_t size;
190 /* Ethernet frame data follows. */
191 } eepro100_rx_t;
192
193 typedef enum {
194 COMMAND_EL = BIT(15),
195 COMMAND_S = BIT(14),
196 COMMAND_I = BIT(13),
197 COMMAND_NC = BIT(4),
198 COMMAND_SF = BIT(3),
199 COMMAND_CMD = BITS(2, 0),
200 } scb_command_bit;
201
202 typedef enum {
203 STATUS_C = BIT(15),
204 STATUS_OK = BIT(13),
205 } scb_status_bit;
206
207 typedef struct {
208 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
209 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
210 tx_multiple_collisions, tx_total_collisions;
211 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
212 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
213 rx_short_frame_errors;
214 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
215 uint16_t xmt_tco_frames, rcv_tco_frames;
216 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
217 uint32_t reserved[4];
218 } eepro100_stats_t;
219
220 typedef enum {
221 cu_idle = 0,
222 cu_suspended = 1,
223 cu_active = 2,
224 cu_lpq_active = 2,
225 cu_hqp_active = 3
226 } cu_state_t;
227
228 typedef enum {
229 ru_idle = 0,
230 ru_suspended = 1,
231 ru_no_resources = 2,
232 ru_ready = 4
233 } ru_state_t;
234
235 typedef struct {
236 PCIDevice dev;
237 /* Hash register (multicast mask array, multiple individual addresses). */
238 uint8_t mult[8];
239 MemoryRegion mmio_bar;
240 MemoryRegion io_bar;
241 MemoryRegion flash_bar;
242 NICState *nic;
243 NICConf conf;
244 uint8_t scb_stat; /* SCB stat/ack byte */
245 uint8_t int_stat; /* PCI interrupt status */
246 /* region must not be saved by nic_save. */
247 uint16_t mdimem[32];
248 eeprom_t *eeprom;
249 uint32_t device; /* device variant */
250 /* (cu_base + cu_offset) address the next command block in the command block list. */
251 uint32_t cu_base; /* CU base address */
252 uint32_t cu_offset; /* CU address offset */
253 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
254 uint32_t ru_base; /* RU base address */
255 uint32_t ru_offset; /* RU address offset */
256 uint32_t statsaddr; /* pointer to eepro100_stats_t */
257
258 /* Temporary status information (no need to save these values),
259 * used while processing CU commands. */
260 eepro100_tx_t tx; /* transmit buffer descriptor */
261 uint32_t cb_address; /* = cu_base + cu_offset */
262
263 /* Statistical counters. Also used for wake-up packet (i82559). */
264 eepro100_stats_t statistics;
265
266 /* Data in mem is always in the byte order of the controller (le).
267 * It must be dword aligned to allow direct access to 32 bit values. */
268 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
269
270 /* Configuration bytes. */
271 uint8_t configuration[22];
272
273 /* vmstate for each particular nic */
274 VMStateDescription *vmstate;
275
276 /* Quasi static device properties (no need to save them). */
277 uint16_t stats_size;
278 bool has_extended_tcb_support;
279 } EEPRO100State;
280
281 /* Word indices in EEPROM. */
282 typedef enum {
283 EEPROM_CNFG_MDIX = 0x03,
284 EEPROM_ID = 0x05,
285 EEPROM_PHY_ID = 0x06,
286 EEPROM_VENDOR_ID = 0x0c,
287 EEPROM_CONFIG_ASF = 0x0d,
288 EEPROM_DEVICE_ID = 0x23,
289 EEPROM_SMBUS_ADDR = 0x90,
290 } EEPROMOffset;
291
292 /* Bit values for EEPROM ID word. */
293 typedef enum {
294 EEPROM_ID_MDM = BIT(0), /* Modem */
295 EEPROM_ID_STB = BIT(1), /* Standby Enable */
296 EEPROM_ID_WMR = BIT(2), /* ??? */
297 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
298 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
299 EEPROM_ID_ALT = BIT(7), /* */
300 /* BITS(10, 8) device revision */
301 EEPROM_ID_BD = BIT(11), /* boot disable */
302 EEPROM_ID_ID = BIT(13), /* id bit */
303 /* BITS(15, 14) signature */
304 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
305 } eeprom_id_bit;
306
307 /* Default values for MDI (PHY) registers */
308 static const uint16_t eepro100_mdi_default[] = {
309 /* MDI Registers 0 - 6, 7 */
310 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
311 /* MDI Registers 8 - 15 */
312 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
313 /* MDI Registers 16 - 31 */
314 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
316 };
317
318 /* Readonly mask for MDI (PHY) registers */
319 static const uint16_t eepro100_mdi_mask[] = {
320 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
321 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
322 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
323 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
324 };
325
326 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
327
328 /* Read a 16 bit control/status (CSR) register. */
329 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
330 {
331 assert(!((uintptr_t)&s->mem[addr] & 1));
332 return lduw_le_p(&s->mem[addr]);
333 }
334
335 /* Read a 32 bit control/status (CSR) register. */
336 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
337 {
338 assert(!((uintptr_t)&s->mem[addr] & 3));
339 return ldl_le_p(&s->mem[addr]);
340 }
341
342 /* Write a 16 bit control/status (CSR) register. */
343 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
344 uint16_t val)
345 {
346 assert(!((uintptr_t)&s->mem[addr] & 1));
347 stw_le_p(&s->mem[addr], val);
348 }
349
350 /* Read a 32 bit control/status (CSR) register. */
351 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
352 uint32_t val)
353 {
354 assert(!((uintptr_t)&s->mem[addr] & 3));
355 stl_le_p(&s->mem[addr], val);
356 }
357
358 #if defined(DEBUG_EEPRO100)
359 static const char *nic_dump(const uint8_t * buf, unsigned size)
360 {
361 static char dump[3 * 16 + 1];
362 char *p = &dump[0];
363 if (size > 16) {
364 size = 16;
365 }
366 while (size-- > 0) {
367 p += sprintf(p, " %02x", *buf++);
368 }
369 return dump;
370 }
371 #endif /* DEBUG_EEPRO100 */
372
373 enum scb_stat_ack {
374 stat_ack_not_ours = 0x00,
375 stat_ack_sw_gen = 0x04,
376 stat_ack_rnr = 0x10,
377 stat_ack_cu_idle = 0x20,
378 stat_ack_frame_rx = 0x40,
379 stat_ack_cu_cmd_done = 0x80,
380 stat_ack_not_present = 0xFF,
381 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
382 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
383 };
384
385 static void disable_interrupt(EEPRO100State * s)
386 {
387 if (s->int_stat) {
388 TRACE(INT, logout("interrupt disabled\n"));
389 pci_irq_deassert(&s->dev);
390 s->int_stat = 0;
391 }
392 }
393
394 static void enable_interrupt(EEPRO100State * s)
395 {
396 if (!s->int_stat) {
397 TRACE(INT, logout("interrupt enabled\n"));
398 pci_irq_assert(&s->dev);
399 s->int_stat = 1;
400 }
401 }
402
403 static void eepro100_acknowledge(EEPRO100State * s)
404 {
405 s->scb_stat &= ~s->mem[SCBAck];
406 s->mem[SCBAck] = s->scb_stat;
407 if (s->scb_stat == 0) {
408 disable_interrupt(s);
409 }
410 }
411
412 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
413 {
414 uint8_t mask = ~s->mem[SCBIntmask];
415 s->mem[SCBAck] |= status;
416 status = s->scb_stat = s->mem[SCBAck];
417 status &= (mask | 0x0f);
418 #if 0
419 status &= (~s->mem[SCBIntmask] | 0x0xf);
420 #endif
421 if (status && (mask & 0x01)) {
422 /* SCB mask and SCB Bit M do not disable interrupt. */
423 enable_interrupt(s);
424 } else if (s->int_stat) {
425 disable_interrupt(s);
426 }
427 }
428
429 static void eepro100_cx_interrupt(EEPRO100State * s)
430 {
431 /* CU completed action command. */
432 /* Transmit not ok (82557 only, not in emulation). */
433 eepro100_interrupt(s, 0x80);
434 }
435
436 static void eepro100_cna_interrupt(EEPRO100State * s)
437 {
438 /* CU left the active state. */
439 eepro100_interrupt(s, 0x20);
440 }
441
442 static void eepro100_fr_interrupt(EEPRO100State * s)
443 {
444 /* RU received a complete frame. */
445 eepro100_interrupt(s, 0x40);
446 }
447
448 static void eepro100_rnr_interrupt(EEPRO100State * s)
449 {
450 /* RU is not ready. */
451 eepro100_interrupt(s, 0x10);
452 }
453
454 static void eepro100_mdi_interrupt(EEPRO100State * s)
455 {
456 /* MDI completed read or write cycle. */
457 eepro100_interrupt(s, 0x08);
458 }
459
460 static void eepro100_swi_interrupt(EEPRO100State * s)
461 {
462 /* Software has requested an interrupt. */
463 eepro100_interrupt(s, 0x04);
464 }
465
466 #if 0
467 static void eepro100_fcp_interrupt(EEPRO100State * s)
468 {
469 /* Flow control pause interrupt (82558 and later). */
470 eepro100_interrupt(s, 0x01);
471 }
472 #endif
473
474 static void e100_pci_reset(EEPRO100State *s, Error **errp)
475 {
476 E100PCIDeviceInfo *info = eepro100_get_class(s);
477 uint32_t device = s->device;
478 uint8_t *pci_conf = s->dev.config;
479
480 TRACE(OTHER, logout("%p\n", s));
481
482 /* PCI Status */
483 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
484 PCI_STATUS_FAST_BACK);
485 /* PCI Latency Timer */
486 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
487 /* Capability Pointer is set by PCI framework. */
488 /* Interrupt Line */
489 /* Interrupt Pin */
490 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
491 /* Minimum Grant */
492 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
493 /* Maximum Latency */
494 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
495
496 s->stats_size = info->stats_size;
497 s->has_extended_tcb_support = info->has_extended_tcb_support;
498
499 switch (device) {
500 case i82550:
501 case i82551:
502 case i82557A:
503 case i82557B:
504 case i82557C:
505 case i82558A:
506 case i82558B:
507 case i82559A:
508 case i82559B:
509 case i82559ER:
510 case i82562:
511 case i82801:
512 case i82559C:
513 break;
514 default:
515 logout("Device %X is undefined!\n", device);
516 }
517
518 /* Standard TxCB. */
519 s->configuration[6] |= BIT(4);
520
521 /* Standard statistical counters. */
522 s->configuration[6] |= BIT(5);
523
524 if (s->stats_size == 80) {
525 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
526 if (s->configuration[6] & BIT(2)) {
527 /* TCO statistical counters. */
528 assert(s->configuration[6] & BIT(5));
529 } else {
530 if (s->configuration[6] & BIT(5)) {
531 /* No extended statistical counters, i82557 compatible. */
532 s->stats_size = 64;
533 } else {
534 /* i82558 compatible. */
535 s->stats_size = 76;
536 }
537 }
538 } else {
539 if (s->configuration[6] & BIT(5)) {
540 /* No extended statistical counters. */
541 s->stats_size = 64;
542 }
543 }
544 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
545
546 if (info->power_management) {
547 /* Power Management Capabilities */
548 int cfg_offset = 0xdc;
549 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
550 cfg_offset, PCI_PM_SIZEOF,
551 errp);
552 if (r < 0) {
553 return;
554 }
555
556 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
557 #if 0 /* TODO: replace dummy code for power management emulation. */
558 /* TODO: Power Management Control / Status. */
559 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
560 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
561 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
562 #endif
563 }
564
565 #if EEPROM_SIZE > 0
566 if (device == i82557C || device == i82558B || device == i82559C) {
567 /*
568 TODO: get vendor id from EEPROM for i82557C or later.
569 TODO: get device id from EEPROM for i82557C or later.
570 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
571 TODO: header type is determined by EEPROM for i82559.
572 TODO: get subsystem id from EEPROM for i82557C or later.
573 TODO: get subsystem vendor id from EEPROM for i82557C or later.
574 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
575 TODO: capability pointer depends on EEPROM for i82558.
576 */
577 logout("Get device id and revision from EEPROM!!!\n");
578 }
579 #endif /* EEPROM_SIZE > 0 */
580 }
581
582 static void nic_selective_reset(EEPRO100State * s)
583 {
584 size_t i;
585 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
586 #if 0
587 eeprom93xx_reset(s->eeprom);
588 #endif
589 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
590 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
591 if (s->device == i82557B || s->device == i82557C)
592 eeprom_contents[5] = 0x0100;
593 eeprom_contents[EEPROM_PHY_ID] = 1;
594 uint16_t sum = 0;
595 for (i = 0; i < EEPROM_SIZE - 1; i++) {
596 sum += eeprom_contents[i];
597 }
598 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
599 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
600
601 memset(s->mem, 0, sizeof(s->mem));
602 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
603
604 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
605 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
606 }
607
608 static void nic_reset(void *opaque)
609 {
610 EEPRO100State *s = opaque;
611 TRACE(OTHER, logout("%p\n", s));
612 /* TODO: Clearing of hash register for selective reset, too? */
613 memset(&s->mult[0], 0, sizeof(s->mult));
614 nic_selective_reset(s);
615 }
616
617 #if defined(DEBUG_EEPRO100)
618 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
619 "Command/Status",
620 "General Pointer",
621 "Port",
622 "EEPROM/Flash Control",
623 "MDI Control",
624 "Receive DMA Byte Count",
625 "Flow Control",
626 "General Status/Control"
627 };
628
629 static char *regname(uint32_t addr)
630 {
631 static char buf[32];
632 if (addr < PCI_IO_SIZE) {
633 const char *r = e100_reg[addr / 4];
634 if (r != 0) {
635 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
636 } else {
637 snprintf(buf, sizeof(buf), "0x%02x", addr);
638 }
639 } else {
640 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
641 }
642 return buf;
643 }
644 #endif /* DEBUG_EEPRO100 */
645
646 /*****************************************************************************
647 *
648 * Command emulation.
649 *
650 ****************************************************************************/
651
652 #if 0
653 static uint16_t eepro100_read_command(EEPRO100State * s)
654 {
655 uint16_t val = 0xffff;
656 TRACE(OTHER, logout("val=0x%04x\n", val));
657 return val;
658 }
659 #endif
660
661 /* Commands that can be put in a command list entry. */
662 enum commands {
663 CmdNOp = 0,
664 CmdIASetup = 1,
665 CmdConfigure = 2,
666 CmdMulticastList = 3,
667 CmdTx = 4,
668 CmdTDR = 5, /* load microcode */
669 CmdDump = 6,
670 CmdDiagnose = 7,
671
672 /* And some extra flags: */
673 CmdSuspend = 0x4000, /* Suspend after completion. */
674 CmdIntr = 0x2000, /* Interrupt after completion. */
675 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
676 };
677
678 static cu_state_t get_cu_state(EEPRO100State * s)
679 {
680 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
681 }
682
683 static void set_cu_state(EEPRO100State * s, cu_state_t state)
684 {
685 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
686 }
687
688 static ru_state_t get_ru_state(EEPRO100State * s)
689 {
690 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
691 }
692
693 static void set_ru_state(EEPRO100State * s, ru_state_t state)
694 {
695 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
696 }
697
698 static void dump_statistics(EEPRO100State * s)
699 {
700 /* Dump statistical data. Most data is never changed by the emulation
701 * and always 0, so we first just copy the whole block and then those
702 * values which really matter.
703 * Number of data should check configuration!!!
704 */
705 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
706 stl_le_pci_dma(&s->dev, s->statsaddr + 0,
707 s->statistics.tx_good_frames);
708 stl_le_pci_dma(&s->dev, s->statsaddr + 36,
709 s->statistics.rx_good_frames);
710 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
711 s->statistics.rx_resource_errors);
712 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
713 s->statistics.rx_short_frame_errors);
714 #if 0
715 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
716 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
717 missing("CU dump statistical counters");
718 #endif
719 }
720
721 static void read_cb(EEPRO100State *s)
722 {
723 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
724 s->tx.status = le16_to_cpu(s->tx.status);
725 s->tx.command = le16_to_cpu(s->tx.command);
726 s->tx.link = le32_to_cpu(s->tx.link);
727 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
728 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
729 }
730
731 static void tx_command(EEPRO100State *s)
732 {
733 uint32_t tbd_array = s->tx.tbd_array_addr;
734 uint16_t tcb_bytes = s->tx.tcb_bytes & 0x3fff;
735 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
736 uint8_t buf[2600];
737 uint16_t size = 0;
738 uint32_t tbd_address = s->cb_address + 0x10;
739 TRACE(RXTX, logout
740 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
741 tbd_array, tcb_bytes, s->tx.tbd_count));
742
743 if (tcb_bytes > 2600) {
744 logout("TCB byte count too large, using 2600\n");
745 tcb_bytes = 2600;
746 }
747 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
748 logout
749 ("illegal values of TBD array address and TCB byte count!\n");
750 }
751 assert(tcb_bytes <= sizeof(buf));
752 while (size < tcb_bytes) {
753 TRACE(RXTX, logout
754 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
755 tbd_address, tcb_bytes));
756 pci_dma_read(&s->dev, tbd_address, &buf[size], tcb_bytes);
757 size += tcb_bytes;
758 }
759 if (tbd_array == 0xffffffff) {
760 /* Simplified mode. Was already handled by code above. */
761 } else {
762 /* Flexible mode. */
763 uint8_t tbd_count = 0;
764 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
765 /* Extended Flexible TCB. */
766 for (; tbd_count < 2; tbd_count++) {
767 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev,
768 tbd_address);
769 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev,
770 tbd_address + 4);
771 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev,
772 tbd_address + 6);
773 tbd_address += 8;
774 TRACE(RXTX, logout
775 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
776 tx_buffer_address, tx_buffer_size));
777 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
778 pci_dma_read(&s->dev, tx_buffer_address,
779 &buf[size], tx_buffer_size);
780 size += tx_buffer_size;
781 if (tx_buffer_el & 1) {
782 break;
783 }
784 }
785 }
786 tbd_address = tbd_array;
787 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
788 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
789 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
790 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
791 tbd_address += 8;
792 TRACE(RXTX, logout
793 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
794 tx_buffer_address, tx_buffer_size));
795 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
796 pci_dma_read(&s->dev, tx_buffer_address,
797 &buf[size], tx_buffer_size);
798 size += tx_buffer_size;
799 if (tx_buffer_el & 1) {
800 break;
801 }
802 }
803 }
804 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
805 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
806 s->statistics.tx_good_frames++;
807 /* Transmit with bad status would raise an CX/TNO interrupt.
808 * (82557 only). Emulation never has bad status. */
809 #if 0
810 eepro100_cx_interrupt(s);
811 #endif
812 }
813
814 static void set_multicast_list(EEPRO100State *s)
815 {
816 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
817 uint16_t i;
818 memset(&s->mult[0], 0, sizeof(s->mult));
819 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
820 for (i = 0; i < multicast_count; i += 6) {
821 uint8_t multicast_addr[6];
822 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
823 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
824 unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) &
825 BITS(7, 2)) >> 2;
826 assert(mcast_idx < 64);
827 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
828 }
829 }
830
831 static void action_command(EEPRO100State *s)
832 {
833 /* The loop below won't stop if it gets special handcrafted data.
834 Therefore we limit the number of iterations. */
835 unsigned max_loop_count = 16;
836
837 for (;;) {
838 bool bit_el;
839 bool bit_s;
840 bool bit_i;
841 bool bit_nc;
842 uint16_t ok_status = STATUS_OK;
843 s->cb_address = s->cu_base + s->cu_offset;
844 read_cb(s);
845 bit_el = ((s->tx.command & COMMAND_EL) != 0);
846 bit_s = ((s->tx.command & COMMAND_S) != 0);
847 bit_i = ((s->tx.command & COMMAND_I) != 0);
848 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
849 #if 0
850 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
851 #endif
852
853 if (max_loop_count-- == 0) {
854 /* Prevent an endless loop. */
855 logout("loop in %s:%u\n", __FILE__, __LINE__);
856 break;
857 }
858
859 s->cu_offset = s->tx.link;
860 TRACE(OTHER,
861 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
862 s->tx.status, s->tx.command, s->tx.link));
863 switch (s->tx.command & COMMAND_CMD) {
864 case CmdNOp:
865 /* Do nothing. */
866 break;
867 case CmdIASetup:
868 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
869 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
870 break;
871 case CmdConfigure:
872 pci_dma_read(&s->dev, s->cb_address + 8,
873 &s->configuration[0], sizeof(s->configuration));
874 TRACE(OTHER, logout("configuration: %s\n",
875 nic_dump(&s->configuration[0], 16)));
876 TRACE(OTHER, logout("configuration: %s\n",
877 nic_dump(&s->configuration[16],
878 ARRAY_SIZE(s->configuration) - 16)));
879 if (s->configuration[20] & BIT(6)) {
880 TRACE(OTHER, logout("Multiple IA bit\n"));
881 }
882 break;
883 case CmdMulticastList:
884 set_multicast_list(s);
885 break;
886 case CmdTx:
887 if (bit_nc) {
888 missing("CmdTx: NC = 0");
889 ok_status = 0;
890 break;
891 }
892 tx_command(s);
893 break;
894 case CmdTDR:
895 TRACE(OTHER, logout("load microcode\n"));
896 /* Starting with offset 8, the command contains
897 * 64 dwords microcode which we just ignore here. */
898 break;
899 case CmdDiagnose:
900 TRACE(OTHER, logout("diagnose\n"));
901 /* Make sure error flag is not set. */
902 s->tx.status = 0;
903 break;
904 default:
905 missing("undefined command");
906 ok_status = 0;
907 break;
908 }
909 /* Write new status. */
910 stw_le_pci_dma(&s->dev, s->cb_address,
911 s->tx.status | ok_status | STATUS_C);
912 if (bit_i) {
913 /* CU completed action. */
914 eepro100_cx_interrupt(s);
915 }
916 if (bit_el) {
917 /* CU becomes idle. Terminate command loop. */
918 set_cu_state(s, cu_idle);
919 eepro100_cna_interrupt(s);
920 break;
921 } else if (bit_s) {
922 /* CU becomes suspended. Terminate command loop. */
923 set_cu_state(s, cu_suspended);
924 eepro100_cna_interrupt(s);
925 break;
926 } else {
927 /* More entries in list. */
928 TRACE(OTHER, logout("CU list with at least one more entry\n"));
929 }
930 }
931 TRACE(OTHER, logout("CU list empty\n"));
932 /* List is empty. Now CU is idle or suspended. */
933 }
934
935 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
936 {
937 cu_state_t cu_state;
938 switch (val) {
939 case CU_NOP:
940 /* No operation. */
941 break;
942 case CU_START:
943 cu_state = get_cu_state(s);
944 if (cu_state != cu_idle && cu_state != cu_suspended) {
945 /* Intel documentation says that CU must be idle or suspended
946 * for the CU start command. */
947 logout("unexpected CU state is %u\n", cu_state);
948 }
949 set_cu_state(s, cu_active);
950 s->cu_offset = e100_read_reg4(s, SCBPointer);
951 action_command(s);
952 break;
953 case CU_RESUME:
954 if (get_cu_state(s) != cu_suspended) {
955 logout("bad CU resume from CU state %u\n", get_cu_state(s));
956 /* Workaround for bad Linux eepro100 driver which resumes
957 * from idle state. */
958 #if 0
959 missing("cu resume");
960 #endif
961 set_cu_state(s, cu_suspended);
962 }
963 if (get_cu_state(s) == cu_suspended) {
964 TRACE(OTHER, logout("CU resuming\n"));
965 set_cu_state(s, cu_active);
966 action_command(s);
967 }
968 break;
969 case CU_STATSADDR:
970 /* Load dump counters address. */
971 s->statsaddr = e100_read_reg4(s, SCBPointer);
972 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
973 if (s->statsaddr & 3) {
974 /* Memory must be Dword aligned. */
975 logout("unaligned dump counters address\n");
976 /* Handling of misaligned addresses is undefined.
977 * Here we align the address by ignoring the lower bits. */
978 /* TODO: Test unaligned dump counter address on real hardware. */
979 s->statsaddr &= ~3;
980 }
981 break;
982 case CU_SHOWSTATS:
983 /* Dump statistical counters. */
984 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
985 dump_statistics(s);
986 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
987 break;
988 case CU_CMD_BASE:
989 /* Load CU base. */
990 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
991 s->cu_base = e100_read_reg4(s, SCBPointer);
992 break;
993 case CU_DUMPSTATS:
994 /* Dump and reset statistical counters. */
995 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
996 dump_statistics(s);
997 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
998 memset(&s->statistics, 0, sizeof(s->statistics));
999 break;
1000 case CU_SRESUME:
1001 /* CU static resume. */
1002 missing("CU static resume");
1003 break;
1004 default:
1005 missing("Undefined CU command");
1006 }
1007 }
1008
1009 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1010 {
1011 switch (val) {
1012 case RU_NOP:
1013 /* No operation. */
1014 break;
1015 case RX_START:
1016 /* RU start. */
1017 if (get_ru_state(s) != ru_idle) {
1018 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1019 #if 0
1020 assert(!"wrong RU state");
1021 #endif
1022 }
1023 set_ru_state(s, ru_ready);
1024 s->ru_offset = e100_read_reg4(s, SCBPointer);
1025 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1026 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1027 break;
1028 case RX_RESUME:
1029 /* Restart RU. */
1030 if (get_ru_state(s) != ru_suspended) {
1031 logout("RU state is %u, should be %u\n", get_ru_state(s),
1032 ru_suspended);
1033 #if 0
1034 assert(!"wrong RU state");
1035 #endif
1036 }
1037 set_ru_state(s, ru_ready);
1038 break;
1039 case RU_ABORT:
1040 /* RU abort. */
1041 if (get_ru_state(s) == ru_ready) {
1042 eepro100_rnr_interrupt(s);
1043 }
1044 set_ru_state(s, ru_idle);
1045 break;
1046 case RX_ADDR_LOAD:
1047 /* Load RU base. */
1048 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1049 s->ru_base = e100_read_reg4(s, SCBPointer);
1050 break;
1051 default:
1052 logout("val=0x%02x (undefined RU command)\n", val);
1053 missing("Undefined SU command");
1054 }
1055 }
1056
1057 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1058 {
1059 eepro100_ru_command(s, val & 0x0f);
1060 eepro100_cu_command(s, val & 0xf0);
1061 if ((val) == 0) {
1062 TRACE(OTHER, logout("val=0x%02x\n", val));
1063 }
1064 /* Clear command byte after command was accepted. */
1065 s->mem[SCBCmd] = 0;
1066 }
1067
1068 /*****************************************************************************
1069 *
1070 * EEPROM emulation.
1071 *
1072 ****************************************************************************/
1073
1074 #define EEPROM_CS 0x02
1075 #define EEPROM_SK 0x01
1076 #define EEPROM_DI 0x04
1077 #define EEPROM_DO 0x08
1078
1079 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1080 {
1081 uint16_t val = e100_read_reg2(s, SCBeeprom);
1082 if (eeprom93xx_read(s->eeprom)) {
1083 val |= EEPROM_DO;
1084 } else {
1085 val &= ~EEPROM_DO;
1086 }
1087 TRACE(EEPROM, logout("val=0x%04x\n", val));
1088 return val;
1089 }
1090
1091 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1092 {
1093 TRACE(EEPROM, logout("val=0x%02x\n", val));
1094
1095 /* mask unwritable bits */
1096 #if 0
1097 val = SET_MASKED(val, 0x31, eeprom->value);
1098 #endif
1099
1100 int eecs = ((val & EEPROM_CS) != 0);
1101 int eesk = ((val & EEPROM_SK) != 0);
1102 int eedi = ((val & EEPROM_DI) != 0);
1103 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1104 }
1105
1106 /*****************************************************************************
1107 *
1108 * MDI emulation.
1109 *
1110 ****************************************************************************/
1111
1112 #if defined(DEBUG_EEPRO100)
1113 static const char * const mdi_op_name[] = {
1114 "opcode 0",
1115 "write",
1116 "read",
1117 "opcode 3"
1118 };
1119
1120 static const char * const mdi_reg_name[] = {
1121 "Control",
1122 "Status",
1123 "PHY Identification (Word 1)",
1124 "PHY Identification (Word 2)",
1125 "Auto-Negotiation Advertisement",
1126 "Auto-Negotiation Link Partner Ability",
1127 "Auto-Negotiation Expansion"
1128 };
1129
1130 static const char *reg2name(uint8_t reg)
1131 {
1132 static char buffer[10];
1133 const char *p = buffer;
1134 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1135 p = mdi_reg_name[reg];
1136 } else {
1137 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1138 }
1139 return p;
1140 }
1141 #endif /* DEBUG_EEPRO100 */
1142
1143 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1144 {
1145 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1146
1147 #ifdef DEBUG_EEPRO100
1148 uint8_t raiseint = (val & BIT(29)) >> 29;
1149 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1150 uint8_t phy = (val & BITS(25, 21)) >> 21;
1151 uint8_t reg = (val & BITS(20, 16)) >> 16;
1152 uint16_t data = (val & BITS(15, 0));
1153 #endif
1154 /* Emulation takes no time to finish MDI transaction. */
1155 val |= BIT(28);
1156 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1157 val, raiseint, mdi_op_name[opcode], phy,
1158 reg2name(reg), data));
1159 return val;
1160 }
1161
1162 static void eepro100_write_mdi(EEPRO100State *s)
1163 {
1164 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1165 uint8_t raiseint = (val & BIT(29)) >> 29;
1166 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1167 uint8_t phy = (val & BITS(25, 21)) >> 21;
1168 uint8_t reg = (val & BITS(20, 16)) >> 16;
1169 uint16_t data = (val & BITS(15, 0));
1170 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1171 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1172 if (phy != 1) {
1173 /* Unsupported PHY address. */
1174 #if 0
1175 logout("phy must be 1 but is %u\n", phy);
1176 #endif
1177 data = 0;
1178 } else if (opcode != 1 && opcode != 2) {
1179 /* Unsupported opcode. */
1180 logout("opcode must be 1 or 2 but is %u\n", opcode);
1181 data = 0;
1182 } else if (reg > 6) {
1183 /* Unsupported register. */
1184 logout("register must be 0...6 but is %u\n", reg);
1185 data = 0;
1186 } else {
1187 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1188 val, raiseint, mdi_op_name[opcode], phy,
1189 reg2name(reg), data));
1190 if (opcode == 1) {
1191 /* MDI write */
1192 switch (reg) {
1193 case 0: /* Control Register */
1194 if (data & 0x8000) {
1195 /* Reset status and control registers to default. */
1196 s->mdimem[0] = eepro100_mdi_default[0];
1197 s->mdimem[1] = eepro100_mdi_default[1];
1198 data = s->mdimem[reg];
1199 } else {
1200 /* Restart Auto Configuration = Normal Operation */
1201 data &= ~0x0200;
1202 }
1203 break;
1204 case 1: /* Status Register */
1205 missing("not writable");
1206 break;
1207 case 2: /* PHY Identification Register (Word 1) */
1208 case 3: /* PHY Identification Register (Word 2) */
1209 missing("not implemented");
1210 break;
1211 case 4: /* Auto-Negotiation Advertisement Register */
1212 case 5: /* Auto-Negotiation Link Partner Ability Register */
1213 break;
1214 case 6: /* Auto-Negotiation Expansion Register */
1215 default:
1216 missing("not implemented");
1217 }
1218 s->mdimem[reg] &= eepro100_mdi_mask[reg];
1219 s->mdimem[reg] |= data & ~eepro100_mdi_mask[reg];
1220 } else if (opcode == 2) {
1221 /* MDI read */
1222 switch (reg) {
1223 case 0: /* Control Register */
1224 if (data & 0x8000) {
1225 /* Reset status and control registers to default. */
1226 s->mdimem[0] = eepro100_mdi_default[0];
1227 s->mdimem[1] = eepro100_mdi_default[1];
1228 }
1229 break;
1230 case 1: /* Status Register */
1231 s->mdimem[reg] |= 0x0020;
1232 break;
1233 case 2: /* PHY Identification Register (Word 1) */
1234 case 3: /* PHY Identification Register (Word 2) */
1235 case 4: /* Auto-Negotiation Advertisement Register */
1236 break;
1237 case 5: /* Auto-Negotiation Link Partner Ability Register */
1238 s->mdimem[reg] = 0x41fe;
1239 break;
1240 case 6: /* Auto-Negotiation Expansion Register */
1241 s->mdimem[reg] = 0x0001;
1242 break;
1243 }
1244 data = s->mdimem[reg];
1245 }
1246 /* Emulation takes no time to finish MDI transaction.
1247 * Set MDI bit in SCB status register. */
1248 s->mem[SCBAck] |= 0x08;
1249 val |= BIT(28);
1250 if (raiseint) {
1251 eepro100_mdi_interrupt(s);
1252 }
1253 }
1254 val = (val & 0xffff0000) + data;
1255 e100_write_reg4(s, SCBCtrlMDI, val);
1256 }
1257
1258 /*****************************************************************************
1259 *
1260 * Port emulation.
1261 *
1262 ****************************************************************************/
1263
1264 #define PORT_SOFTWARE_RESET 0
1265 #define PORT_SELFTEST 1
1266 #define PORT_SELECTIVE_RESET 2
1267 #define PORT_DUMP 3
1268 #define PORT_SELECTION_MASK 3
1269
1270 typedef struct {
1271 uint32_t st_sign; /* Self Test Signature */
1272 uint32_t st_result; /* Self Test Results */
1273 } eepro100_selftest_t;
1274
1275 static uint32_t eepro100_read_port(EEPRO100State * s)
1276 {
1277 return 0;
1278 }
1279
1280 static void eepro100_write_port(EEPRO100State *s)
1281 {
1282 uint32_t val = e100_read_reg4(s, SCBPort);
1283 uint32_t address = (val & ~PORT_SELECTION_MASK);
1284 uint8_t selection = (val & PORT_SELECTION_MASK);
1285 switch (selection) {
1286 case PORT_SOFTWARE_RESET:
1287 nic_reset(s);
1288 break;
1289 case PORT_SELFTEST:
1290 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1291 eepro100_selftest_t data;
1292 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
1293 data.st_sign = 0xffffffff;
1294 data.st_result = 0;
1295 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
1296 break;
1297 case PORT_SELECTIVE_RESET:
1298 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1299 nic_selective_reset(s);
1300 break;
1301 default:
1302 logout("val=0x%08x\n", val);
1303 missing("unknown port selection");
1304 }
1305 }
1306
1307 /*****************************************************************************
1308 *
1309 * General hardware emulation.
1310 *
1311 ****************************************************************************/
1312
1313 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1314 {
1315 uint8_t val = 0;
1316 if (addr <= sizeof(s->mem) - sizeof(val)) {
1317 val = s->mem[addr];
1318 }
1319
1320 switch (addr) {
1321 case SCBStatus:
1322 case SCBAck:
1323 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1324 break;
1325 case SCBCmd:
1326 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1327 #if 0
1328 val = eepro100_read_command(s);
1329 #endif
1330 break;
1331 case SCBIntmask:
1332 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1333 break;
1334 case SCBPort + 3:
1335 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1336 break;
1337 case SCBeeprom:
1338 val = eepro100_read_eeprom(s);
1339 break;
1340 case SCBCtrlMDI:
1341 case SCBCtrlMDI + 1:
1342 case SCBCtrlMDI + 2:
1343 case SCBCtrlMDI + 3:
1344 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1345 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1346 break;
1347 case SCBpmdr: /* Power Management Driver Register */
1348 val = 0;
1349 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1350 break;
1351 case SCBgctrl: /* General Control Register */
1352 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1353 break;
1354 case SCBgstat: /* General Status Register */
1355 /* 100 Mbps full duplex, valid link */
1356 val = 0x07;
1357 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1358 break;
1359 default:
1360 logout("addr=%s val=0x%02x\n", regname(addr), val);
1361 missing("unknown byte read");
1362 }
1363 return val;
1364 }
1365
1366 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1367 {
1368 uint16_t val = 0;
1369 if (addr <= sizeof(s->mem) - sizeof(val)) {
1370 val = e100_read_reg2(s, addr);
1371 }
1372
1373 switch (addr) {
1374 case SCBStatus:
1375 case SCBCmd:
1376 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1377 break;
1378 case SCBeeprom:
1379 val = eepro100_read_eeprom(s);
1380 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1381 break;
1382 case SCBCtrlMDI:
1383 case SCBCtrlMDI + 2:
1384 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1385 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1386 break;
1387 default:
1388 logout("addr=%s val=0x%04x\n", regname(addr), val);
1389 missing("unknown word read");
1390 }
1391 return val;
1392 }
1393
1394 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1395 {
1396 uint32_t val = 0;
1397 if (addr <= sizeof(s->mem) - sizeof(val)) {
1398 val = e100_read_reg4(s, addr);
1399 }
1400
1401 switch (addr) {
1402 case SCBStatus:
1403 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1404 break;
1405 case SCBPointer:
1406 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1407 break;
1408 case SCBPort:
1409 val = eepro100_read_port(s);
1410 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1411 break;
1412 case SCBflash:
1413 val = eepro100_read_eeprom(s);
1414 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1415 break;
1416 case SCBCtrlMDI:
1417 val = eepro100_read_mdi(s);
1418 break;
1419 default:
1420 logout("addr=%s val=0x%08x\n", regname(addr), val);
1421 missing("unknown longword read");
1422 }
1423 return val;
1424 }
1425
1426 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1427 {
1428 /* SCBStatus is readonly. */
1429 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1430 s->mem[addr] = val;
1431 }
1432
1433 switch (addr) {
1434 case SCBStatus:
1435 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1436 break;
1437 case SCBAck:
1438 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1439 eepro100_acknowledge(s);
1440 break;
1441 case SCBCmd:
1442 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1443 eepro100_write_command(s, val);
1444 break;
1445 case SCBIntmask:
1446 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1447 if (val & BIT(1)) {
1448 eepro100_swi_interrupt(s);
1449 }
1450 eepro100_interrupt(s, 0);
1451 break;
1452 case SCBPointer:
1453 case SCBPointer + 1:
1454 case SCBPointer + 2:
1455 case SCBPointer + 3:
1456 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1457 break;
1458 case SCBPort:
1459 case SCBPort + 1:
1460 case SCBPort + 2:
1461 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1462 break;
1463 case SCBPort + 3:
1464 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1465 eepro100_write_port(s);
1466 break;
1467 case SCBFlow: /* does not exist on 82557 */
1468 case SCBFlow + 1:
1469 case SCBFlow + 2:
1470 case SCBpmdr: /* does not exist on 82557 */
1471 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1472 break;
1473 case SCBeeprom:
1474 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1475 eepro100_write_eeprom(s->eeprom, val);
1476 break;
1477 case SCBCtrlMDI:
1478 case SCBCtrlMDI + 1:
1479 case SCBCtrlMDI + 2:
1480 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1481 break;
1482 case SCBCtrlMDI + 3:
1483 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1484 eepro100_write_mdi(s);
1485 break;
1486 default:
1487 logout("addr=%s val=0x%02x\n", regname(addr), val);
1488 missing("unknown byte write");
1489 }
1490 }
1491
1492 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1493 {
1494 /* SCBStatus is readonly. */
1495 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1496 e100_write_reg2(s, addr, val);
1497 }
1498
1499 switch (addr) {
1500 case SCBStatus:
1501 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1502 s->mem[SCBAck] = (val >> 8);
1503 eepro100_acknowledge(s);
1504 break;
1505 case SCBCmd:
1506 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1507 eepro100_write_command(s, val);
1508 eepro100_write1(s, SCBIntmask, val >> 8);
1509 break;
1510 case SCBPointer:
1511 case SCBPointer + 2:
1512 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1513 break;
1514 case SCBPort:
1515 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1516 break;
1517 case SCBPort + 2:
1518 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1519 eepro100_write_port(s);
1520 break;
1521 case SCBeeprom:
1522 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1523 eepro100_write_eeprom(s->eeprom, val);
1524 break;
1525 case SCBCtrlMDI:
1526 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1527 break;
1528 case SCBCtrlMDI + 2:
1529 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1530 eepro100_write_mdi(s);
1531 break;
1532 default:
1533 logout("addr=%s val=0x%04x\n", regname(addr), val);
1534 missing("unknown word write");
1535 }
1536 }
1537
1538 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1539 {
1540 if (addr <= sizeof(s->mem) - sizeof(val)) {
1541 e100_write_reg4(s, addr, val);
1542 }
1543
1544 switch (addr) {
1545 case SCBPointer:
1546 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1547 break;
1548 case SCBPort:
1549 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1550 eepro100_write_port(s);
1551 break;
1552 case SCBflash:
1553 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1554 val = val >> 16;
1555 eepro100_write_eeprom(s->eeprom, val);
1556 break;
1557 case SCBCtrlMDI:
1558 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1559 eepro100_write_mdi(s);
1560 break;
1561 default:
1562 logout("addr=%s val=0x%08x\n", regname(addr), val);
1563 missing("unknown longword write");
1564 }
1565 }
1566
1567 static uint64_t eepro100_read(void *opaque, hwaddr addr,
1568 unsigned size)
1569 {
1570 EEPRO100State *s = opaque;
1571
1572 switch (size) {
1573 case 1: return eepro100_read1(s, addr);
1574 case 2: return eepro100_read2(s, addr);
1575 case 4: return eepro100_read4(s, addr);
1576 default: abort();
1577 }
1578 }
1579
1580 static void eepro100_write(void *opaque, hwaddr addr,
1581 uint64_t data, unsigned size)
1582 {
1583 EEPRO100State *s = opaque;
1584
1585 switch (size) {
1586 case 1:
1587 eepro100_write1(s, addr, data);
1588 break;
1589 case 2:
1590 eepro100_write2(s, addr, data);
1591 break;
1592 case 4:
1593 eepro100_write4(s, addr, data);
1594 break;
1595 default:
1596 abort();
1597 }
1598 }
1599
1600 static const MemoryRegionOps eepro100_ops = {
1601 .read = eepro100_read,
1602 .write = eepro100_write,
1603 .endianness = DEVICE_LITTLE_ENDIAN,
1604 };
1605
1606 static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size)
1607 {
1608 /* TODO:
1609 * - Magic packets should set bit 30 in power management driver register.
1610 * - Interesting packets should set bit 29 in power management driver register.
1611 */
1612 EEPRO100State *s = qemu_get_nic_opaque(nc);
1613 uint16_t rfd_status = 0xa000;
1614 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1615 uint8_t min_buf[60];
1616 #endif
1617 static const uint8_t broadcast_macaddr[6] =
1618 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1619
1620 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1621 /* Pad to minimum Ethernet frame length */
1622 if (size < sizeof(min_buf)) {
1623 memcpy(min_buf, buf, size);
1624 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1625 buf = min_buf;
1626 size = sizeof(min_buf);
1627 }
1628 #endif
1629
1630 if (s->configuration[8] & 0x80) {
1631 /* CSMA is disabled. */
1632 logout("%p received while CSMA is disabled\n", s);
1633 return -1;
1634 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1635 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1636 /* Short frame and configuration byte 7/0 (discard short receive) set:
1637 * Short frame is discarded */
1638 logout("%p received short frame (%zu byte)\n", s, size);
1639 s->statistics.rx_short_frame_errors++;
1640 return -1;
1641 #endif
1642 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1643 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1644 * Long frames are discarded. */
1645 logout("%p received long frame (%zu byte), ignored\n", s, size);
1646 return -1;
1647 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1648 /* Frame matches individual address. */
1649 /* TODO: check configuration byte 15/4 (ignore U/L). */
1650 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1651 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1652 /* Broadcast frame. */
1653 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1654 rfd_status |= 0x0002;
1655 } else if (buf[0] & 0x01) {
1656 /* Multicast frame. */
1657 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1658 if (s->configuration[21] & BIT(3)) {
1659 /* Multicast all bit is set, receive all multicast frames. */
1660 } else {
1661 unsigned mcast_idx = (net_crc32(buf, ETH_ALEN) & BITS(7, 2)) >> 2;
1662 assert(mcast_idx < 64);
1663 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1664 /* Multicast frame is allowed in hash table. */
1665 } else if (s->configuration[15] & BIT(0)) {
1666 /* Promiscuous: receive all. */
1667 rfd_status |= 0x0004;
1668 } else {
1669 TRACE(RXTX, logout("%p multicast ignored\n", s));
1670 return -1;
1671 }
1672 }
1673 /* TODO: Next not for promiscuous mode? */
1674 rfd_status |= 0x0002;
1675 } else if (s->configuration[15] & BIT(0)) {
1676 /* Promiscuous: receive all. */
1677 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1678 rfd_status |= 0x0004;
1679 } else if (s->configuration[20] & BIT(6)) {
1680 /* Multiple IA bit set. */
1681 unsigned mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
1682 assert(mcast_idx < 64);
1683 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1684 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1685 } else {
1686 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1687 return -1;
1688 }
1689 } else {
1690 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1691 nic_dump(buf, size)));
1692 return size;
1693 }
1694
1695 if (get_ru_state(s) != ru_ready) {
1696 /* No resources available. */
1697 logout("no resources, state=%u\n", get_ru_state(s));
1698 /* TODO: RNR interrupt only at first failed frame? */
1699 eepro100_rnr_interrupt(s);
1700 s->statistics.rx_resource_errors++;
1701 #if 0
1702 assert(!"no resources");
1703 #endif
1704 return -1;
1705 }
1706 /* !!! */
1707 eepro100_rx_t rx;
1708 pci_dma_read(&s->dev, s->ru_base + s->ru_offset,
1709 &rx, sizeof(eepro100_rx_t));
1710 uint16_t rfd_command = le16_to_cpu(rx.command);
1711 uint16_t rfd_size = le16_to_cpu(rx.size);
1712
1713 if (size > rfd_size) {
1714 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1715 "(%zu bytes); data truncated\n", rfd_size, size);
1716 size = rfd_size;
1717 }
1718 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1719 if (size < 64) {
1720 rfd_status |= 0x0080;
1721 }
1722 #endif
1723 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1724 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1725 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1726 offsetof(eepro100_rx_t, status), rfd_status);
1727 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1728 offsetof(eepro100_rx_t, count), size);
1729 /* Early receive interrupt not supported. */
1730 #if 0
1731 eepro100_er_interrupt(s);
1732 #endif
1733 /* Receive CRC Transfer not supported. */
1734 if (s->configuration[18] & BIT(2)) {
1735 missing("Receive CRC Transfer");
1736 return -1;
1737 }
1738 /* TODO: check stripping enable bit. */
1739 #if 0
1740 assert(!(s->configuration[17] & BIT(0)));
1741 #endif
1742 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1743 sizeof(eepro100_rx_t), buf, size);
1744 s->statistics.rx_good_frames++;
1745 eepro100_fr_interrupt(s);
1746 s->ru_offset = le32_to_cpu(rx.link);
1747 if (rfd_command & COMMAND_EL) {
1748 /* EL bit is set, so this was the last frame. */
1749 logout("receive: Running out of frames\n");
1750 set_ru_state(s, ru_no_resources);
1751 eepro100_rnr_interrupt(s);
1752 }
1753 if (rfd_command & COMMAND_S) {
1754 /* S bit is set. */
1755 set_ru_state(s, ru_suspended);
1756 }
1757 return size;
1758 }
1759
1760 static const VMStateDescription vmstate_eepro100 = {
1761 .version_id = 3,
1762 .minimum_version_id = 2,
1763 .fields = (VMStateField[]) {
1764 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1765 VMSTATE_UNUSED(32),
1766 VMSTATE_BUFFER(mult, EEPRO100State),
1767 VMSTATE_BUFFER(mem, EEPRO100State),
1768 /* Save all members of struct between scb_stat and mem. */
1769 VMSTATE_UINT8(scb_stat, EEPRO100State),
1770 VMSTATE_UINT8(int_stat, EEPRO100State),
1771 VMSTATE_UNUSED(3*4),
1772 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1773 VMSTATE_UNUSED(19*4),
1774 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1775 /* The eeprom should be saved and restored by its own routines. */
1776 VMSTATE_UINT32(device, EEPRO100State),
1777 /* TODO check device. */
1778 VMSTATE_UINT32(cu_base, EEPRO100State),
1779 VMSTATE_UINT32(cu_offset, EEPRO100State),
1780 VMSTATE_UINT32(ru_base, EEPRO100State),
1781 VMSTATE_UINT32(ru_offset, EEPRO100State),
1782 VMSTATE_UINT32(statsaddr, EEPRO100State),
1783 /* Save eepro100_stats_t statistics. */
1784 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1785 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1786 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1787 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1788 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1789 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1790 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1791 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1792 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1793 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1794 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1795 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1796 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1797 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1798 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1799 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1800 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1801 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1802 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1803 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1804 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1805 /* Configuration bytes. */
1806 VMSTATE_BUFFER(configuration, EEPRO100State),
1807 VMSTATE_END_OF_LIST()
1808 }
1809 };
1810
1811 static void pci_nic_uninit(PCIDevice *pci_dev)
1812 {
1813 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1814
1815 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1816 g_free(s->vmstate);
1817 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1818 qemu_del_nic(s->nic);
1819 }
1820
1821 static NetClientInfo net_eepro100_info = {
1822 .type = NET_CLIENT_DRIVER_NIC,
1823 .size = sizeof(NICState),
1824 .receive = nic_receive,
1825 };
1826
1827 static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
1828 {
1829 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1830 E100PCIDeviceInfo *info = eepro100_get_class(s);
1831 Error *local_err = NULL;
1832
1833 TRACE(OTHER, logout("\n"));
1834
1835 s->device = info->device;
1836
1837 e100_pci_reset(s, &local_err);
1838 if (local_err) {
1839 error_propagate(errp, local_err);
1840 return;
1841 }
1842
1843 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1844 * i82559 and later support 64 or 256 word EEPROM. */
1845 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1846
1847 /* Handler for memory-mapped I/O */
1848 memory_region_init_io(&s->mmio_bar, OBJECT(s), &eepro100_ops, s,
1849 "eepro100-mmio", PCI_MEM_SIZE);
1850 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
1851 memory_region_init_io(&s->io_bar, OBJECT(s), &eepro100_ops, s,
1852 "eepro100-io", PCI_IO_SIZE);
1853 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1854 /* FIXME: flash aliases to mmio?! */
1855 memory_region_init_io(&s->flash_bar, OBJECT(s), &eepro100_ops, s,
1856 "eepro100-flash", PCI_FLASH_SIZE);
1857 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
1858
1859 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1860 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1861
1862 nic_reset(s);
1863
1864 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1865 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
1866
1867 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1868 TRACE(OTHER, logout("%s\n", qemu_get_queue(s->nic)->info_str));
1869
1870 qemu_register_reset(nic_reset, s);
1871
1872 s->vmstate = g_memdup(&vmstate_eepro100, sizeof(vmstate_eepro100));
1873 s->vmstate->name = qemu_get_queue(s->nic)->model;
1874 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1875 }
1876
1877 static void eepro100_instance_init(Object *obj)
1878 {
1879 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, PCI_DEVICE(obj));
1880 device_add_bootindex_property(obj, &s->conf.bootindex,
1881 "bootindex", "/ethernet-phy@0",
1882 DEVICE(s), NULL);
1883 }
1884
1885 static E100PCIDeviceInfo e100_devices[] = {
1886 {
1887 .name = "i82550",
1888 .desc = "Intel i82550 Ethernet",
1889 .device = i82550,
1890 /* TODO: check device id. */
1891 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1892 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1893 .revision = 0x0e,
1894 /* TODO: check size of statistical counters. */
1895 .stats_size = 80,
1896 /* TODO: check extended tcb support. */
1897 .has_extended_tcb_support = true,
1898 .power_management = true,
1899 },{
1900 .name = "i82551",
1901 .desc = "Intel i82551 Ethernet",
1902 .device = i82551,
1903 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1904 /* Revision ID: 0x0f, 0x10. */
1905 .revision = 0x0f,
1906 /* TODO: check size of statistical counters. */
1907 .stats_size = 80,
1908 .has_extended_tcb_support = true,
1909 .power_management = true,
1910 },{
1911 .name = "i82557a",
1912 .desc = "Intel i82557A Ethernet",
1913 .device = i82557A,
1914 .device_id = PCI_DEVICE_ID_INTEL_82557,
1915 .revision = 0x01,
1916 .power_management = false,
1917 },{
1918 .name = "i82557b",
1919 .desc = "Intel i82557B Ethernet",
1920 .device = i82557B,
1921 .device_id = PCI_DEVICE_ID_INTEL_82557,
1922 .revision = 0x02,
1923 .power_management = false,
1924 },{
1925 .name = "i82557c",
1926 .desc = "Intel i82557C Ethernet",
1927 .device = i82557C,
1928 .device_id = PCI_DEVICE_ID_INTEL_82557,
1929 .revision = 0x03,
1930 .power_management = false,
1931 },{
1932 .name = "i82558a",
1933 .desc = "Intel i82558A Ethernet",
1934 .device = i82558A,
1935 .device_id = PCI_DEVICE_ID_INTEL_82557,
1936 .revision = 0x04,
1937 .stats_size = 76,
1938 .has_extended_tcb_support = true,
1939 .power_management = true,
1940 },{
1941 .name = "i82558b",
1942 .desc = "Intel i82558B Ethernet",
1943 .device = i82558B,
1944 .device_id = PCI_DEVICE_ID_INTEL_82557,
1945 .revision = 0x05,
1946 .stats_size = 76,
1947 .has_extended_tcb_support = true,
1948 .power_management = true,
1949 },{
1950 .name = "i82559a",
1951 .desc = "Intel i82559A Ethernet",
1952 .device = i82559A,
1953 .device_id = PCI_DEVICE_ID_INTEL_82557,
1954 .revision = 0x06,
1955 .stats_size = 80,
1956 .has_extended_tcb_support = true,
1957 .power_management = true,
1958 },{
1959 .name = "i82559b",
1960 .desc = "Intel i82559B Ethernet",
1961 .device = i82559B,
1962 .device_id = PCI_DEVICE_ID_INTEL_82557,
1963 .revision = 0x07,
1964 .stats_size = 80,
1965 .has_extended_tcb_support = true,
1966 .power_management = true,
1967 },{
1968 .name = "i82559c",
1969 .desc = "Intel i82559C Ethernet",
1970 .device = i82559C,
1971 .device_id = PCI_DEVICE_ID_INTEL_82557,
1972 #if 0
1973 .revision = 0x08,
1974 #endif
1975 /* TODO: Windows wants revision id 0x0c. */
1976 .revision = 0x0c,
1977 #if EEPROM_SIZE > 0
1978 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
1979 .subsystem_id = 0x0040,
1980 #endif
1981 .stats_size = 80,
1982 .has_extended_tcb_support = true,
1983 .power_management = true,
1984 },{
1985 .name = "i82559er",
1986 .desc = "Intel i82559ER Ethernet",
1987 .device = i82559ER,
1988 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1989 .revision = 0x09,
1990 .stats_size = 80,
1991 .has_extended_tcb_support = true,
1992 .power_management = true,
1993 },{
1994 .name = "i82562",
1995 .desc = "Intel i82562 Ethernet",
1996 .device = i82562,
1997 /* TODO: check device id. */
1998 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1999 /* TODO: wrong revision id. */
2000 .revision = 0x0e,
2001 .stats_size = 80,
2002 .has_extended_tcb_support = true,
2003 .power_management = true,
2004 },{
2005 /* Toshiba Tecra 8200. */
2006 .name = "i82801",
2007 .desc = "Intel i82801 Ethernet",
2008 .device = i82801,
2009 .device_id = 0x2449,
2010 .revision = 0x03,
2011 .stats_size = 80,
2012 .has_extended_tcb_support = true,
2013 .power_management = true,
2014 }
2015 };
2016
2017 static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename)
2018 {
2019 E100PCIDeviceInfo *info = NULL;
2020 int i;
2021
2022 /* This is admittedly awkward but also temporary. QOM allows for
2023 * parameterized typing and for subclassing both of which would suitable
2024 * handle what's going on here. But class_data is already being used as
2025 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2026 * right now. Once we merge the final QOM series, we can come back here and
2027 * do this in a much more elegant fashion.
2028 */
2029 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2030 if (strcmp(e100_devices[i].name, typename) == 0) {
2031 info = &e100_devices[i];
2032 break;
2033 }
2034 }
2035 assert(info != NULL);
2036
2037 return info;
2038 }
2039
2040 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s)
2041 {
2042 return eepro100_get_class_by_name(object_get_typename(OBJECT(s)));
2043 }
2044
2045 static Property e100_properties[] = {
2046 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2047 DEFINE_PROP_END_OF_LIST(),
2048 };
2049
2050 static void eepro100_class_init(ObjectClass *klass, void *data)
2051 {
2052 DeviceClass *dc = DEVICE_CLASS(klass);
2053 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2054 E100PCIDeviceInfo *info;
2055
2056 info = eepro100_get_class_by_name(object_class_get_name(klass));
2057
2058 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2059 dc->props = e100_properties;
2060 dc->desc = info->desc;
2061 k->vendor_id = PCI_VENDOR_ID_INTEL;
2062 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
2063 k->romfile = "pxe-eepro100.rom";
2064 k->realize = e100_nic_realize;
2065 k->exit = pci_nic_uninit;
2066 k->device_id = info->device_id;
2067 k->revision = info->revision;
2068 k->subsystem_vendor_id = info->subsystem_vendor_id;
2069 k->subsystem_id = info->subsystem_id;
2070 }
2071
2072 static void eepro100_register_types(void)
2073 {
2074 size_t i;
2075 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2076 TypeInfo type_info = {};
2077 E100PCIDeviceInfo *info = &e100_devices[i];
2078
2079 type_info.name = info->name;
2080 type_info.parent = TYPE_PCI_DEVICE;
2081 type_info.class_init = eepro100_class_init;
2082 type_info.instance_size = sizeof(EEPRO100State);
2083 type_info.instance_init = eepro100_instance_init;
2084 type_info.interfaces = (InterfaceInfo[]) {
2085 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2086 { },
2087 };
2088
2089 type_register(&type_info);
2090 }
2091 }
2092
2093 type_init(eepro100_register_types)
Eric Blake's pending patches to qemu