2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "hw/arm/arm.h"
20 #include "hw/arm/armv7m_nvic.h"
21 #include "target/arm/cpu.h"
22 #include "exec/exec-all.h"
26 /* IRQ number counting:
28 * the num-irq property counts the number of external IRQ lines
30 * NVICState::num_irq counts the total number of exceptions
31 * (external IRQs, the 15 internal exceptions including reset,
32 * and one for the unused exception number 0).
34 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
36 * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
38 * Iterating through all exceptions should typically be done with
39 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
41 * The external qemu_irq lines are the NVIC's external IRQ lines,
42 * so line 0 is exception 16.
44 * In the terminology of the architecture manual, "interrupts" are
45 * a subcategory of exception referring to the external interrupts
46 * (which are exception numbers NVIC_FIRST_IRQ and upward).
47 * For historical reasons QEMU tends to use "interrupt" and
48 * "exception" more or less interchangeably.
50 #define NVIC_FIRST_IRQ 16
51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
53 /* Effective running priority of the CPU when no exception is active
54 * (higher than the highest possible priority value)
56 #define NVIC_NOEXC_PRIO 0x100
58 static const uint8_t nvic_id
[] = {
59 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
62 static int nvic_pending_prio(NVICState
*s
)
64 /* return the priority of the current pending interrupt,
65 * or NVIC_NOEXC_PRIO if no interrupt is pending
67 return s
->vectpending
? s
->vectors
[s
->vectpending
].prio
: NVIC_NOEXC_PRIO
;
70 /* Return the value of the ISCR RETTOBASE bit:
71 * 1 if there is exactly one active exception
72 * 0 if there is more than one active exception
73 * UNKNOWN if there are no active exceptions (we choose 1,
74 * which matches the choice Cortex-M3 is documented as making).
76 * NB: some versions of the documentation talk about this
77 * counting "active exceptions other than the one shown by IPSR";
78 * this is only different in the obscure corner case where guest
79 * code has manually deactivated an exception and is about
80 * to fail an exception-return integrity check. The definition
81 * above is the one from the v8M ARM ARM and is also in line
82 * with the behaviour documented for the Cortex-M3.
84 static bool nvic_rettobase(NVICState
*s
)
88 for (irq
= ARMV7M_EXCP_RESET
; irq
< s
->num_irq
; irq
++) {
89 if (s
->vectors
[irq
].active
) {
100 /* Return the value of the ISCR ISRPENDING bit:
101 * 1 if an external interrupt is pending
102 * 0 if no external interrupt is pending
104 static bool nvic_isrpending(NVICState
*s
)
108 /* We can shortcut if the highest priority pending interrupt
109 * happens to be external or if there is nothing pending.
111 if (s
->vectpending
> NVIC_FIRST_IRQ
) {
114 if (s
->vectpending
== 0) {
118 for (irq
= NVIC_FIRST_IRQ
; irq
< s
->num_irq
; irq
++) {
119 if (s
->vectors
[irq
].pending
) {
126 /* Return a mask word which clears the subpriority bits from
127 * a priority value for an M-profile exception, leaving only
128 * the group priority.
130 static inline uint32_t nvic_gprio_mask(NVICState
*s
)
132 return ~0U << (s
->prigroup
+ 1);
135 /* Recompute vectpending and exception_prio */
136 static void nvic_recompute_state(NVICState
*s
)
139 int pend_prio
= NVIC_NOEXC_PRIO
;
140 int active_prio
= NVIC_NOEXC_PRIO
;
143 for (i
= 1; i
< s
->num_irq
; i
++) {
144 VecInfo
*vec
= &s
->vectors
[i
];
146 if (vec
->enabled
&& vec
->pending
&& vec
->prio
< pend_prio
) {
147 pend_prio
= vec
->prio
;
150 if (vec
->active
&& vec
->prio
< active_prio
) {
151 active_prio
= vec
->prio
;
155 s
->vectpending
= pend_irq
;
156 s
->exception_prio
= active_prio
& nvic_gprio_mask(s
);
158 trace_nvic_recompute_state(s
->vectpending
, s
->exception_prio
);
161 /* Return the current execution priority of the CPU
162 * (equivalent to the pseudocode ExecutionPriority function).
163 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
165 static inline int nvic_exec_prio(NVICState
*s
)
167 CPUARMState
*env
= &s
->cpu
->env
;
170 if (env
->daif
& PSTATE_F
) { /* FAULTMASK */
172 } else if (env
->daif
& PSTATE_I
) { /* PRIMASK */
174 } else if (env
->v7m
.basepri
> 0) {
175 running
= env
->v7m
.basepri
& nvic_gprio_mask(s
);
177 running
= NVIC_NOEXC_PRIO
; /* lower than any possible priority */
179 /* consider priority of active handler */
180 return MIN(running
, s
->exception_prio
);
183 bool armv7m_nvic_can_take_pending_exception(void *opaque
)
185 NVICState
*s
= opaque
;
187 return nvic_exec_prio(s
) > nvic_pending_prio(s
);
190 /* caller must call nvic_irq_update() after this */
191 static void set_prio(NVICState
*s
, unsigned irq
, uint8_t prio
)
193 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
194 assert(irq
< s
->num_irq
);
196 s
->vectors
[irq
].prio
= prio
;
198 trace_nvic_set_prio(irq
, prio
);
201 /* Recompute state and assert irq line accordingly.
202 * Must be called after changes to:
203 * vec->active, vec->enabled, vec->pending or vec->prio for any vector
206 static void nvic_irq_update(NVICState
*s
)
211 nvic_recompute_state(s
);
212 pend_prio
= nvic_pending_prio(s
);
214 /* Raise NVIC output if this IRQ would be taken, except that we
215 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
216 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
217 * to those CPU registers don't cause us to recalculate the NVIC
220 lvl
= (pend_prio
< s
->exception_prio
);
221 trace_nvic_irq_update(s
->vectpending
, pend_prio
, s
->exception_prio
, lvl
);
222 qemu_set_irq(s
->excpout
, lvl
);
225 static void armv7m_nvic_clear_pending(void *opaque
, int irq
)
227 NVICState
*s
= (NVICState
*)opaque
;
230 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
232 vec
= &s
->vectors
[irq
];
233 trace_nvic_clear_pending(irq
, vec
->enabled
, vec
->prio
);
240 void armv7m_nvic_set_pending(void *opaque
, int irq
)
242 NVICState
*s
= (NVICState
*)opaque
;
245 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
247 vec
= &s
->vectors
[irq
];
248 trace_nvic_set_pending(irq
, vec
->enabled
, vec
->prio
);
251 if (irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
) {
252 /* If a synchronous exception is pending then it may be
253 * escalated to HardFault if:
254 * * it is equal or lower priority to current execution
256 * (ie we need to take it immediately but we can't do so).
257 * Asynchronous exceptions (and interrupts) simply remain pending.
259 * For QEMU, we don't have any imprecise (asynchronous) faults,
260 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
262 * Debug exceptions are awkward because only Debug exceptions
263 * resulting from the BKPT instruction should be escalated,
264 * but we don't currently implement any Debug exceptions other
265 * than those that result from BKPT, so we treat all debug exceptions
266 * as needing escalation.
268 * This all means we can identify whether to escalate based only on
269 * the exception number and don't (yet) need the caller to explicitly
270 * tell us whether this exception is synchronous or not.
272 int running
= nvic_exec_prio(s
);
273 bool escalate
= false;
275 if (vec
->prio
>= running
) {
276 trace_nvic_escalate_prio(irq
, vec
->prio
, running
);
278 } else if (!vec
->enabled
) {
279 trace_nvic_escalate_disabled(irq
);
285 /* We want to escalate to HardFault but we can't take a
286 * synchronous HardFault at this point either. This is a
287 * Lockup condition due to a guest bug. We don't model
288 * Lockup, so report via cpu_abort() instead.
290 cpu_abort(&s
->cpu
->parent_obj
,
291 "Lockup: can't escalate %d to HardFault "
292 "(current priority %d)\n", irq
, running
);
295 /* We can do the escalation, so we take HardFault instead */
296 irq
= ARMV7M_EXCP_HARD
;
297 vec
= &s
->vectors
[irq
];
298 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
308 /* Make pending IRQ active. */
309 void armv7m_nvic_acknowledge_irq(void *opaque
)
311 NVICState
*s
= (NVICState
*)opaque
;
312 CPUARMState
*env
= &s
->cpu
->env
;
313 const int pending
= s
->vectpending
;
314 const int running
= nvic_exec_prio(s
);
318 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
320 vec
= &s
->vectors
[pending
];
322 assert(vec
->enabled
);
323 assert(vec
->pending
);
325 pendgroupprio
= vec
->prio
& nvic_gprio_mask(s
);
326 assert(pendgroupprio
< running
);
328 trace_nvic_acknowledge_irq(pending
, vec
->prio
);
333 env
->v7m
.exception
= s
->vectpending
;
338 int armv7m_nvic_complete_irq(void *opaque
, int irq
)
340 NVICState
*s
= (NVICState
*)opaque
;
344 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
346 vec
= &s
->vectors
[irq
];
348 trace_nvic_complete_irq(irq
);
351 /* Tell the caller this was an illegal exception return */
355 ret
= nvic_rettobase(s
);
359 /* Re-pend the exception if it's still held high; only
360 * happens for extenal IRQs
362 assert(irq
>= NVIC_FIRST_IRQ
);
371 /* callback when external interrupt line is changed */
372 static void set_irq_level(void *opaque
, int n
, int level
)
374 NVICState
*s
= opaque
;
379 assert(n
>= NVIC_FIRST_IRQ
&& n
< s
->num_irq
);
381 trace_nvic_set_irq_level(n
, level
);
383 /* The pending status of an external interrupt is
384 * latched on rising edge and exception handler return.
386 * Pulsing the IRQ will always run the handler
387 * once, and the handler will re-run until the
388 * level is low when the handler completes.
390 vec
= &s
->vectors
[n
];
391 if (level
!= vec
->level
) {
394 armv7m_nvic_set_pending(s
, n
);
399 static uint32_t nvic_readl(NVICState
*s
, uint32_t offset
)
401 ARMCPU
*cpu
= s
->cpu
;
405 case 4: /* Interrupt Control Type. */
406 return ((s
->num_irq
- NVIC_FIRST_IRQ
) / 32) - 1;
407 case 0xd00: /* CPUID Base. */
409 case 0xd04: /* Interrupt Control State. */
411 val
= cpu
->env
.v7m
.exception
;
413 val
|= (s
->vectpending
& 0xff) << 12;
414 /* ISRPENDING - set if any external IRQ is pending */
415 if (nvic_isrpending(s
)) {
418 /* RETTOBASE - set if only one handler is active */
419 if (nvic_rettobase(s
)) {
423 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
427 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
431 if (s
->vectors
[ARMV7M_EXCP_NMI
].pending
) {
434 /* ISRPREEMPT not implemented */
436 case 0xd08: /* Vector Table Offset. */
437 return cpu
->env
.v7m
.vecbase
;
438 case 0xd0c: /* Application Interrupt/Reset Control. */
439 return 0xfa050000 | (s
->prigroup
<< 8);
440 case 0xd10: /* System Control. */
441 /* TODO: Implement SLEEPONEXIT. */
443 case 0xd14: /* Configuration Control. */
444 return cpu
->env
.v7m
.ccr
;
445 case 0xd24: /* System Handler Status. */
447 if (s
->vectors
[ARMV7M_EXCP_MEM
].active
) {
450 if (s
->vectors
[ARMV7M_EXCP_BUS
].active
) {
453 if (s
->vectors
[ARMV7M_EXCP_USAGE
].active
) {
456 if (s
->vectors
[ARMV7M_EXCP_SVC
].active
) {
459 if (s
->vectors
[ARMV7M_EXCP_DEBUG
].active
) {
462 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].active
) {
465 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
468 if (s
->vectors
[ARMV7M_EXCP_USAGE
].pending
) {
471 if (s
->vectors
[ARMV7M_EXCP_MEM
].pending
) {
474 if (s
->vectors
[ARMV7M_EXCP_BUS
].pending
) {
477 if (s
->vectors
[ARMV7M_EXCP_SVC
].pending
) {
480 if (s
->vectors
[ARMV7M_EXCP_MEM
].enabled
) {
483 if (s
->vectors
[ARMV7M_EXCP_BUS
].enabled
) {
486 if (s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
490 case 0xd28: /* Configurable Fault Status. */
491 return cpu
->env
.v7m
.cfsr
;
492 case 0xd2c: /* Hard Fault Status. */
493 return cpu
->env
.v7m
.hfsr
;
494 case 0xd30: /* Debug Fault Status. */
495 return cpu
->env
.v7m
.dfsr
;
496 case 0xd34: /* MMFAR MemManage Fault Address */
497 return cpu
->env
.v7m
.mmfar
;
498 case 0xd38: /* Bus Fault Address. */
499 return cpu
->env
.v7m
.bfar
;
500 case 0xd3c: /* Aux Fault Status. */
501 /* TODO: Implement fault status registers. */
502 qemu_log_mask(LOG_UNIMP
,
503 "Aux Fault status registers unimplemented\n");
505 case 0xd40: /* PFR0. */
507 case 0xd44: /* PRF1. */
509 case 0xd48: /* DFR0. */
511 case 0xd4c: /* AFR0. */
513 case 0xd50: /* MMFR0. */
515 case 0xd54: /* MMFR1. */
517 case 0xd58: /* MMFR2. */
519 case 0xd5c: /* MMFR3. */
521 case 0xd60: /* ISAR0. */
523 case 0xd64: /* ISAR1. */
525 case 0xd68: /* ISAR2. */
527 case 0xd6c: /* ISAR3. */
529 case 0xd70: /* ISAR4. */
531 /* TODO: Implement debug registers. */
532 case 0xd90: /* MPU_TYPE */
533 /* Unified MPU; if the MPU is not present this value is zero */
534 return cpu
->pmsav7_dregion
<< 8;
536 case 0xd94: /* MPU_CTRL */
537 return cpu
->env
.v7m
.mpu_ctrl
;
538 case 0xd98: /* MPU_RNR */
539 return cpu
->env
.pmsav7
.rnr
;
540 case 0xd9c: /* MPU_RBAR */
541 case 0xda4: /* MPU_RBAR_A1 */
542 case 0xdac: /* MPU_RBAR_A2 */
543 case 0xdb4: /* MPU_RBAR_A3 */
545 int region
= cpu
->env
.pmsav7
.rnr
;
547 if (region
>= cpu
->pmsav7_dregion
) {
550 return (cpu
->env
.pmsav7
.drbar
[region
] & 0x1f) | (region
& 0xf);
552 case 0xda0: /* MPU_RASR */
553 case 0xda8: /* MPU_RASR_A1 */
554 case 0xdb0: /* MPU_RASR_A2 */
555 case 0xdb8: /* MPU_RASR_A3 */
557 int region
= cpu
->env
.pmsav7
.rnr
;
559 if (region
>= cpu
->pmsav7_dregion
) {
562 return ((cpu
->env
.pmsav7
.dracr
[region
] & 0xffff) << 16) |
563 (cpu
->env
.pmsav7
.drsr
[region
] & 0xffff);
566 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
571 static void nvic_writel(NVICState
*s
, uint32_t offset
, uint32_t value
)
573 ARMCPU
*cpu
= s
->cpu
;
576 case 0xd04: /* Interrupt Control State. */
577 if (value
& (1 << 31)) {
578 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
);
580 if (value
& (1 << 28)) {
581 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
);
582 } else if (value
& (1 << 27)) {
583 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_PENDSV
);
585 if (value
& (1 << 26)) {
586 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
);
587 } else if (value
& (1 << 25)) {
588 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_SYSTICK
);
591 case 0xd08: /* Vector Table Offset. */
592 cpu
->env
.v7m
.vecbase
= value
& 0xffffff80;
594 case 0xd0c: /* Application Interrupt/Reset Control. */
595 if ((value
>> 16) == 0x05fa) {
597 qemu_irq_pulse(s
->sysresetreq
);
600 qemu_log_mask(LOG_GUEST_ERROR
,
601 "Setting VECTCLRACTIVE when not in DEBUG mode "
602 "is UNPREDICTABLE\n");
605 qemu_log_mask(LOG_GUEST_ERROR
,
606 "Setting VECTRESET when not in DEBUG mode "
607 "is UNPREDICTABLE\n");
609 s
->prigroup
= extract32(value
, 8, 3);
613 case 0xd10: /* System Control. */
614 /* TODO: Implement control registers. */
615 qemu_log_mask(LOG_UNIMP
, "NVIC: SCR unimplemented\n");
617 case 0xd14: /* Configuration Control. */
618 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
619 value
&= (R_V7M_CCR_STKALIGN_MASK
|
620 R_V7M_CCR_BFHFNMIGN_MASK
|
621 R_V7M_CCR_DIV_0_TRP_MASK
|
622 R_V7M_CCR_UNALIGN_TRP_MASK
|
623 R_V7M_CCR_USERSETMPEND_MASK
|
624 R_V7M_CCR_NONBASETHRDENA_MASK
);
626 cpu
->env
.v7m
.ccr
= value
;
628 case 0xd24: /* System Handler Control. */
629 s
->vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
630 s
->vectors
[ARMV7M_EXCP_BUS
].active
= (value
& (1 << 1)) != 0;
631 s
->vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
632 s
->vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
633 s
->vectors
[ARMV7M_EXCP_DEBUG
].active
= (value
& (1 << 8)) != 0;
634 s
->vectors
[ARMV7M_EXCP_PENDSV
].active
= (value
& (1 << 10)) != 0;
635 s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
= (value
& (1 << 11)) != 0;
636 s
->vectors
[ARMV7M_EXCP_USAGE
].pending
= (value
& (1 << 12)) != 0;
637 s
->vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
638 s
->vectors
[ARMV7M_EXCP_BUS
].pending
= (value
& (1 << 14)) != 0;
639 s
->vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
640 s
->vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
641 s
->vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
642 s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
645 case 0xd28: /* Configurable Fault Status. */
646 cpu
->env
.v7m
.cfsr
&= ~value
; /* W1C */
648 case 0xd2c: /* Hard Fault Status. */
649 cpu
->env
.v7m
.hfsr
&= ~value
; /* W1C */
651 case 0xd30: /* Debug Fault Status. */
652 cpu
->env
.v7m
.dfsr
&= ~value
; /* W1C */
654 case 0xd34: /* Mem Manage Address. */
655 cpu
->env
.v7m
.mmfar
= value
;
657 case 0xd38: /* Bus Fault Address. */
658 cpu
->env
.v7m
.bfar
= value
;
660 case 0xd3c: /* Aux Fault Status. */
661 qemu_log_mask(LOG_UNIMP
,
662 "NVIC: Aux fault status registers unimplemented\n");
664 case 0xd90: /* MPU_TYPE */
666 case 0xd94: /* MPU_CTRL */
668 (R_V7M_MPU_CTRL_HFNMIENA_MASK
| R_V7M_MPU_CTRL_ENABLE_MASK
))
669 == R_V7M_MPU_CTRL_HFNMIENA_MASK
) {
670 qemu_log_mask(LOG_GUEST_ERROR
, "MPU_CTRL: HFNMIENA and !ENABLE is "
673 cpu
->env
.v7m
.mpu_ctrl
= value
& (R_V7M_MPU_CTRL_ENABLE_MASK
|
674 R_V7M_MPU_CTRL_HFNMIENA_MASK
|
675 R_V7M_MPU_CTRL_PRIVDEFENA_MASK
);
678 case 0xd98: /* MPU_RNR */
679 if (value
>= cpu
->pmsav7_dregion
) {
680 qemu_log_mask(LOG_GUEST_ERROR
, "MPU region out of range %"
681 PRIu32
"/%" PRIu32
"\n",
682 value
, cpu
->pmsav7_dregion
);
684 cpu
->env
.pmsav7
.rnr
= value
;
687 case 0xd9c: /* MPU_RBAR */
688 case 0xda4: /* MPU_RBAR_A1 */
689 case 0xdac: /* MPU_RBAR_A2 */
690 case 0xdb4: /* MPU_RBAR_A3 */
694 if (value
& (1 << 4)) {
695 /* VALID bit means use the region number specified in this
696 * value and also update MPU_RNR.REGION with that value.
698 region
= extract32(value
, 0, 4);
699 if (region
>= cpu
->pmsav7_dregion
) {
700 qemu_log_mask(LOG_GUEST_ERROR
,
701 "MPU region out of range %u/%" PRIu32
"\n",
702 region
, cpu
->pmsav7_dregion
);
705 cpu
->env
.pmsav7
.rnr
= region
;
707 region
= cpu
->env
.pmsav7
.rnr
;
710 if (region
>= cpu
->pmsav7_dregion
) {
714 cpu
->env
.pmsav7
.drbar
[region
] = value
& ~0x1f;
718 case 0xda0: /* MPU_RASR */
719 case 0xda8: /* MPU_RASR_A1 */
720 case 0xdb0: /* MPU_RASR_A2 */
721 case 0xdb8: /* MPU_RASR_A3 */
723 int region
= cpu
->env
.pmsav7
.rnr
;
725 if (region
>= cpu
->pmsav7_dregion
) {
729 cpu
->env
.pmsav7
.drsr
[region
] = value
& 0xff3f;
730 cpu
->env
.pmsav7
.dracr
[region
] = (value
>> 16) & 0x173f;
734 case 0xf00: /* Software Triggered Interrupt Register */
736 /* user mode can only write to STIR if CCR.USERSETMPEND permits it */
737 int excnum
= (value
& 0x1ff) + NVIC_FIRST_IRQ
;
738 if (excnum
< s
->num_irq
&&
739 (arm_current_el(&cpu
->env
) ||
740 (cpu
->env
.v7m
.ccr
& R_V7M_CCR_USERSETMPEND_MASK
))) {
741 armv7m_nvic_set_pending(s
, excnum
);
746 qemu_log_mask(LOG_GUEST_ERROR
,
747 "NVIC: Bad write offset 0x%x\n", offset
);
751 static uint64_t nvic_sysreg_read(void *opaque
, hwaddr addr
,
754 NVICState
*s
= (NVICState
*)opaque
;
755 uint32_t offset
= addr
;
756 unsigned i
, startvec
, end
;
760 /* reads of set and clear both return the status */
761 case 0x100 ... 0x13f: /* NVIC Set enable */
764 case 0x180 ... 0x1bf: /* NVIC Clear enable */
766 startvec
= offset
- 0x180 + NVIC_FIRST_IRQ
; /* vector # */
768 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
769 if (s
->vectors
[startvec
+ i
].enabled
) {
774 case 0x200 ... 0x23f: /* NVIC Set pend */
777 case 0x280 ... 0x2bf: /* NVIC Clear pend */
779 startvec
= offset
- 0x280 + NVIC_FIRST_IRQ
; /* vector # */
780 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
781 if (s
->vectors
[startvec
+ i
].pending
) {
786 case 0x300 ... 0x33f: /* NVIC Active */
788 startvec
= offset
- 0x300 + NVIC_FIRST_IRQ
; /* vector # */
790 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
791 if (s
->vectors
[startvec
+ i
].active
) {
796 case 0x400 ... 0x5ef: /* NVIC Priority */
798 startvec
= offset
- 0x400 + NVIC_FIRST_IRQ
; /* vector # */
800 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
801 val
|= s
->vectors
[startvec
+ i
].prio
<< (8 * i
);
804 case 0xd18 ... 0xd23: /* System Handler Priority. */
806 for (i
= 0; i
< size
; i
++) {
807 val
|= s
->vectors
[(offset
- 0xd14) + i
].prio
<< (i
* 8);
810 case 0xfe0 ... 0xfff: /* ID. */
814 val
= nvic_id
[(offset
- 0xfe0) >> 2];
819 val
= nvic_readl(s
, offset
);
821 qemu_log_mask(LOG_GUEST_ERROR
,
822 "NVIC: Bad read of size %d at offset 0x%x\n",
828 trace_nvic_sysreg_read(addr
, val
, size
);
832 static void nvic_sysreg_write(void *opaque
, hwaddr addr
,
833 uint64_t value
, unsigned size
)
835 NVICState
*s
= (NVICState
*)opaque
;
836 uint32_t offset
= addr
;
837 unsigned i
, startvec
, end
;
840 trace_nvic_sysreg_write(addr
, value
, size
);
843 case 0x100 ... 0x13f: /* NVIC Set enable */
847 case 0x180 ... 0x1bf: /* NVIC Clear enable */
848 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
;
850 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
851 if (value
& (1 << i
)) {
852 s
->vectors
[startvec
+ i
].enabled
= setval
;
857 case 0x200 ... 0x23f: /* NVIC Set pend */
858 /* the special logic in armv7m_nvic_set_pending()
859 * is not needed since IRQs are never escalated
864 case 0x280 ... 0x2bf: /* NVIC Clear pend */
865 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
867 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
868 if (value
& (1 << i
)) {
869 s
->vectors
[startvec
+ i
].pending
= setval
;
874 case 0x300 ... 0x33f: /* NVIC Active */
876 case 0x400 ... 0x5ef: /* NVIC Priority */
877 startvec
= 8 * (offset
- 0x400) + NVIC_FIRST_IRQ
; /* vector # */
879 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
880 set_prio(s
, startvec
+ i
, (value
>> (i
* 8)) & 0xff);
884 case 0xd18 ... 0xd23: /* System Handler Priority. */
885 for (i
= 0; i
< size
; i
++) {
886 unsigned hdlidx
= (offset
- 0xd14) + i
;
887 set_prio(s
, hdlidx
, (value
>> (i
* 8)) & 0xff);
893 nvic_writel(s
, offset
, value
);
896 qemu_log_mask(LOG_GUEST_ERROR
,
897 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
900 static const MemoryRegionOps nvic_sysreg_ops
= {
901 .read
= nvic_sysreg_read
,
902 .write
= nvic_sysreg_write
,
903 .endianness
= DEVICE_NATIVE_ENDIAN
,
906 static int nvic_post_load(void *opaque
, int version_id
)
908 NVICState
*s
= opaque
;
911 /* Check for out of range priority settings */
912 if (s
->vectors
[ARMV7M_EXCP_RESET
].prio
!= -3 ||
913 s
->vectors
[ARMV7M_EXCP_NMI
].prio
!= -2 ||
914 s
->vectors
[ARMV7M_EXCP_HARD
].prio
!= -1) {
917 for (i
= ARMV7M_EXCP_MEM
; i
< s
->num_irq
; i
++) {
918 if (s
->vectors
[i
].prio
& ~0xff) {
923 nvic_recompute_state(s
);
928 static const VMStateDescription vmstate_VecInfo
= {
929 .name
= "armv7m_nvic_info",
931 .minimum_version_id
= 1,
932 .fields
= (VMStateField
[]) {
933 VMSTATE_INT16(prio
, VecInfo
),
934 VMSTATE_UINT8(enabled
, VecInfo
),
935 VMSTATE_UINT8(pending
, VecInfo
),
936 VMSTATE_UINT8(active
, VecInfo
),
937 VMSTATE_UINT8(level
, VecInfo
),
938 VMSTATE_END_OF_LIST()
942 static const VMStateDescription vmstate_nvic
= {
943 .name
= "armv7m_nvic",
945 .minimum_version_id
= 4,
946 .post_load
= &nvic_post_load
,
947 .fields
= (VMStateField
[]) {
948 VMSTATE_STRUCT_ARRAY(vectors
, NVICState
, NVIC_MAX_VECTORS
, 1,
949 vmstate_VecInfo
, VecInfo
),
950 VMSTATE_UINT32(prigroup
, NVICState
),
951 VMSTATE_END_OF_LIST()
955 static Property props_nvic
[] = {
956 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
957 DEFINE_PROP_UINT32("num-irq", NVICState
, num_irq
, 64),
958 DEFINE_PROP_END_OF_LIST()
961 static void armv7m_nvic_reset(DeviceState
*dev
)
963 NVICState
*s
= NVIC(dev
);
965 s
->vectors
[ARMV7M_EXCP_NMI
].enabled
= 1;
966 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
967 /* MEM, BUS, and USAGE are enabled through
968 * the System Handler Control register
970 s
->vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
971 s
->vectors
[ARMV7M_EXCP_DEBUG
].enabled
= 1;
972 s
->vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
973 s
->vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
975 s
->vectors
[ARMV7M_EXCP_RESET
].prio
= -3;
976 s
->vectors
[ARMV7M_EXCP_NMI
].prio
= -2;
977 s
->vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
979 /* Strictly speaking the reset handler should be enabled.
980 * However, we don't simulate soft resets through the NVIC,
981 * and the reset vector should never be pended.
982 * So we leave it disabled to catch logic errors.
985 s
->exception_prio
= NVIC_NOEXC_PRIO
;
989 static void nvic_systick_trigger(void *opaque
, int n
, int level
)
991 NVICState
*s
= opaque
;
994 /* SysTick just asked us to pend its exception.
995 * (This is different from an external interrupt line's
998 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
);
1002 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
1004 NVICState
*s
= NVIC(dev
);
1005 SysBusDevice
*systick_sbd
;
1008 s
->cpu
= ARM_CPU(qemu_get_cpu(0));
1011 if (s
->num_irq
> NVIC_MAX_IRQ
) {
1012 error_setg(errp
, "num-irq %d exceeds NVIC maximum", s
->num_irq
);
1016 qdev_init_gpio_in(dev
, set_irq_level
, s
->num_irq
);
1018 /* include space for internal exception vectors */
1019 s
->num_irq
+= NVIC_FIRST_IRQ
;
1021 object_property_set_bool(OBJECT(&s
->systick
), true, "realized", &err
);
1023 error_propagate(errp
, err
);
1026 systick_sbd
= SYS_BUS_DEVICE(&s
->systick
);
1027 sysbus_connect_irq(systick_sbd
, 0,
1028 qdev_get_gpio_in_named(dev
, "systick-trigger", 0));
1030 /* The NVIC and System Control Space (SCS) starts at 0xe000e000
1031 * and looks like this:
1033 * 0x010 - 0xff - systick
1034 * 0x100..0x7ec - NVIC
1035 * 0x7f0..0xcff - Reserved
1036 * 0xd00..0xd3c - SCS registers
1037 * 0xd40..0xeff - Reserved or Not implemented
1040 * At the moment there is only one thing in the container region,
1041 * but we leave it in place to allow us to pull systick out into
1042 * its own device object later.
1044 memory_region_init(&s
->container
, OBJECT(s
), "nvic", 0x1000);
1045 /* The system register region goes at the bottom of the priority
1046 * stack as it covers the whole page.
1048 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
1049 "nvic_sysregs", 0x1000);
1050 memory_region_add_subregion(&s
->container
, 0, &s
->sysregmem
);
1051 memory_region_add_subregion_overlap(&s
->container
, 0x10,
1052 sysbus_mmio_get_region(systick_sbd
, 0),
1055 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->container
);
1058 static void armv7m_nvic_instance_init(Object
*obj
)
1060 /* We have a different default value for the num-irq property
1061 * than our superclass. This function runs after qdev init
1062 * has set the defaults from the Property array and before
1063 * any user-specified property setting, so just modify the
1064 * value in the GICState struct.
1066 DeviceState
*dev
= DEVICE(obj
);
1067 NVICState
*nvic
= NVIC(obj
);
1068 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1070 object_initialize(&nvic
->systick
, sizeof(nvic
->systick
), TYPE_SYSTICK
);
1071 qdev_set_parent_bus(DEVICE(&nvic
->systick
), sysbus_get_default());
1073 sysbus_init_irq(sbd
, &nvic
->excpout
);
1074 qdev_init_gpio_out_named(dev
, &nvic
->sysresetreq
, "SYSRESETREQ", 1);
1075 qdev_init_gpio_in_named(dev
, nvic_systick_trigger
, "systick-trigger", 1);
1078 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
1080 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1082 dc
->vmsd
= &vmstate_nvic
;
1083 dc
->props
= props_nvic
;
1084 dc
->reset
= armv7m_nvic_reset
;
1085 dc
->realize
= armv7m_nvic_realize
;
1088 static const TypeInfo armv7m_nvic_info
= {
1090 .parent
= TYPE_SYS_BUS_DEVICE
,
1091 .instance_init
= armv7m_nvic_instance_init
,
1092 .instance_size
= sizeof(NVICState
),
1093 .class_init
= armv7m_nvic_class_init
,
1094 .class_size
= sizeof(SysBusDeviceClass
),
1097 static void armv7m_nvic_register_types(void)
1099 type_register_static(&armv7m_nvic_info
);
1102 type_init(armv7m_nvic_register_types
)