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i386/cpu/kvm: look at PMU's CPUID before setting MSRs
[qemu/ericb.git] / target / i386 / kvm.c
blobd23127cf8316dadfe7c76749794b4c0adc660d79
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "exec/ioport.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_xss;
94
95 static uint32_t has_architectural_pmu_version;
96 static uint32_t num_architectural_pmu_gp_counters;
97 static uint32_t num_architectural_pmu_fixed_counters;
98
99 static int has_xsave;
100 static int has_xcrs;
101 static int has_pit_state2;
102
103 static bool has_msr_mcg_ext_ctl;
104
105 static struct kvm_cpuid2 *cpuid_cache;
106
107 int kvm_has_pit_state2(void)
108 {
109 return has_pit_state2;
110 }
111
112 bool kvm_has_smm(void)
113 {
114 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
115 }
116
117 bool kvm_has_adjust_clock_stable(void)
118 {
119 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
120
121 return (ret == KVM_CLOCK_TSC_STABLE);
122 }
123
124 bool kvm_allows_irq0_override(void)
125 {
126 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
127 }
128
129 static bool kvm_x2apic_api_set_flags(uint64_t flags)
130 {
131 KVMState *s = KVM_STATE(current_machine->accelerator);
132
133 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
134 }
135
136 #define MEMORIZE(fn, _result) \
137 ({ \
138 static bool _memorized; \
139 \
140 if (_memorized) { \
141 return _result; \
142 } \
143 _memorized = true; \
144 _result = fn; \
145 })
146
147 static bool has_x2apic_api;
148
149 bool kvm_has_x2apic_api(void)
150 {
151 return has_x2apic_api;
152 }
153
154 bool kvm_enable_x2apic(void)
155 {
156 return MEMORIZE(
157 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
158 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
159 has_x2apic_api);
160 }
161
162 static int kvm_get_tsc(CPUState *cs)
163 {
164 X86CPU *cpu = X86_CPU(cs);
165 CPUX86State *env = &cpu->env;
166 struct {
167 struct kvm_msrs info;
168 struct kvm_msr_entry entries[1];
169 } msr_data;
170 int ret;
171
172 if (env->tsc_valid) {
173 return 0;
174 }
175
176 msr_data.info.nmsrs = 1;
177 msr_data.entries[0].index = MSR_IA32_TSC;
178 env->tsc_valid = !runstate_is_running();
179
180 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
181 if (ret < 0) {
182 return ret;
183 }
184
185 assert(ret == 1);
186 env->tsc = msr_data.entries[0].data;
187 return 0;
188 }
189
190 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
191 {
192 kvm_get_tsc(cpu);
193 }
194
195 void kvm_synchronize_all_tsc(void)
196 {
197 CPUState *cpu;
198
199 if (kvm_enabled()) {
200 CPU_FOREACH(cpu) {
201 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
202 }
203 }
204 }
205
206 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
207 {
208 struct kvm_cpuid2 *cpuid;
209 int r, size;
210
211 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
212 cpuid = g_malloc0(size);
213 cpuid->nent = max;
214 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
215 if (r == 0 && cpuid->nent >= max) {
216 r = -E2BIG;
217 }
218 if (r < 0) {
219 if (r == -E2BIG) {
220 g_free(cpuid);
221 return NULL;
222 } else {
223 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
224 strerror(-r));
225 exit(1);
226 }
227 }
228 return cpuid;
229 }
230
231 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
232 * for all entries.
233 */
234 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
235 {
236 struct kvm_cpuid2 *cpuid;
237 int max = 1;
238
239 if (cpuid_cache != NULL) {
240 return cpuid_cache;
241 }
242 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
243 max *= 2;
244 }
245 cpuid_cache = cpuid;
246 return cpuid;
247 }
248
249 static const struct kvm_para_features {
250 int cap;
251 int feature;
252 } para_features[] = {
253 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
254 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
255 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
256 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
257 };
258
259 static int get_para_features(KVMState *s)
260 {
261 int i, features = 0;
262
263 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
264 if (kvm_check_extension(s, para_features[i].cap)) {
265 features |= (1 << para_features[i].feature);
266 }
267 }
268
269 return features;
270 }
271
272 static bool host_tsx_blacklisted(void)
273 {
274 int family, model, stepping;\
275 char vendor[CPUID_VENDOR_SZ + 1];
276
277 host_vendor_fms(vendor, &family, &model, &stepping);
278
279 /* Check if we are running on a Haswell host known to have broken TSX */
280 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
281 (family == 6) &&
282 ((model == 63 && stepping < 4) ||
283 model == 60 || model == 69 || model == 70);
284 }
285
286 /* Returns the value for a specific register on the cpuid entry
287 */
288 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
289 {
290 uint32_t ret = 0;
291 switch (reg) {
292 case R_EAX:
293 ret = entry->eax;
294 break;
295 case R_EBX:
296 ret = entry->ebx;
297 break;
298 case R_ECX:
299 ret = entry->ecx;
300 break;
301 case R_EDX:
302 ret = entry->edx;
303 break;
304 }
305 return ret;
306 }
307
308 /* Find matching entry for function/index on kvm_cpuid2 struct
309 */
310 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
311 uint32_t function,
312 uint32_t index)
313 {
314 int i;
315 for (i = 0; i < cpuid->nent; ++i) {
316 if (cpuid->entries[i].function == function &&
317 cpuid->entries[i].index == index) {
318 return &cpuid->entries[i];
319 }
320 }
321 /* not found: */
322 return NULL;
323 }
324
325 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
326 uint32_t index, int reg)
327 {
328 struct kvm_cpuid2 *cpuid;
329 uint32_t ret = 0;
330 uint32_t cpuid_1_edx;
331 bool found = false;
332
333 cpuid = get_supported_cpuid(s);
334
335 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
336 if (entry) {
337 found = true;
338 ret = cpuid_entry_get_reg(entry, reg);
339 }
340
341 /* Fixups for the data returned by KVM, below */
342
343 if (function == 1 && reg == R_EDX) {
344 /* KVM before 2.6.30 misreports the following features */
345 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
346 } else if (function == 1 && reg == R_ECX) {
347 /* We can set the hypervisor flag, even if KVM does not return it on
348 * GET_SUPPORTED_CPUID
349 */
350 ret |= CPUID_EXT_HYPERVISOR;
351 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
352 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
353 * and the irqchip is in the kernel.
354 */
355 if (kvm_irqchip_in_kernel() &&
356 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
357 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
358 }
359
360 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
361 * without the in-kernel irqchip
362 */
363 if (!kvm_irqchip_in_kernel()) {
364 ret &= ~CPUID_EXT_X2APIC;
365 }
366 } else if (function == 6 && reg == R_EAX) {
367 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
368 } else if (function == 7 && index == 0 && reg == R_EBX) {
369 if (host_tsx_blacklisted()) {
370 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
371 }
372 } else if (function == 0x80000001 && reg == R_EDX) {
373 /* On Intel, kvm returns cpuid according to the Intel spec,
374 * so add missing bits according to the AMD spec:
375 */
376 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
377 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
378 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
379 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
380 * be enabled without the in-kernel irqchip
381 */
382 if (!kvm_irqchip_in_kernel()) {
383 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
384 }
385 }
386
387 /* fallback for older kernels */
388 if ((function == KVM_CPUID_FEATURES) && !found) {
389 ret = get_para_features(s);
390 }
391
392 return ret;
393 }
394
395 typedef struct HWPoisonPage {
396 ram_addr_t ram_addr;
397 QLIST_ENTRY(HWPoisonPage) list;
398 } HWPoisonPage;
399
400 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
401 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
402
403 static void kvm_unpoison_all(void *param)
404 {
405 HWPoisonPage *page, *next_page;
406
407 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
408 QLIST_REMOVE(page, list);
409 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
410 g_free(page);
411 }
412 }
413
414 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
415 {
416 HWPoisonPage *page;
417
418 QLIST_FOREACH(page, &hwpoison_page_list, list) {
419 if (page->ram_addr == ram_addr) {
420 return;
421 }
422 }
423 page = g_new(HWPoisonPage, 1);
424 page->ram_addr = ram_addr;
425 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
426 }
427
428 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
429 int *max_banks)
430 {
431 int r;
432
433 r = kvm_check_extension(s, KVM_CAP_MCE);
434 if (r > 0) {
435 *max_banks = r;
436 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
437 }
438 return -ENOSYS;
439 }
440
441 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
442 {
443 CPUState *cs = CPU(cpu);
444 CPUX86State *env = &cpu->env;
445 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
446 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
447 uint64_t mcg_status = MCG_STATUS_MCIP;
448 int flags = 0;
449
450 if (code == BUS_MCEERR_AR) {
451 status |= MCI_STATUS_AR | 0x134;
452 mcg_status |= MCG_STATUS_EIPV;
453 } else {
454 status |= 0xc0;
455 mcg_status |= MCG_STATUS_RIPV;
456 }
457
458 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
459 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
460 * guest kernel back into env->mcg_ext_ctl.
461 */
462 cpu_synchronize_state(cs);
463 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
464 mcg_status |= MCG_STATUS_LMCE;
465 flags = 0;
466 }
467
468 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
469 (MCM_ADDR_PHYS << 6) | 0xc, flags);
470 }
471
472 static void hardware_memory_error(void)
473 {
474 fprintf(stderr, "Hardware memory error!\n");
475 exit(1);
476 }
477
478 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
479 {
480 X86CPU *cpu = X86_CPU(c);
481 CPUX86State *env = &cpu->env;
482 ram_addr_t ram_addr;
483 hwaddr paddr;
484
485 /* If we get an action required MCE, it has been injected by KVM
486 * while the VM was running. An action optional MCE instead should
487 * be coming from the main thread, which qemu_init_sigbus identifies
488 * as the "early kill" thread.
489 */
490 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
491
492 if ((env->mcg_cap & MCG_SER_P) && addr) {
493 ram_addr = qemu_ram_addr_from_host(addr);
494 if (ram_addr != RAM_ADDR_INVALID &&
495 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
496 kvm_hwpoison_page_add(ram_addr);
497 kvm_mce_inject(cpu, paddr, code);
498 return;
499 }
500
501 fprintf(stderr, "Hardware memory error for memory used by "
502 "QEMU itself instead of guest system!\n");
503 }
504
505 if (code == BUS_MCEERR_AR) {
506 hardware_memory_error();
507 }
508
509 /* Hope we are lucky for AO MCE */
510 }
511
512 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
513 {
514 CPUX86State *env = &cpu->env;
515
516 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
517 unsigned int bank, bank_num = env->mcg_cap & 0xff;
518 struct kvm_x86_mce mce;
519
520 env->exception_injected = -1;
521
522 /*
523 * There must be at least one bank in use if an MCE is pending.
524 * Find it and use its values for the event injection.
525 */
526 for (bank = 0; bank < bank_num; bank++) {
527 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
528 break;
529 }
530 }
531 assert(bank < bank_num);
532
533 mce.bank = bank;
534 mce.status = env->mce_banks[bank * 4 + 1];
535 mce.mcg_status = env->mcg_status;
536 mce.addr = env->mce_banks[bank * 4 + 2];
537 mce.misc = env->mce_banks[bank * 4 + 3];
538
539 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
540 }
541 return 0;
542 }
543
544 static void cpu_update_state(void *opaque, int running, RunState state)
545 {
546 CPUX86State *env = opaque;
547
548 if (running) {
549 env->tsc_valid = false;
550 }
551 }
552
553 unsigned long kvm_arch_vcpu_id(CPUState *cs)
554 {
555 X86CPU *cpu = X86_CPU(cs);
556 return cpu->apic_id;
557 }
558
559 #ifndef KVM_CPUID_SIGNATURE_NEXT
560 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
561 #endif
562
563 static bool hyperv_hypercall_available(X86CPU *cpu)
564 {
565 return cpu->hyperv_vapic ||
566 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
567 }
568
569 static bool hyperv_enabled(X86CPU *cpu)
570 {
571 CPUState *cs = CPU(cpu);
572 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
573 (hyperv_hypercall_available(cpu) ||
574 cpu->hyperv_time ||
575 cpu->hyperv_relaxed_timing ||
576 cpu->hyperv_crash ||
577 cpu->hyperv_reset ||
578 cpu->hyperv_vpindex ||
579 cpu->hyperv_runtime ||
580 cpu->hyperv_synic ||
581 cpu->hyperv_stimer);
582 }
583
584 static int kvm_arch_set_tsc_khz(CPUState *cs)
585 {
586 X86CPU *cpu = X86_CPU(cs);
587 CPUX86State *env = &cpu->env;
588 int r;
589
590 if (!env->tsc_khz) {
591 return 0;
592 }
593
594 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
595 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
596 -ENOTSUP;
597 if (r < 0) {
598 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
599 * TSC frequency doesn't match the one we want.
600 */
601 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
602 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
603 -ENOTSUP;
604 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
605 warn_report("TSC frequency mismatch between "
606 "VM (%" PRId64 " kHz) and host (%d kHz), "
607 "and TSC scaling unavailable",
608 env->tsc_khz, cur_freq);
609 return r;
610 }
611 }
612
613 return 0;
614 }
615
616 static bool tsc_is_stable_and_known(CPUX86State *env)
617 {
618 if (!env->tsc_khz) {
619 return false;
620 }
621 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
622 || env->user_tsc_khz;
623 }
624
625 static int hyperv_handle_properties(CPUState *cs)
626 {
627 X86CPU *cpu = X86_CPU(cs);
628 CPUX86State *env = &cpu->env;
629
630 if (cpu->hyperv_time &&
631 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
632 cpu->hyperv_time = false;
633 }
634
635 if (cpu->hyperv_relaxed_timing) {
636 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
637 }
638 if (cpu->hyperv_vapic) {
639 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
640 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
641 }
642 if (cpu->hyperv_time) {
643 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
644 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
645 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
646
647 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
648 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
649 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
650 }
651 }
652 if (cpu->hyperv_crash && has_msr_hv_crash) {
653 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
654 }
655 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
656 if (cpu->hyperv_reset && has_msr_hv_reset) {
657 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
658 }
659 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
660 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
661 }
662 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
663 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
664 }
665 if (cpu->hyperv_synic) {
666 if (!has_msr_hv_synic ||
667 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
668 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
669 return -ENOSYS;
670 }
671
672 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
673 }
674 if (cpu->hyperv_stimer) {
675 if (!has_msr_hv_stimer) {
676 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
677 return -ENOSYS;
678 }
679 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
680 }
681 return 0;
682 }
683
684 static Error *invtsc_mig_blocker;
685
686 #define KVM_MAX_CPUID_ENTRIES 100
687
688 int kvm_arch_init_vcpu(CPUState *cs)
689 {
690 struct {
691 struct kvm_cpuid2 cpuid;
692 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
693 } QEMU_PACKED cpuid_data;
694 X86CPU *cpu = X86_CPU(cs);
695 CPUX86State *env = &cpu->env;
696 uint32_t limit, i, j, cpuid_i;
697 uint32_t unused;
698 struct kvm_cpuid_entry2 *c;
699 uint32_t signature[3];
700 int kvm_base = KVM_CPUID_SIGNATURE;
701 int r;
702 Error *local_err = NULL;
703
704 memset(&cpuid_data, 0, sizeof(cpuid_data));
705
706 cpuid_i = 0;
707
708 r = kvm_arch_set_tsc_khz(cs);
709 if (r < 0) {
710 goto fail;
711 }
712
713 /* vcpu's TSC frequency is either specified by user, or following
714 * the value used by KVM if the former is not present. In the
715 * latter case, we query it from KVM and record in env->tsc_khz,
716 * so that vcpu's TSC frequency can be migrated later via this field.
717 */
718 if (!env->tsc_khz) {
719 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
720 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
721 -ENOTSUP;
722 if (r > 0) {
723 env->tsc_khz = r;
724 }
725 }
726
727 /* Paravirtualization CPUIDs */
728 if (hyperv_enabled(cpu)) {
729 c = &cpuid_data.entries[cpuid_i++];
730 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
731 if (!cpu->hyperv_vendor_id) {
732 memcpy(signature, "Microsoft Hv", 12);
733 } else {
734 size_t len = strlen(cpu->hyperv_vendor_id);
735
736 if (len > 12) {
737 error_report("hv-vendor-id truncated to 12 characters");
738 len = 12;
739 }
740 memset(signature, 0, 12);
741 memcpy(signature, cpu->hyperv_vendor_id, len);
742 }
743 c->eax = HV_CPUID_MIN;
744 c->ebx = signature[0];
745 c->ecx = signature[1];
746 c->edx = signature[2];
747
748 c = &cpuid_data.entries[cpuid_i++];
749 c->function = HV_CPUID_INTERFACE;
750 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
751 c->eax = signature[0];
752 c->ebx = 0;
753 c->ecx = 0;
754 c->edx = 0;
755
756 c = &cpuid_data.entries[cpuid_i++];
757 c->function = HV_CPUID_VERSION;
758 c->eax = 0x00001bbc;
759 c->ebx = 0x00060001;
760
761 c = &cpuid_data.entries[cpuid_i++];
762 c->function = HV_CPUID_FEATURES;
763 r = hyperv_handle_properties(cs);
764 if (r) {
765 return r;
766 }
767 c->eax = env->features[FEAT_HYPERV_EAX];
768 c->ebx = env->features[FEAT_HYPERV_EBX];
769 c->edx = env->features[FEAT_HYPERV_EDX];
770
771 c = &cpuid_data.entries[cpuid_i++];
772 c->function = HV_CPUID_ENLIGHTMENT_INFO;
773 if (cpu->hyperv_relaxed_timing) {
774 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
775 }
776 if (cpu->hyperv_vapic) {
777 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
778 }
779 c->ebx = cpu->hyperv_spinlock_attempts;
780
781 c = &cpuid_data.entries[cpuid_i++];
782 c->function = HV_CPUID_IMPLEMENT_LIMITS;
783
784 c->eax = cpu->hv_max_vps;
785 c->ebx = 0x40;
786
787 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
788 has_msr_hv_hypercall = true;
789 }
790
791 if (cpu->expose_kvm) {
792 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
793 c = &cpuid_data.entries[cpuid_i++];
794 c->function = KVM_CPUID_SIGNATURE | kvm_base;
795 c->eax = KVM_CPUID_FEATURES | kvm_base;
796 c->ebx = signature[0];
797 c->ecx = signature[1];
798 c->edx = signature[2];
799
800 c = &cpuid_data.entries[cpuid_i++];
801 c->function = KVM_CPUID_FEATURES | kvm_base;
802 c->eax = env->features[FEAT_KVM];
803 }
804
805 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
806
807 for (i = 0; i <= limit; i++) {
808 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
809 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
810 abort();
811 }
812 c = &cpuid_data.entries[cpuid_i++];
813
814 switch (i) {
815 case 2: {
816 /* Keep reading function 2 till all the input is received */
817 int times;
818
819 c->function = i;
820 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
821 KVM_CPUID_FLAG_STATE_READ_NEXT;
822 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
823 times = c->eax & 0xff;
824
825 for (j = 1; j < times; ++j) {
826 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
827 fprintf(stderr, "cpuid_data is full, no space for "
828 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
829 abort();
830 }
831 c = &cpuid_data.entries[cpuid_i++];
832 c->function = i;
833 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
834 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
835 }
836 break;
837 }
838 case 4:
839 case 0xb:
840 case 0xd:
841 for (j = 0; ; j++) {
842 if (i == 0xd && j == 64) {
843 break;
844 }
845 c->function = i;
846 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
847 c->index = j;
848 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
849
850 if (i == 4 && c->eax == 0) {
851 break;
852 }
853 if (i == 0xb && !(c->ecx & 0xff00)) {
854 break;
855 }
856 if (i == 0xd && c->eax == 0) {
857 continue;
858 }
859 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
860 fprintf(stderr, "cpuid_data is full, no space for "
861 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
862 abort();
863 }
864 c = &cpuid_data.entries[cpuid_i++];
865 }
866 break;
867 default:
868 c->function = i;
869 c->flags = 0;
870 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
871 break;
872 }
873 }
874
875 if (limit >= 0x0a) {
876 uint32_t eax, edx;
877
878 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
879
880 has_architectural_pmu_version = eax & 0xff;
881 if (has_architectural_pmu_version > 0) {
882 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
883
884 /* Shouldn't be more than 32, since that's the number of bits
885 * available in EBX to tell us _which_ counters are available.
886 * Play it safe.
887 */
888 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
889 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
890 }
891
892 if (has_architectural_pmu_version > 1) {
893 num_architectural_pmu_fixed_counters = edx & 0x1f;
894
895 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
896 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
897 }
898 }
899 }
900 }
901
902 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
903
904 for (i = 0x80000000; i <= limit; i++) {
905 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
906 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
907 abort();
908 }
909 c = &cpuid_data.entries[cpuid_i++];
910
911 c->function = i;
912 c->flags = 0;
913 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
914 }
915
916 /* Call Centaur's CPUID instructions they are supported. */
917 if (env->cpuid_xlevel2 > 0) {
918 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
919
920 for (i = 0xC0000000; i <= limit; i++) {
921 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
922 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
923 abort();
924 }
925 c = &cpuid_data.entries[cpuid_i++];
926
927 c->function = i;
928 c->flags = 0;
929 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
930 }
931 }
932
933 cpuid_data.cpuid.nent = cpuid_i;
934
935 if (((env->cpuid_version >> 8)&0xF) >= 6
936 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
937 (CPUID_MCE | CPUID_MCA)
938 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
939 uint64_t mcg_cap, unsupported_caps;
940 int banks;
941 int ret;
942
943 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
944 if (ret < 0) {
945 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
946 return ret;
947 }
948
949 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
950 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
951 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
952 return -ENOTSUP;
953 }
954
955 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
956 if (unsupported_caps) {
957 if (unsupported_caps & MCG_LMCE_P) {
958 error_report("kvm: LMCE not supported");
959 return -ENOTSUP;
960 }
961 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
962 unsupported_caps);
963 }
964
965 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
966 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
967 if (ret < 0) {
968 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
969 return ret;
970 }
971 }
972
973 qemu_add_vm_change_state_handler(cpu_update_state, env);
974
975 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
976 if (c) {
977 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
978 !!(c->ecx & CPUID_EXT_SMX);
979 }
980
981 if (env->mcg_cap & MCG_LMCE_P) {
982 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
983 }
984
985 if (!env->user_tsc_khz) {
986 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
987 invtsc_mig_blocker == NULL) {
988 /* for migration */
989 error_setg(&invtsc_mig_blocker,
990 "State blocked by non-migratable CPU device"
991 " (invtsc flag)");
992 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
993 if (local_err) {
994 error_report_err(local_err);
995 error_free(invtsc_mig_blocker);
996 goto fail;
997 }
998 /* for savevm */
999 vmstate_x86_cpu.unmigratable = 1;
1000 }
1001 }
1002
1003 if (cpu->vmware_cpuid_freq
1004 /* Guests depend on 0x40000000 to detect this feature, so only expose
1005 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1006 && cpu->expose_kvm
1007 && kvm_base == KVM_CPUID_SIGNATURE
1008 /* TSC clock must be stable and known for this feature. */
1009 && tsc_is_stable_and_known(env)) {
1010
1011 c = &cpuid_data.entries[cpuid_i++];
1012 c->function = KVM_CPUID_SIGNATURE | 0x10;
1013 c->eax = env->tsc_khz;
1014 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1015 * APIC_BUS_CYCLE_NS */
1016 c->ebx = 1000000;
1017 c->ecx = c->edx = 0;
1018
1019 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1020 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1021 }
1022
1023 cpuid_data.cpuid.nent = cpuid_i;
1024
1025 cpuid_data.cpuid.padding = 0;
1026 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1027 if (r) {
1028 goto fail;
1029 }
1030
1031 if (has_xsave) {
1032 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1033 }
1034 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1035
1036 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1037 has_msr_tsc_aux = false;
1038 }
1039
1040 return 0;
1041
1042 fail:
1043 migrate_del_blocker(invtsc_mig_blocker);
1044 return r;
1045 }
1046
1047 void kvm_arch_reset_vcpu(X86CPU *cpu)
1048 {
1049 CPUX86State *env = &cpu->env;
1050
1051 env->xcr0 = 1;
1052 if (kvm_irqchip_in_kernel()) {
1053 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1054 KVM_MP_STATE_UNINITIALIZED;
1055 } else {
1056 env->mp_state = KVM_MP_STATE_RUNNABLE;
1057 }
1058
1059 if (cpu->hyperv_synic) {
1060 int i;
1061 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1062 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1063 }
1064 }
1065 }
1066
1067 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1068 {
1069 CPUX86State *env = &cpu->env;
1070
1071 /* APs get directly into wait-for-SIPI state. */
1072 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1073 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1074 }
1075 }
1076
1077 static int kvm_get_supported_msrs(KVMState *s)
1078 {
1079 static int kvm_supported_msrs;
1080 int ret = 0;
1081
1082 /* first time */
1083 if (kvm_supported_msrs == 0) {
1084 struct kvm_msr_list msr_list, *kvm_msr_list;
1085
1086 kvm_supported_msrs = -1;
1087
1088 /* Obtain MSR list from KVM. These are the MSRs that we must
1089 * save/restore */
1090 msr_list.nmsrs = 0;
1091 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1092 if (ret < 0 && ret != -E2BIG) {
1093 return ret;
1094 }
1095 /* Old kernel modules had a bug and could write beyond the provided
1096 memory. Allocate at least a safe amount of 1K. */
1097 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1098 msr_list.nmsrs *
1099 sizeof(msr_list.indices[0])));
1100
1101 kvm_msr_list->nmsrs = msr_list.nmsrs;
1102 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1103 if (ret >= 0) {
1104 int i;
1105
1106 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1107 switch (kvm_msr_list->indices[i]) {
1108 case MSR_STAR:
1109 has_msr_star = true;
1110 break;
1111 case MSR_VM_HSAVE_PA:
1112 has_msr_hsave_pa = true;
1113 break;
1114 case MSR_TSC_AUX:
1115 has_msr_tsc_aux = true;
1116 break;
1117 case MSR_TSC_ADJUST:
1118 has_msr_tsc_adjust = true;
1119 break;
1120 case MSR_IA32_TSCDEADLINE:
1121 has_msr_tsc_deadline = true;
1122 break;
1123 case MSR_IA32_SMBASE:
1124 has_msr_smbase = true;
1125 break;
1126 case MSR_IA32_MISC_ENABLE:
1127 has_msr_misc_enable = true;
1128 break;
1129 case MSR_IA32_BNDCFGS:
1130 has_msr_bndcfgs = true;
1131 break;
1132 case MSR_IA32_XSS:
1133 has_msr_xss = true;
1134 break;
1135 case HV_X64_MSR_CRASH_CTL:
1136 has_msr_hv_crash = true;
1137 break;
1138 case HV_X64_MSR_RESET:
1139 has_msr_hv_reset = true;
1140 break;
1141 case HV_X64_MSR_VP_INDEX:
1142 has_msr_hv_vpindex = true;
1143 break;
1144 case HV_X64_MSR_VP_RUNTIME:
1145 has_msr_hv_runtime = true;
1146 break;
1147 case HV_X64_MSR_SCONTROL:
1148 has_msr_hv_synic = true;
1149 break;
1150 case HV_X64_MSR_STIMER0_CONFIG:
1151 has_msr_hv_stimer = true;
1152 break;
1153 case HV_X64_MSR_TSC_FREQUENCY:
1154 has_msr_hv_frequencies = true;
1155 break;
1156 }
1157 }
1158 }
1159
1160 g_free(kvm_msr_list);
1161 }
1162
1163 return ret;
1164 }
1165
1166 static Notifier smram_machine_done;
1167 static KVMMemoryListener smram_listener;
1168 static AddressSpace smram_address_space;
1169 static MemoryRegion smram_as_root;
1170 static MemoryRegion smram_as_mem;
1171
1172 static void register_smram_listener(Notifier *n, void *unused)
1173 {
1174 MemoryRegion *smram =
1175 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1176
1177 /* Outer container... */
1178 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1179 memory_region_set_enabled(&smram_as_root, true);
1180
1181 /* ... with two regions inside: normal system memory with low
1182 * priority, and...
1183 */
1184 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1185 get_system_memory(), 0, ~0ull);
1186 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1187 memory_region_set_enabled(&smram_as_mem, true);
1188
1189 if (smram) {
1190 /* ... SMRAM with higher priority */
1191 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1192 memory_region_set_enabled(smram, true);
1193 }
1194
1195 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1196 kvm_memory_listener_register(kvm_state, &smram_listener,
1197 &smram_address_space, 1);
1198 }
1199
1200 int kvm_arch_init(MachineState *ms, KVMState *s)
1201 {
1202 uint64_t identity_base = 0xfffbc000;
1203 uint64_t shadow_mem;
1204 int ret;
1205 struct utsname utsname;
1206
1207 #ifdef KVM_CAP_XSAVE
1208 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1209 #endif
1210
1211 #ifdef KVM_CAP_XCRS
1212 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1213 #endif
1214
1215 #ifdef KVM_CAP_PIT_STATE2
1216 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1217 #endif
1218
1219 ret = kvm_get_supported_msrs(s);
1220 if (ret < 0) {
1221 return ret;
1222 }
1223
1224 uname(&utsname);
1225 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1226
1227 /*
1228 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1229 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1230 * Since these must be part of guest physical memory, we need to allocate
1231 * them, both by setting their start addresses in the kernel and by
1232 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1233 *
1234 * Older KVM versions may not support setting the identity map base. In
1235 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1236 * size.
1237 */
1238 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1239 /* Allows up to 16M BIOSes. */
1240 identity_base = 0xfeffc000;
1241
1242 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1243 if (ret < 0) {
1244 return ret;
1245 }
1246 }
1247
1248 /* Set TSS base one page after EPT identity map. */
1249 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1250 if (ret < 0) {
1251 return ret;
1252 }
1253
1254 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1255 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1256 if (ret < 0) {
1257 fprintf(stderr, "e820_add_entry() table is full\n");
1258 return ret;
1259 }
1260 qemu_register_reset(kvm_unpoison_all, NULL);
1261
1262 shadow_mem = machine_kvm_shadow_mem(ms);
1263 if (shadow_mem != -1) {
1264 shadow_mem /= 4096;
1265 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1266 if (ret < 0) {
1267 return ret;
1268 }
1269 }
1270
1271 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1272 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1273 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1274 smram_machine_done.notify = register_smram_listener;
1275 qemu_add_machine_init_done_notifier(&smram_machine_done);
1276 }
1277 return 0;
1278 }
1279
1280 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1281 {
1282 lhs->selector = rhs->selector;
1283 lhs->base = rhs->base;
1284 lhs->limit = rhs->limit;
1285 lhs->type = 3;
1286 lhs->present = 1;
1287 lhs->dpl = 3;
1288 lhs->db = 0;
1289 lhs->s = 1;
1290 lhs->l = 0;
1291 lhs->g = 0;
1292 lhs->avl = 0;
1293 lhs->unusable = 0;
1294 }
1295
1296 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1297 {
1298 unsigned flags = rhs->flags;
1299 lhs->selector = rhs->selector;
1300 lhs->base = rhs->base;
1301 lhs->limit = rhs->limit;
1302 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1303 lhs->present = (flags & DESC_P_MASK) != 0;
1304 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1305 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1306 lhs->s = (flags & DESC_S_MASK) != 0;
1307 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1308 lhs->g = (flags & DESC_G_MASK) != 0;
1309 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1310 lhs->unusable = !lhs->present;
1311 lhs->padding = 0;
1312 }
1313
1314 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1315 {
1316 lhs->selector = rhs->selector;
1317 lhs->base = rhs->base;
1318 lhs->limit = rhs->limit;
1319 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1320 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1321 (rhs->dpl << DESC_DPL_SHIFT) |
1322 (rhs->db << DESC_B_SHIFT) |
1323 (rhs->s * DESC_S_MASK) |
1324 (rhs->l << DESC_L_SHIFT) |
1325 (rhs->g * DESC_G_MASK) |
1326 (rhs->avl * DESC_AVL_MASK);
1327 }
1328
1329 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1330 {
1331 if (set) {
1332 *kvm_reg = *qemu_reg;
1333 } else {
1334 *qemu_reg = *kvm_reg;
1335 }
1336 }
1337
1338 static int kvm_getput_regs(X86CPU *cpu, int set)
1339 {
1340 CPUX86State *env = &cpu->env;
1341 struct kvm_regs regs;
1342 int ret = 0;
1343
1344 if (!set) {
1345 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1346 if (ret < 0) {
1347 return ret;
1348 }
1349 }
1350
1351 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1352 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1353 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1354 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1355 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1356 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1357 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1358 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1359 #ifdef TARGET_X86_64
1360 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1361 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1362 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1363 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1364 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1365 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1366 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1367 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1368 #endif
1369
1370 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1371 kvm_getput_reg(&regs.rip, &env->eip, set);
1372
1373 if (set) {
1374 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1375 }
1376
1377 return ret;
1378 }
1379
1380 static int kvm_put_fpu(X86CPU *cpu)
1381 {
1382 CPUX86State *env = &cpu->env;
1383 struct kvm_fpu fpu;
1384 int i;
1385
1386 memset(&fpu, 0, sizeof fpu);
1387 fpu.fsw = env->fpus & ~(7 << 11);
1388 fpu.fsw |= (env->fpstt & 7) << 11;
1389 fpu.fcw = env->fpuc;
1390 fpu.last_opcode = env->fpop;
1391 fpu.last_ip = env->fpip;
1392 fpu.last_dp = env->fpdp;
1393 for (i = 0; i < 8; ++i) {
1394 fpu.ftwx |= (!env->fptags[i]) << i;
1395 }
1396 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1397 for (i = 0; i < CPU_NB_REGS; i++) {
1398 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1399 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1400 }
1401 fpu.mxcsr = env->mxcsr;
1402
1403 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1404 }
1405
1406 #define XSAVE_FCW_FSW 0
1407 #define XSAVE_FTW_FOP 1
1408 #define XSAVE_CWD_RIP 2
1409 #define XSAVE_CWD_RDP 4
1410 #define XSAVE_MXCSR 6
1411 #define XSAVE_ST_SPACE 8
1412 #define XSAVE_XMM_SPACE 40
1413 #define XSAVE_XSTATE_BV 128
1414 #define XSAVE_YMMH_SPACE 144
1415 #define XSAVE_BNDREGS 240
1416 #define XSAVE_BNDCSR 256
1417 #define XSAVE_OPMASK 272
1418 #define XSAVE_ZMM_Hi256 288
1419 #define XSAVE_Hi16_ZMM 416
1420 #define XSAVE_PKRU 672
1421
1422 #define XSAVE_BYTE_OFFSET(word_offset) \
1423 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1424
1425 #define ASSERT_OFFSET(word_offset, field) \
1426 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1427 offsetof(X86XSaveArea, field))
1428
1429 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1430 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1431 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1432 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1433 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1434 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1435 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1436 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1437 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1438 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1439 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1440 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1441 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1442 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1443 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1444
1445 static int kvm_put_xsave(X86CPU *cpu)
1446 {
1447 CPUX86State *env = &cpu->env;
1448 X86XSaveArea *xsave = env->kvm_xsave_buf;
1449
1450 if (!has_xsave) {
1451 return kvm_put_fpu(cpu);
1452 }
1453 x86_cpu_xsave_all_areas(cpu, xsave);
1454
1455 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1456 }
1457
1458 static int kvm_put_xcrs(X86CPU *cpu)
1459 {
1460 CPUX86State *env = &cpu->env;
1461 struct kvm_xcrs xcrs = {};
1462
1463 if (!has_xcrs) {
1464 return 0;
1465 }
1466
1467 xcrs.nr_xcrs = 1;
1468 xcrs.flags = 0;
1469 xcrs.xcrs[0].xcr = 0;
1470 xcrs.xcrs[0].value = env->xcr0;
1471 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1472 }
1473
1474 static int kvm_put_sregs(X86CPU *cpu)
1475 {
1476 CPUX86State *env = &cpu->env;
1477 struct kvm_sregs sregs;
1478
1479 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1480 if (env->interrupt_injected >= 0) {
1481 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1482 (uint64_t)1 << (env->interrupt_injected % 64);
1483 }
1484
1485 if ((env->eflags & VM_MASK)) {
1486 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1487 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1488 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1489 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1490 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1491 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1492 } else {
1493 set_seg(&sregs.cs, &env->segs[R_CS]);
1494 set_seg(&sregs.ds, &env->segs[R_DS]);
1495 set_seg(&sregs.es, &env->segs[R_ES]);
1496 set_seg(&sregs.fs, &env->segs[R_FS]);
1497 set_seg(&sregs.gs, &env->segs[R_GS]);
1498 set_seg(&sregs.ss, &env->segs[R_SS]);
1499 }
1500
1501 set_seg(&sregs.tr, &env->tr);
1502 set_seg(&sregs.ldt, &env->ldt);
1503
1504 sregs.idt.limit = env->idt.limit;
1505 sregs.idt.base = env->idt.base;
1506 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1507 sregs.gdt.limit = env->gdt.limit;
1508 sregs.gdt.base = env->gdt.base;
1509 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1510
1511 sregs.cr0 = env->cr[0];
1512 sregs.cr2 = env->cr[2];
1513 sregs.cr3 = env->cr[3];
1514 sregs.cr4 = env->cr[4];
1515
1516 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1517 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1518
1519 sregs.efer = env->efer;
1520
1521 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1522 }
1523
1524 static void kvm_msr_buf_reset(X86CPU *cpu)
1525 {
1526 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1527 }
1528
1529 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1530 {
1531 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1532 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1533 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1534
1535 assert((void *)(entry + 1) <= limit);
1536
1537 entry->index = index;
1538 entry->reserved = 0;
1539 entry->data = value;
1540 msrs->nmsrs++;
1541 }
1542
1543 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1544 {
1545 kvm_msr_buf_reset(cpu);
1546 kvm_msr_entry_add(cpu, index, value);
1547
1548 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1549 }
1550
1551 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1552 {
1553 int ret;
1554
1555 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1556 assert(ret == 1);
1557 }
1558
1559 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1560 {
1561 CPUX86State *env = &cpu->env;
1562 int ret;
1563
1564 if (!has_msr_tsc_deadline) {
1565 return 0;
1566 }
1567
1568 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1569 if (ret < 0) {
1570 return ret;
1571 }
1572
1573 assert(ret == 1);
1574 return 0;
1575 }
1576
1577 /*
1578 * Provide a separate write service for the feature control MSR in order to
1579 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1580 * before writing any other state because forcibly leaving nested mode
1581 * invalidates the VCPU state.
1582 */
1583 static int kvm_put_msr_feature_control(X86CPU *cpu)
1584 {
1585 int ret;
1586
1587 if (!has_msr_feature_control) {
1588 return 0;
1589 }
1590
1591 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1592 cpu->env.msr_ia32_feature_control);
1593 if (ret < 0) {
1594 return ret;
1595 }
1596
1597 assert(ret == 1);
1598 return 0;
1599 }
1600
1601 static int kvm_put_msrs(X86CPU *cpu, int level)
1602 {
1603 CPUX86State *env = &cpu->env;
1604 int i;
1605 int ret;
1606
1607 kvm_msr_buf_reset(cpu);
1608
1609 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1610 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1611 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1612 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1613 if (has_msr_star) {
1614 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1615 }
1616 if (has_msr_hsave_pa) {
1617 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1618 }
1619 if (has_msr_tsc_aux) {
1620 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1621 }
1622 if (has_msr_tsc_adjust) {
1623 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1624 }
1625 if (has_msr_misc_enable) {
1626 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1627 env->msr_ia32_misc_enable);
1628 }
1629 if (has_msr_smbase) {
1630 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1631 }
1632 if (has_msr_bndcfgs) {
1633 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1634 }
1635 if (has_msr_xss) {
1636 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1637 }
1638 #ifdef TARGET_X86_64
1639 if (lm_capable_kernel) {
1640 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1641 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1642 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1643 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1644 }
1645 #endif
1646 /*
1647 * The following MSRs have side effects on the guest or are too heavy
1648 * for normal writeback. Limit them to reset or full state updates.
1649 */
1650 if (level >= KVM_PUT_RESET_STATE) {
1651 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1652 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1653 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1654 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1655 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1656 }
1657 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1658 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1659 }
1660 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1661 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1662 }
1663 if (has_architectural_pmu_version > 0) {
1664 if (has_architectural_pmu_version > 1) {
1665 /* Stop the counter. */
1666 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1667 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1668 }
1669
1670 /* Set the counter values. */
1671 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1672 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1673 env->msr_fixed_counters[i]);
1674 }
1675 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1676 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1677 env->msr_gp_counters[i]);
1678 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1679 env->msr_gp_evtsel[i]);
1680 }
1681 if (has_architectural_pmu_version > 1) {
1682 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1683 env->msr_global_status);
1684 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1685 env->msr_global_ovf_ctrl);
1686
1687 /* Now start the PMU. */
1688 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1689 env->msr_fixed_ctr_ctrl);
1690 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1691 env->msr_global_ctrl);
1692 }
1693 }
1694 /*
1695 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1696 * only sync them to KVM on the first cpu
1697 */
1698 if (current_cpu == first_cpu) {
1699 if (has_msr_hv_hypercall) {
1700 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1701 env->msr_hv_guest_os_id);
1702 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1703 env->msr_hv_hypercall);
1704 }
1705 if (cpu->hyperv_time) {
1706 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1707 env->msr_hv_tsc);
1708 }
1709 }
1710 if (cpu->hyperv_vapic) {
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1712 env->msr_hv_vapic);
1713 }
1714 if (has_msr_hv_crash) {
1715 int j;
1716
1717 for (j = 0; j < HV_CRASH_PARAMS; j++)
1718 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1719 env->msr_hv_crash_params[j]);
1720
1721 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1722 }
1723 if (has_msr_hv_runtime) {
1724 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1725 }
1726 if (cpu->hyperv_synic) {
1727 int j;
1728
1729 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1730
1731 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1732 env->msr_hv_synic_control);
1733 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1734 env->msr_hv_synic_evt_page);
1735 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1736 env->msr_hv_synic_msg_page);
1737
1738 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1739 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1740 env->msr_hv_synic_sint[j]);
1741 }
1742 }
1743 if (has_msr_hv_stimer) {
1744 int j;
1745
1746 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1747 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1748 env->msr_hv_stimer_config[j]);
1749 }
1750
1751 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1752 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1753 env->msr_hv_stimer_count[j]);
1754 }
1755 }
1756 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1757 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1758
1759 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1760 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1761 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1762 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1763 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1764 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1765 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1766 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1767 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1768 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1769 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1770 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1771 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1772 /* The CPU GPs if we write to a bit above the physical limit of
1773 * the host CPU (and KVM emulates that)
1774 */
1775 uint64_t mask = env->mtrr_var[i].mask;
1776 mask &= phys_mask;
1777
1778 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1779 env->mtrr_var[i].base);
1780 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1781 }
1782 }
1783
1784 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1785 * kvm_put_msr_feature_control. */
1786 }
1787 if (env->mcg_cap) {
1788 int i;
1789
1790 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1791 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1792 if (has_msr_mcg_ext_ctl) {
1793 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1794 }
1795 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1796 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1797 }
1798 }
1799
1800 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1801 if (ret < 0) {
1802 return ret;
1803 }
1804
1805 if (ret < cpu->kvm_msr_buf->nmsrs) {
1806 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1807 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1808 (uint32_t)e->index, (uint64_t)e->data);
1809 }
1810
1811 assert(ret == cpu->kvm_msr_buf->nmsrs);
1812 return 0;
1813 }
1814
1815
1816 static int kvm_get_fpu(X86CPU *cpu)
1817 {
1818 CPUX86State *env = &cpu->env;
1819 struct kvm_fpu fpu;
1820 int i, ret;
1821
1822 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1823 if (ret < 0) {
1824 return ret;
1825 }
1826
1827 env->fpstt = (fpu.fsw >> 11) & 7;
1828 env->fpus = fpu.fsw;
1829 env->fpuc = fpu.fcw;
1830 env->fpop = fpu.last_opcode;
1831 env->fpip = fpu.last_ip;
1832 env->fpdp = fpu.last_dp;
1833 for (i = 0; i < 8; ++i) {
1834 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1835 }
1836 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1837 for (i = 0; i < CPU_NB_REGS; i++) {
1838 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1839 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1840 }
1841 env->mxcsr = fpu.mxcsr;
1842
1843 return 0;
1844 }
1845
1846 static int kvm_get_xsave(X86CPU *cpu)
1847 {
1848 CPUX86State *env = &cpu->env;
1849 X86XSaveArea *xsave = env->kvm_xsave_buf;
1850 int ret;
1851
1852 if (!has_xsave) {
1853 return kvm_get_fpu(cpu);
1854 }
1855
1856 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1857 if (ret < 0) {
1858 return ret;
1859 }
1860 x86_cpu_xrstor_all_areas(cpu, xsave);
1861
1862 return 0;
1863 }
1864
1865 static int kvm_get_xcrs(X86CPU *cpu)
1866 {
1867 CPUX86State *env = &cpu->env;
1868 int i, ret;
1869 struct kvm_xcrs xcrs;
1870
1871 if (!has_xcrs) {
1872 return 0;
1873 }
1874
1875 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1876 if (ret < 0) {
1877 return ret;
1878 }
1879
1880 for (i = 0; i < xcrs.nr_xcrs; i++) {
1881 /* Only support xcr0 now */
1882 if (xcrs.xcrs[i].xcr == 0) {
1883 env->xcr0 = xcrs.xcrs[i].value;
1884 break;
1885 }
1886 }
1887 return 0;
1888 }
1889
1890 static int kvm_get_sregs(X86CPU *cpu)
1891 {
1892 CPUX86State *env = &cpu->env;
1893 struct kvm_sregs sregs;
1894 uint32_t hflags;
1895 int bit, i, ret;
1896
1897 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1898 if (ret < 0) {
1899 return ret;
1900 }
1901
1902 /* There can only be one pending IRQ set in the bitmap at a time, so try
1903 to find it and save its number instead (-1 for none). */
1904 env->interrupt_injected = -1;
1905 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1906 if (sregs.interrupt_bitmap[i]) {
1907 bit = ctz64(sregs.interrupt_bitmap[i]);
1908 env->interrupt_injected = i * 64 + bit;
1909 break;
1910 }
1911 }
1912
1913 get_seg(&env->segs[R_CS], &sregs.cs);
1914 get_seg(&env->segs[R_DS], &sregs.ds);
1915 get_seg(&env->segs[R_ES], &sregs.es);
1916 get_seg(&env->segs[R_FS], &sregs.fs);
1917 get_seg(&env->segs[R_GS], &sregs.gs);
1918 get_seg(&env->segs[R_SS], &sregs.ss);
1919
1920 get_seg(&env->tr, &sregs.tr);
1921 get_seg(&env->ldt, &sregs.ldt);
1922
1923 env->idt.limit = sregs.idt.limit;
1924 env->idt.base = sregs.idt.base;
1925 env->gdt.limit = sregs.gdt.limit;
1926 env->gdt.base = sregs.gdt.base;
1927
1928 env->cr[0] = sregs.cr0;
1929 env->cr[2] = sregs.cr2;
1930 env->cr[3] = sregs.cr3;
1931 env->cr[4] = sregs.cr4;
1932
1933 env->efer = sregs.efer;
1934
1935 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1936
1937 #define HFLAG_COPY_MASK \
1938 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1939 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1940 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1941 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1942
1943 hflags = env->hflags & HFLAG_COPY_MASK;
1944 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1945 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1946 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1947 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1948 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1949
1950 if (env->cr[4] & CR4_OSFXSR_MASK) {
1951 hflags |= HF_OSFXSR_MASK;
1952 }
1953
1954 if (env->efer & MSR_EFER_LMA) {
1955 hflags |= HF_LMA_MASK;
1956 }
1957
1958 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1959 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1960 } else {
1961 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1962 (DESC_B_SHIFT - HF_CS32_SHIFT);
1963 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1964 (DESC_B_SHIFT - HF_SS32_SHIFT);
1965 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1966 !(hflags & HF_CS32_MASK)) {
1967 hflags |= HF_ADDSEG_MASK;
1968 } else {
1969 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1970 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1971 }
1972 }
1973 env->hflags = hflags;
1974
1975 return 0;
1976 }
1977
1978 static int kvm_get_msrs(X86CPU *cpu)
1979 {
1980 CPUX86State *env = &cpu->env;
1981 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1982 int ret, i;
1983 uint64_t mtrr_top_bits;
1984
1985 kvm_msr_buf_reset(cpu);
1986
1987 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1988 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1989 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1990 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1991 if (has_msr_star) {
1992 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1993 }
1994 if (has_msr_hsave_pa) {
1995 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1996 }
1997 if (has_msr_tsc_aux) {
1998 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1999 }
2000 if (has_msr_tsc_adjust) {
2001 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2002 }
2003 if (has_msr_tsc_deadline) {
2004 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2005 }
2006 if (has_msr_misc_enable) {
2007 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2008 }
2009 if (has_msr_smbase) {
2010 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2011 }
2012 if (has_msr_feature_control) {
2013 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2014 }
2015 if (has_msr_bndcfgs) {
2016 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2017 }
2018 if (has_msr_xss) {
2019 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2020 }
2021
2022
2023 if (!env->tsc_valid) {
2024 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2025 env->tsc_valid = !runstate_is_running();
2026 }
2027
2028 #ifdef TARGET_X86_64
2029 if (lm_capable_kernel) {
2030 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2031 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2032 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2033 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2034 }
2035 #endif
2036 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2037 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2038 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2039 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2040 }
2041 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2042 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2043 }
2044 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2045 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2046 }
2047 if (has_architectural_pmu_version > 0) {
2048 if (has_architectural_pmu_version > 1) {
2049 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2050 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2052 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2053 }
2054 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2055 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2056 }
2057 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2058 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2059 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2060 }
2061 }
2062
2063 if (env->mcg_cap) {
2064 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2065 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2066 if (has_msr_mcg_ext_ctl) {
2067 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2068 }
2069 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2070 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2071 }
2072 }
2073
2074 if (has_msr_hv_hypercall) {
2075 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2076 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2077 }
2078 if (cpu->hyperv_vapic) {
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2080 }
2081 if (cpu->hyperv_time) {
2082 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2083 }
2084 if (has_msr_hv_crash) {
2085 int j;
2086
2087 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2088 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2089 }
2090 }
2091 if (has_msr_hv_runtime) {
2092 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2093 }
2094 if (cpu->hyperv_synic) {
2095 uint32_t msr;
2096
2097 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2098 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2099 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2100 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2101 kvm_msr_entry_add(cpu, msr, 0);
2102 }
2103 }
2104 if (has_msr_hv_stimer) {
2105 uint32_t msr;
2106
2107 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2108 msr++) {
2109 kvm_msr_entry_add(cpu, msr, 0);
2110 }
2111 }
2112 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2113 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2114 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2115 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2116 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2117 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2124 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2125 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2126 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2127 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2128 }
2129 }
2130
2131 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2132 if (ret < 0) {
2133 return ret;
2134 }
2135
2136 if (ret < cpu->kvm_msr_buf->nmsrs) {
2137 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2138 error_report("error: failed to get MSR 0x%" PRIx32,
2139 (uint32_t)e->index);
2140 }
2141
2142 assert(ret == cpu->kvm_msr_buf->nmsrs);
2143 /*
2144 * MTRR masks: Each mask consists of 5 parts
2145 * a 10..0: must be zero
2146 * b 11 : valid bit
2147 * c n-1.12: actual mask bits
2148 * d 51..n: reserved must be zero
2149 * e 63.52: reserved must be zero
2150 *
2151 * 'n' is the number of physical bits supported by the CPU and is
2152 * apparently always <= 52. We know our 'n' but don't know what
2153 * the destinations 'n' is; it might be smaller, in which case
2154 * it masks (c) on loading. It might be larger, in which case
2155 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2156 * we're migrating to.
2157 */
2158
2159 if (cpu->fill_mtrr_mask) {
2160 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2161 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2162 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2163 } else {
2164 mtrr_top_bits = 0;
2165 }
2166
2167 for (i = 0; i < ret; i++) {
2168 uint32_t index = msrs[i].index;
2169 switch (index) {
2170 case MSR_IA32_SYSENTER_CS:
2171 env->sysenter_cs = msrs[i].data;
2172 break;
2173 case MSR_IA32_SYSENTER_ESP:
2174 env->sysenter_esp = msrs[i].data;
2175 break;
2176 case MSR_IA32_SYSENTER_EIP:
2177 env->sysenter_eip = msrs[i].data;
2178 break;
2179 case MSR_PAT:
2180 env->pat = msrs[i].data;
2181 break;
2182 case MSR_STAR:
2183 env->star = msrs[i].data;
2184 break;
2185 #ifdef TARGET_X86_64
2186 case MSR_CSTAR:
2187 env->cstar = msrs[i].data;
2188 break;
2189 case MSR_KERNELGSBASE:
2190 env->kernelgsbase = msrs[i].data;
2191 break;
2192 case MSR_FMASK:
2193 env->fmask = msrs[i].data;
2194 break;
2195 case MSR_LSTAR:
2196 env->lstar = msrs[i].data;
2197 break;
2198 #endif
2199 case MSR_IA32_TSC:
2200 env->tsc = msrs[i].data;
2201 break;
2202 case MSR_TSC_AUX:
2203 env->tsc_aux = msrs[i].data;
2204 break;
2205 case MSR_TSC_ADJUST:
2206 env->tsc_adjust = msrs[i].data;
2207 break;
2208 case MSR_IA32_TSCDEADLINE:
2209 env->tsc_deadline = msrs[i].data;
2210 break;
2211 case MSR_VM_HSAVE_PA:
2212 env->vm_hsave = msrs[i].data;
2213 break;
2214 case MSR_KVM_SYSTEM_TIME:
2215 env->system_time_msr = msrs[i].data;
2216 break;
2217 case MSR_KVM_WALL_CLOCK:
2218 env->wall_clock_msr = msrs[i].data;
2219 break;
2220 case MSR_MCG_STATUS:
2221 env->mcg_status = msrs[i].data;
2222 break;
2223 case MSR_MCG_CTL:
2224 env->mcg_ctl = msrs[i].data;
2225 break;
2226 case MSR_MCG_EXT_CTL:
2227 env->mcg_ext_ctl = msrs[i].data;
2228 break;
2229 case MSR_IA32_MISC_ENABLE:
2230 env->msr_ia32_misc_enable = msrs[i].data;
2231 break;
2232 case MSR_IA32_SMBASE:
2233 env->smbase = msrs[i].data;
2234 break;
2235 case MSR_IA32_FEATURE_CONTROL:
2236 env->msr_ia32_feature_control = msrs[i].data;
2237 break;
2238 case MSR_IA32_BNDCFGS:
2239 env->msr_bndcfgs = msrs[i].data;
2240 break;
2241 case MSR_IA32_XSS:
2242 env->xss = msrs[i].data;
2243 break;
2244 default:
2245 if (msrs[i].index >= MSR_MC0_CTL &&
2246 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2247 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2248 }
2249 break;
2250 case MSR_KVM_ASYNC_PF_EN:
2251 env->async_pf_en_msr = msrs[i].data;
2252 break;
2253 case MSR_KVM_PV_EOI_EN:
2254 env->pv_eoi_en_msr = msrs[i].data;
2255 break;
2256 case MSR_KVM_STEAL_TIME:
2257 env->steal_time_msr = msrs[i].data;
2258 break;
2259 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2260 env->msr_fixed_ctr_ctrl = msrs[i].data;
2261 break;
2262 case MSR_CORE_PERF_GLOBAL_CTRL:
2263 env->msr_global_ctrl = msrs[i].data;
2264 break;
2265 case MSR_CORE_PERF_GLOBAL_STATUS:
2266 env->msr_global_status = msrs[i].data;
2267 break;
2268 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2269 env->msr_global_ovf_ctrl = msrs[i].data;
2270 break;
2271 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2272 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2273 break;
2274 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2275 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2276 break;
2277 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2278 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2279 break;
2280 case HV_X64_MSR_HYPERCALL:
2281 env->msr_hv_hypercall = msrs[i].data;
2282 break;
2283 case HV_X64_MSR_GUEST_OS_ID:
2284 env->msr_hv_guest_os_id = msrs[i].data;
2285 break;
2286 case HV_X64_MSR_APIC_ASSIST_PAGE:
2287 env->msr_hv_vapic = msrs[i].data;
2288 break;
2289 case HV_X64_MSR_REFERENCE_TSC:
2290 env->msr_hv_tsc = msrs[i].data;
2291 break;
2292 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2293 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2294 break;
2295 case HV_X64_MSR_VP_RUNTIME:
2296 env->msr_hv_runtime = msrs[i].data;
2297 break;
2298 case HV_X64_MSR_SCONTROL:
2299 env->msr_hv_synic_control = msrs[i].data;
2300 break;
2301 case HV_X64_MSR_SIEFP:
2302 env->msr_hv_synic_evt_page = msrs[i].data;
2303 break;
2304 case HV_X64_MSR_SIMP:
2305 env->msr_hv_synic_msg_page = msrs[i].data;
2306 break;
2307 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2308 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2309 break;
2310 case HV_X64_MSR_STIMER0_CONFIG:
2311 case HV_X64_MSR_STIMER1_CONFIG:
2312 case HV_X64_MSR_STIMER2_CONFIG:
2313 case HV_X64_MSR_STIMER3_CONFIG:
2314 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2315 msrs[i].data;
2316 break;
2317 case HV_X64_MSR_STIMER0_COUNT:
2318 case HV_X64_MSR_STIMER1_COUNT:
2319 case HV_X64_MSR_STIMER2_COUNT:
2320 case HV_X64_MSR_STIMER3_COUNT:
2321 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2322 msrs[i].data;
2323 break;
2324 case MSR_MTRRdefType:
2325 env->mtrr_deftype = msrs[i].data;
2326 break;
2327 case MSR_MTRRfix64K_00000:
2328 env->mtrr_fixed[0] = msrs[i].data;
2329 break;
2330 case MSR_MTRRfix16K_80000:
2331 env->mtrr_fixed[1] = msrs[i].data;
2332 break;
2333 case MSR_MTRRfix16K_A0000:
2334 env->mtrr_fixed[2] = msrs[i].data;
2335 break;
2336 case MSR_MTRRfix4K_C0000:
2337 env->mtrr_fixed[3] = msrs[i].data;
2338 break;
2339 case MSR_MTRRfix4K_C8000:
2340 env->mtrr_fixed[4] = msrs[i].data;
2341 break;
2342 case MSR_MTRRfix4K_D0000:
2343 env->mtrr_fixed[5] = msrs[i].data;
2344 break;
2345 case MSR_MTRRfix4K_D8000:
2346 env->mtrr_fixed[6] = msrs[i].data;
2347 break;
2348 case MSR_MTRRfix4K_E0000:
2349 env->mtrr_fixed[7] = msrs[i].data;
2350 break;
2351 case MSR_MTRRfix4K_E8000:
2352 env->mtrr_fixed[8] = msrs[i].data;
2353 break;
2354 case MSR_MTRRfix4K_F0000:
2355 env->mtrr_fixed[9] = msrs[i].data;
2356 break;
2357 case MSR_MTRRfix4K_F8000:
2358 env->mtrr_fixed[10] = msrs[i].data;
2359 break;
2360 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2361 if (index & 1) {
2362 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2363 mtrr_top_bits;
2364 } else {
2365 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2366 }
2367 break;
2368 }
2369 }
2370
2371 return 0;
2372 }
2373
2374 static int kvm_put_mp_state(X86CPU *cpu)
2375 {
2376 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2377
2378 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2379 }
2380
2381 static int kvm_get_mp_state(X86CPU *cpu)
2382 {
2383 CPUState *cs = CPU(cpu);
2384 CPUX86State *env = &cpu->env;
2385 struct kvm_mp_state mp_state;
2386 int ret;
2387
2388 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2389 if (ret < 0) {
2390 return ret;
2391 }
2392 env->mp_state = mp_state.mp_state;
2393 if (kvm_irqchip_in_kernel()) {
2394 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2395 }
2396 return 0;
2397 }
2398
2399 static int kvm_get_apic(X86CPU *cpu)
2400 {
2401 DeviceState *apic = cpu->apic_state;
2402 struct kvm_lapic_state kapic;
2403 int ret;
2404
2405 if (apic && kvm_irqchip_in_kernel()) {
2406 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2407 if (ret < 0) {
2408 return ret;
2409 }
2410
2411 kvm_get_apic_state(apic, &kapic);
2412 }
2413 return 0;
2414 }
2415
2416 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2417 {
2418 CPUState *cs = CPU(cpu);
2419 CPUX86State *env = &cpu->env;
2420 struct kvm_vcpu_events events = {};
2421
2422 if (!kvm_has_vcpu_events()) {
2423 return 0;
2424 }
2425
2426 events.exception.injected = (env->exception_injected >= 0);
2427 events.exception.nr = env->exception_injected;
2428 events.exception.has_error_code = env->has_error_code;
2429 events.exception.error_code = env->error_code;
2430 events.exception.pad = 0;
2431
2432 events.interrupt.injected = (env->interrupt_injected >= 0);
2433 events.interrupt.nr = env->interrupt_injected;
2434 events.interrupt.soft = env->soft_interrupt;
2435
2436 events.nmi.injected = env->nmi_injected;
2437 events.nmi.pending = env->nmi_pending;
2438 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2439 events.nmi.pad = 0;
2440
2441 events.sipi_vector = env->sipi_vector;
2442 events.flags = 0;
2443
2444 if (has_msr_smbase) {
2445 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2446 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2447 if (kvm_irqchip_in_kernel()) {
2448 /* As soon as these are moved to the kernel, remove them
2449 * from cs->interrupt_request.
2450 */
2451 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2452 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2453 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2454 } else {
2455 /* Keep these in cs->interrupt_request. */
2456 events.smi.pending = 0;
2457 events.smi.latched_init = 0;
2458 }
2459 /* Stop SMI delivery on old machine types to avoid a reboot
2460 * on an inward migration of an old VM.
2461 */
2462 if (!cpu->kvm_no_smi_migration) {
2463 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2464 }
2465 }
2466
2467 if (level >= KVM_PUT_RESET_STATE) {
2468 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2469 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2470 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2471 }
2472 }
2473
2474 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2475 }
2476
2477 static int kvm_get_vcpu_events(X86CPU *cpu)
2478 {
2479 CPUX86State *env = &cpu->env;
2480 struct kvm_vcpu_events events;
2481 int ret;
2482
2483 if (!kvm_has_vcpu_events()) {
2484 return 0;
2485 }
2486
2487 memset(&events, 0, sizeof(events));
2488 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2489 if (ret < 0) {
2490 return ret;
2491 }
2492 env->exception_injected =
2493 events.exception.injected ? events.exception.nr : -1;
2494 env->has_error_code = events.exception.has_error_code;
2495 env->error_code = events.exception.error_code;
2496
2497 env->interrupt_injected =
2498 events.interrupt.injected ? events.interrupt.nr : -1;
2499 env->soft_interrupt = events.interrupt.soft;
2500
2501 env->nmi_injected = events.nmi.injected;
2502 env->nmi_pending = events.nmi.pending;
2503 if (events.nmi.masked) {
2504 env->hflags2 |= HF2_NMI_MASK;
2505 } else {
2506 env->hflags2 &= ~HF2_NMI_MASK;
2507 }
2508
2509 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2510 if (events.smi.smm) {
2511 env->hflags |= HF_SMM_MASK;
2512 } else {
2513 env->hflags &= ~HF_SMM_MASK;
2514 }
2515 if (events.smi.pending) {
2516 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2517 } else {
2518 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2519 }
2520 if (events.smi.smm_inside_nmi) {
2521 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2522 } else {
2523 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2524 }
2525 if (events.smi.latched_init) {
2526 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2527 } else {
2528 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2529 }
2530 }
2531
2532 env->sipi_vector = events.sipi_vector;
2533
2534 return 0;
2535 }
2536
2537 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2538 {
2539 CPUState *cs = CPU(cpu);
2540 CPUX86State *env = &cpu->env;
2541 int ret = 0;
2542 unsigned long reinject_trap = 0;
2543
2544 if (!kvm_has_vcpu_events()) {
2545 if (env->exception_injected == 1) {
2546 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2547 } else if (env->exception_injected == 3) {
2548 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2549 }
2550 env->exception_injected = -1;
2551 }
2552
2553 /*
2554 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2555 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2556 * by updating the debug state once again if single-stepping is on.
2557 * Another reason to call kvm_update_guest_debug here is a pending debug
2558 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2559 * reinject them via SET_GUEST_DEBUG.
2560 */
2561 if (reinject_trap ||
2562 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2563 ret = kvm_update_guest_debug(cs, reinject_trap);
2564 }
2565 return ret;
2566 }
2567
2568 static int kvm_put_debugregs(X86CPU *cpu)
2569 {
2570 CPUX86State *env = &cpu->env;
2571 struct kvm_debugregs dbgregs;
2572 int i;
2573
2574 if (!kvm_has_debugregs()) {
2575 return 0;
2576 }
2577
2578 for (i = 0; i < 4; i++) {
2579 dbgregs.db[i] = env->dr[i];
2580 }
2581 dbgregs.dr6 = env->dr[6];
2582 dbgregs.dr7 = env->dr[7];
2583 dbgregs.flags = 0;
2584
2585 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2586 }
2587
2588 static int kvm_get_debugregs(X86CPU *cpu)
2589 {
2590 CPUX86State *env = &cpu->env;
2591 struct kvm_debugregs dbgregs;
2592 int i, ret;
2593
2594 if (!kvm_has_debugregs()) {
2595 return 0;
2596 }
2597
2598 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2599 if (ret < 0) {
2600 return ret;
2601 }
2602 for (i = 0; i < 4; i++) {
2603 env->dr[i] = dbgregs.db[i];
2604 }
2605 env->dr[4] = env->dr[6] = dbgregs.dr6;
2606 env->dr[5] = env->dr[7] = dbgregs.dr7;
2607
2608 return 0;
2609 }
2610
2611 int kvm_arch_put_registers(CPUState *cpu, int level)
2612 {
2613 X86CPU *x86_cpu = X86_CPU(cpu);
2614 int ret;
2615
2616 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2617
2618 if (level >= KVM_PUT_RESET_STATE) {
2619 ret = kvm_put_msr_feature_control(x86_cpu);
2620 if (ret < 0) {
2621 return ret;
2622 }
2623 }
2624
2625 if (level == KVM_PUT_FULL_STATE) {
2626 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2627 * because TSC frequency mismatch shouldn't abort migration,
2628 * unless the user explicitly asked for a more strict TSC
2629 * setting (e.g. using an explicit "tsc-freq" option).
2630 */
2631 kvm_arch_set_tsc_khz(cpu);
2632 }
2633
2634 ret = kvm_getput_regs(x86_cpu, 1);
2635 if (ret < 0) {
2636 return ret;
2637 }
2638 ret = kvm_put_xsave(x86_cpu);
2639 if (ret < 0) {
2640 return ret;
2641 }
2642 ret = kvm_put_xcrs(x86_cpu);
2643 if (ret < 0) {
2644 return ret;
2645 }
2646 ret = kvm_put_sregs(x86_cpu);
2647 if (ret < 0) {
2648 return ret;
2649 }
2650 /* must be before kvm_put_msrs */
2651 ret = kvm_inject_mce_oldstyle(x86_cpu);
2652 if (ret < 0) {
2653 return ret;
2654 }
2655 ret = kvm_put_msrs(x86_cpu, level);
2656 if (ret < 0) {
2657 return ret;
2658 }
2659 ret = kvm_put_vcpu_events(x86_cpu, level);
2660 if (ret < 0) {
2661 return ret;
2662 }
2663 if (level >= KVM_PUT_RESET_STATE) {
2664 ret = kvm_put_mp_state(x86_cpu);
2665 if (ret < 0) {
2666 return ret;
2667 }
2668 }
2669
2670 ret = kvm_put_tscdeadline_msr(x86_cpu);
2671 if (ret < 0) {
2672 return ret;
2673 }
2674 ret = kvm_put_debugregs(x86_cpu);
2675 if (ret < 0) {
2676 return ret;
2677 }
2678 /* must be last */
2679 ret = kvm_guest_debug_workarounds(x86_cpu);
2680 if (ret < 0) {
2681 return ret;
2682 }
2683 return 0;
2684 }
2685
2686 int kvm_arch_get_registers(CPUState *cs)
2687 {
2688 X86CPU *cpu = X86_CPU(cs);
2689 int ret;
2690
2691 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2692
2693 ret = kvm_get_vcpu_events(cpu);
2694 if (ret < 0) {
2695 goto out;
2696 }
2697 /*
2698 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2699 * KVM_GET_REGS and KVM_GET_SREGS.
2700 */
2701 ret = kvm_get_mp_state(cpu);
2702 if (ret < 0) {
2703 goto out;
2704 }
2705 ret = kvm_getput_regs(cpu, 0);
2706 if (ret < 0) {
2707 goto out;
2708 }
2709 ret = kvm_get_xsave(cpu);
2710 if (ret < 0) {
2711 goto out;
2712 }
2713 ret = kvm_get_xcrs(cpu);
2714 if (ret < 0) {
2715 goto out;
2716 }
2717 ret = kvm_get_sregs(cpu);
2718 if (ret < 0) {
2719 goto out;
2720 }
2721 ret = kvm_get_msrs(cpu);
2722 if (ret < 0) {
2723 goto out;
2724 }
2725 ret = kvm_get_apic(cpu);
2726 if (ret < 0) {
2727 goto out;
2728 }
2729 ret = kvm_get_debugregs(cpu);
2730 if (ret < 0) {
2731 goto out;
2732 }
2733 ret = 0;
2734 out:
2735 cpu_sync_bndcs_hflags(&cpu->env);
2736 return ret;
2737 }
2738
2739 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2740 {
2741 X86CPU *x86_cpu = X86_CPU(cpu);
2742 CPUX86State *env = &x86_cpu->env;
2743 int ret;
2744
2745 /* Inject NMI */
2746 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2747 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2748 qemu_mutex_lock_iothread();
2749 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2750 qemu_mutex_unlock_iothread();
2751 DPRINTF("injected NMI\n");
2752 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2753 if (ret < 0) {
2754 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2755 strerror(-ret));
2756 }
2757 }
2758 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2759 qemu_mutex_lock_iothread();
2760 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2761 qemu_mutex_unlock_iothread();
2762 DPRINTF("injected SMI\n");
2763 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2764 if (ret < 0) {
2765 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2766 strerror(-ret));
2767 }
2768 }
2769 }
2770
2771 if (!kvm_pic_in_kernel()) {
2772 qemu_mutex_lock_iothread();
2773 }
2774
2775 /* Force the VCPU out of its inner loop to process any INIT requests
2776 * or (for userspace APIC, but it is cheap to combine the checks here)
2777 * pending TPR access reports.
2778 */
2779 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2780 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2781 !(env->hflags & HF_SMM_MASK)) {
2782 cpu->exit_request = 1;
2783 }
2784 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2785 cpu->exit_request = 1;
2786 }
2787 }
2788
2789 if (!kvm_pic_in_kernel()) {
2790 /* Try to inject an interrupt if the guest can accept it */
2791 if (run->ready_for_interrupt_injection &&
2792 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2793 (env->eflags & IF_MASK)) {
2794 int irq;
2795
2796 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2797 irq = cpu_get_pic_interrupt(env);
2798 if (irq >= 0) {
2799 struct kvm_interrupt intr;
2800
2801 intr.irq = irq;
2802 DPRINTF("injected interrupt %d\n", irq);
2803 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2804 if (ret < 0) {
2805 fprintf(stderr,
2806 "KVM: injection failed, interrupt lost (%s)\n",
2807 strerror(-ret));
2808 }
2809 }
2810 }
2811
2812 /* If we have an interrupt but the guest is not ready to receive an
2813 * interrupt, request an interrupt window exit. This will
2814 * cause a return to userspace as soon as the guest is ready to
2815 * receive interrupts. */
2816 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2817 run->request_interrupt_window = 1;
2818 } else {
2819 run->request_interrupt_window = 0;
2820 }
2821
2822 DPRINTF("setting tpr\n");
2823 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2824
2825 qemu_mutex_unlock_iothread();
2826 }
2827 }
2828
2829 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2830 {
2831 X86CPU *x86_cpu = X86_CPU(cpu);
2832 CPUX86State *env = &x86_cpu->env;
2833
2834 if (run->flags & KVM_RUN_X86_SMM) {
2835 env->hflags |= HF_SMM_MASK;
2836 } else {
2837 env->hflags &= ~HF_SMM_MASK;
2838 }
2839 if (run->if_flag) {
2840 env->eflags |= IF_MASK;
2841 } else {
2842 env->eflags &= ~IF_MASK;
2843 }
2844
2845 /* We need to protect the apic state against concurrent accesses from
2846 * different threads in case the userspace irqchip is used. */
2847 if (!kvm_irqchip_in_kernel()) {
2848 qemu_mutex_lock_iothread();
2849 }
2850 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2851 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2852 if (!kvm_irqchip_in_kernel()) {
2853 qemu_mutex_unlock_iothread();
2854 }
2855 return cpu_get_mem_attrs(env);
2856 }
2857
2858 int kvm_arch_process_async_events(CPUState *cs)
2859 {
2860 X86CPU *cpu = X86_CPU(cs);
2861 CPUX86State *env = &cpu->env;
2862
2863 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2864 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2865 assert(env->mcg_cap);
2866
2867 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2868
2869 kvm_cpu_synchronize_state(cs);
2870
2871 if (env->exception_injected == EXCP08_DBLE) {
2872 /* this means triple fault */
2873 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2874 cs->exit_request = 1;
2875 return 0;
2876 }
2877 env->exception_injected = EXCP12_MCHK;
2878 env->has_error_code = 0;
2879
2880 cs->halted = 0;
2881 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2882 env->mp_state = KVM_MP_STATE_RUNNABLE;
2883 }
2884 }
2885
2886 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2887 !(env->hflags & HF_SMM_MASK)) {
2888 kvm_cpu_synchronize_state(cs);
2889 do_cpu_init(cpu);
2890 }
2891
2892 if (kvm_irqchip_in_kernel()) {
2893 return 0;
2894 }
2895
2896 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2897 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2898 apic_poll_irq(cpu->apic_state);
2899 }
2900 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2901 (env->eflags & IF_MASK)) ||
2902 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2903 cs->halted = 0;
2904 }
2905 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2906 kvm_cpu_synchronize_state(cs);
2907 do_cpu_sipi(cpu);
2908 }
2909 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2910 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2911 kvm_cpu_synchronize_state(cs);
2912 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2913 env->tpr_access_type);
2914 }
2915
2916 return cs->halted;
2917 }
2918
2919 static int kvm_handle_halt(X86CPU *cpu)
2920 {
2921 CPUState *cs = CPU(cpu);
2922 CPUX86State *env = &cpu->env;
2923
2924 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2925 (env->eflags & IF_MASK)) &&
2926 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2927 cs->halted = 1;
2928 return EXCP_HLT;
2929 }
2930
2931 return 0;
2932 }
2933
2934 static int kvm_handle_tpr_access(X86CPU *cpu)
2935 {
2936 CPUState *cs = CPU(cpu);
2937 struct kvm_run *run = cs->kvm_run;
2938
2939 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2940 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2941 : TPR_ACCESS_READ);
2942 return 1;
2943 }
2944
2945 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2946 {
2947 static const uint8_t int3 = 0xcc;
2948
2949 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2950 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2951 return -EINVAL;
2952 }
2953 return 0;
2954 }
2955
2956 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2957 {
2958 uint8_t int3;
2959
2960 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2961 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2962 return -EINVAL;
2963 }
2964 return 0;
2965 }
2966
2967 static struct {
2968 target_ulong addr;
2969 int len;
2970 int type;
2971 } hw_breakpoint[4];
2972
2973 static int nb_hw_breakpoint;
2974
2975 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2976 {
2977 int n;
2978
2979 for (n = 0; n < nb_hw_breakpoint; n++) {
2980 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2981 (hw_breakpoint[n].len == len || len == -1)) {
2982 return n;
2983 }
2984 }
2985 return -1;
2986 }
2987
2988 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2989 target_ulong len, int type)
2990 {
2991 switch (type) {
2992 case GDB_BREAKPOINT_HW:
2993 len = 1;
2994 break;
2995 case GDB_WATCHPOINT_WRITE:
2996 case GDB_WATCHPOINT_ACCESS:
2997 switch (len) {
2998 case 1:
2999 break;
3000 case 2:
3001 case 4:
3002 case 8:
3003 if (addr & (len - 1)) {
3004 return -EINVAL;
3005 }
3006 break;
3007 default:
3008 return -EINVAL;
3009 }
3010 break;
3011 default:
3012 return -ENOSYS;
3013 }
3014
3015 if (nb_hw_breakpoint == 4) {
3016 return -ENOBUFS;
3017 }
3018 if (find_hw_breakpoint(addr, len, type) >= 0) {
3019 return -EEXIST;
3020 }
3021 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3022 hw_breakpoint[nb_hw_breakpoint].len = len;
3023 hw_breakpoint[nb_hw_breakpoint].type = type;
3024 nb_hw_breakpoint++;
3025
3026 return 0;
3027 }
3028
3029 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3030 target_ulong len, int type)
3031 {
3032 int n;
3033
3034 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3035 if (n < 0) {
3036 return -ENOENT;
3037 }
3038 nb_hw_breakpoint--;
3039 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3040
3041 return 0;
3042 }
3043
3044 void kvm_arch_remove_all_hw_breakpoints(void)
3045 {
3046 nb_hw_breakpoint = 0;
3047 }
3048
3049 static CPUWatchpoint hw_watchpoint;
3050
3051 static int kvm_handle_debug(X86CPU *cpu,
3052 struct kvm_debug_exit_arch *arch_info)
3053 {
3054 CPUState *cs = CPU(cpu);
3055 CPUX86State *env = &cpu->env;
3056 int ret = 0;
3057 int n;
3058
3059 if (arch_info->exception == 1) {
3060 if (arch_info->dr6 & (1 << 14)) {
3061 if (cs->singlestep_enabled) {
3062 ret = EXCP_DEBUG;
3063 }
3064 } else {
3065 for (n = 0; n < 4; n++) {
3066 if (arch_info->dr6 & (1 << n)) {
3067 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3068 case 0x0:
3069 ret = EXCP_DEBUG;
3070 break;
3071 case 0x1:
3072 ret = EXCP_DEBUG;
3073 cs->watchpoint_hit = &hw_watchpoint;
3074 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3075 hw_watchpoint.flags = BP_MEM_WRITE;
3076 break;
3077 case 0x3:
3078 ret = EXCP_DEBUG;
3079 cs->watchpoint_hit = &hw_watchpoint;
3080 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3081 hw_watchpoint.flags = BP_MEM_ACCESS;
3082 break;
3083 }
3084 }
3085 }
3086 }
3087 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3088 ret = EXCP_DEBUG;
3089 }
3090 if (ret == 0) {
3091 cpu_synchronize_state(cs);
3092 assert(env->exception_injected == -1);
3093
3094 /* pass to guest */
3095 env->exception_injected = arch_info->exception;
3096 env->has_error_code = 0;
3097 }
3098
3099 return ret;
3100 }
3101
3102 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3103 {
3104 const uint8_t type_code[] = {
3105 [GDB_BREAKPOINT_HW] = 0x0,
3106 [GDB_WATCHPOINT_WRITE] = 0x1,
3107 [GDB_WATCHPOINT_ACCESS] = 0x3
3108 };
3109 const uint8_t len_code[] = {
3110 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3111 };
3112 int n;
3113
3114 if (kvm_sw_breakpoints_active(cpu)) {
3115 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3116 }
3117 if (nb_hw_breakpoint > 0) {
3118 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3119 dbg->arch.debugreg[7] = 0x0600;
3120 for (n = 0; n < nb_hw_breakpoint; n++) {
3121 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3122 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3123 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3124 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3125 }
3126 }
3127 }
3128
3129 static bool host_supports_vmx(void)
3130 {
3131 uint32_t ecx, unused;
3132
3133 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3134 return ecx & CPUID_EXT_VMX;
3135 }
3136
3137 #define VMX_INVALID_GUEST_STATE 0x80000021
3138
3139 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3140 {
3141 X86CPU *cpu = X86_CPU(cs);
3142 uint64_t code;
3143 int ret;
3144
3145 switch (run->exit_reason) {
3146 case KVM_EXIT_HLT:
3147 DPRINTF("handle_hlt\n");
3148 qemu_mutex_lock_iothread();
3149 ret = kvm_handle_halt(cpu);
3150 qemu_mutex_unlock_iothread();
3151 break;
3152 case KVM_EXIT_SET_TPR:
3153 ret = 0;
3154 break;
3155 case KVM_EXIT_TPR_ACCESS:
3156 qemu_mutex_lock_iothread();
3157 ret = kvm_handle_tpr_access(cpu);
3158 qemu_mutex_unlock_iothread();
3159 break;
3160 case KVM_EXIT_FAIL_ENTRY:
3161 code = run->fail_entry.hardware_entry_failure_reason;
3162 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3163 code);
3164 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3165 fprintf(stderr,
3166 "\nIf you're running a guest on an Intel machine without "
3167 "unrestricted mode\n"
3168 "support, the failure can be most likely due to the guest "
3169 "entering an invalid\n"
3170 "state for Intel VT. For example, the guest maybe running "
3171 "in big real mode\n"
3172 "which is not supported on less recent Intel processors."
3173 "\n\n");
3174 }
3175 ret = -1;
3176 break;
3177 case KVM_EXIT_EXCEPTION:
3178 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3179 run->ex.exception, run->ex.error_code);
3180 ret = -1;
3181 break;
3182 case KVM_EXIT_DEBUG:
3183 DPRINTF("kvm_exit_debug\n");
3184 qemu_mutex_lock_iothread();
3185 ret = kvm_handle_debug(cpu, &run->debug.arch);
3186 qemu_mutex_unlock_iothread();
3187 break;
3188 case KVM_EXIT_HYPERV:
3189 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3190 break;
3191 case KVM_EXIT_IOAPIC_EOI:
3192 ioapic_eoi_broadcast(run->eoi.vector);
3193 ret = 0;
3194 break;
3195 default:
3196 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3197 ret = -1;
3198 break;
3199 }
3200
3201 return ret;
3202 }
3203
3204 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3205 {
3206 X86CPU *cpu = X86_CPU(cs);
3207 CPUX86State *env = &cpu->env;
3208
3209 kvm_cpu_synchronize_state(cs);
3210 return !(env->cr[0] & CR0_PE_MASK) ||
3211 ((env->segs[R_CS].selector & 3) != 3);
3212 }
3213
3214 void kvm_arch_init_irq_routing(KVMState *s)
3215 {
3216 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3217 /* If kernel can't do irq routing, interrupt source
3218 * override 0->2 cannot be set up as required by HPET.
3219 * So we have to disable it.
3220 */
3221 no_hpet = 1;
3222 }
3223 /* We know at this point that we're using the in-kernel
3224 * irqchip, so we can use irqfds, and on x86 we know
3225 * we can use msi via irqfd and GSI routing.
3226 */
3227 kvm_msi_via_irqfd_allowed = true;
3228 kvm_gsi_routing_allowed = true;
3229
3230 if (kvm_irqchip_is_split()) {
3231 int i;
3232
3233 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3234 MSI routes for signaling interrupts to the local apics. */
3235 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3236 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3237 error_report("Could not enable split IRQ mode.");
3238 exit(1);
3239 }
3240 }
3241 }
3242 }
3243
3244 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3245 {
3246 int ret;
3247 if (machine_kernel_irqchip_split(ms)) {
3248 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3249 if (ret) {
3250 error_report("Could not enable split irqchip mode: %s",
3251 strerror(-ret));
3252 exit(1);
3253 } else {
3254 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3255 kvm_split_irqchip = true;
3256 return 1;
3257 }
3258 } else {
3259 return 0;
3260 }
3261 }
3262
3263 /* Classic KVM device assignment interface. Will remain x86 only. */
3264 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3265 uint32_t flags, uint32_t *dev_id)
3266 {
3267 struct kvm_assigned_pci_dev dev_data = {
3268 .segnr = dev_addr->domain,
3269 .busnr = dev_addr->bus,
3270 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3271 .flags = flags,
3272 };
3273 int ret;
3274
3275 dev_data.assigned_dev_id =
3276 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3277
3278 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3279 if (ret < 0) {
3280 return ret;
3281 }
3282
3283 *dev_id = dev_data.assigned_dev_id;
3284
3285 return 0;
3286 }
3287
3288 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3289 {
3290 struct kvm_assigned_pci_dev dev_data = {
3291 .assigned_dev_id = dev_id,
3292 };
3293
3294 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3295 }
3296
3297 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3298 uint32_t irq_type, uint32_t guest_irq)
3299 {
3300 struct kvm_assigned_irq assigned_irq = {
3301 .assigned_dev_id = dev_id,
3302 .guest_irq = guest_irq,
3303 .flags = irq_type,
3304 };
3305
3306 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3307 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3308 } else {
3309 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3310 }
3311 }
3312
3313 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3314 uint32_t guest_irq)
3315 {
3316 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3317 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3318
3319 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3320 }
3321
3322 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3323 {
3324 struct kvm_assigned_pci_dev dev_data = {
3325 .assigned_dev_id = dev_id,
3326 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3327 };
3328
3329 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3330 }
3331
3332 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3333 uint32_t type)
3334 {
3335 struct kvm_assigned_irq assigned_irq = {
3336 .assigned_dev_id = dev_id,
3337 .flags = type,
3338 };
3339
3340 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3341 }
3342
3343 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3344 {
3345 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3346 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3347 }
3348
3349 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3350 {
3351 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3352 KVM_DEV_IRQ_GUEST_MSI, virq);
3353 }
3354
3355 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3356 {
3357 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3358 KVM_DEV_IRQ_HOST_MSI);
3359 }
3360
3361 bool kvm_device_msix_supported(KVMState *s)
3362 {
3363 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3364 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3365 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3366 }
3367
3368 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3369 uint32_t nr_vectors)
3370 {
3371 struct kvm_assigned_msix_nr msix_nr = {
3372 .assigned_dev_id = dev_id,
3373 .entry_nr = nr_vectors,
3374 };
3375
3376 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3377 }
3378
3379 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3380 int virq)
3381 {
3382 struct kvm_assigned_msix_entry msix_entry = {
3383 .assigned_dev_id = dev_id,
3384 .gsi = virq,
3385 .entry = vector,
3386 };
3387
3388 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3389 }
3390
3391 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3392 {
3393 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3394 KVM_DEV_IRQ_GUEST_MSIX, 0);
3395 }
3396
3397 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3398 {
3399 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3400 KVM_DEV_IRQ_HOST_MSIX);
3401 }
3402
3403 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3404 uint64_t address, uint32_t data, PCIDevice *dev)
3405 {
3406 X86IOMMUState *iommu = x86_iommu_get_default();
3407
3408 if (iommu) {
3409 int ret;
3410 MSIMessage src, dst;
3411 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3412
3413 src.address = route->u.msi.address_hi;
3414 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3415 src.address |= route->u.msi.address_lo;
3416 src.data = route->u.msi.data;
3417
3418 ret = class->int_remap(iommu, &src, &dst, dev ? \
3419 pci_requester_id(dev) : \
3420 X86_IOMMU_SID_INVALID);
3421 if (ret) {
3422 trace_kvm_x86_fixup_msi_error(route->gsi);
3423 return 1;
3424 }
3425
3426 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3427 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3428 route->u.msi.data = dst.data;
3429 }
3430
3431 return 0;
3432 }
3433
3434 typedef struct MSIRouteEntry MSIRouteEntry;
3435
3436 struct MSIRouteEntry {
3437 PCIDevice *dev; /* Device pointer */
3438 int vector; /* MSI/MSIX vector index */
3439 int virq; /* Virtual IRQ index */
3440 QLIST_ENTRY(MSIRouteEntry) list;
3441 };
3442
3443 /* List of used GSI routes */
3444 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3445 QLIST_HEAD_INITIALIZER(msi_route_list);
3446
3447 static void kvm_update_msi_routes_all(void *private, bool global,
3448 uint32_t index, uint32_t mask)
3449 {
3450 int cnt = 0;
3451 MSIRouteEntry *entry;
3452 MSIMessage msg;
3453 PCIDevice *dev;
3454
3455 /* TODO: explicit route update */
3456 QLIST_FOREACH(entry, &msi_route_list, list) {
3457 cnt++;
3458 dev = entry->dev;
3459 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3460 continue;
3461 }
3462 msg = pci_get_msi_message(dev, entry->vector);
3463 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3464 }
3465 kvm_irqchip_commit_routes(kvm_state);
3466 trace_kvm_x86_update_msi_routes(cnt);
3467 }
3468
3469 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3470 int vector, PCIDevice *dev)
3471 {
3472 static bool notify_list_inited = false;
3473 MSIRouteEntry *entry;
3474
3475 if (!dev) {
3476 /* These are (possibly) IOAPIC routes only used for split
3477 * kernel irqchip mode, while what we are housekeeping are
3478 * PCI devices only. */
3479 return 0;
3480 }
3481
3482 entry = g_new0(MSIRouteEntry, 1);
3483 entry->dev = dev;
3484 entry->vector = vector;
3485 entry->virq = route->gsi;
3486 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3487
3488 trace_kvm_x86_add_msi_route(route->gsi);
3489
3490 if (!notify_list_inited) {
3491 /* For the first time we do add route, add ourselves into
3492 * IOMMU's IEC notify list if needed. */
3493 X86IOMMUState *iommu = x86_iommu_get_default();
3494 if (iommu) {
3495 x86_iommu_iec_register_notifier(iommu,
3496 kvm_update_msi_routes_all,
3497 NULL);
3498 }
3499 notify_list_inited = true;
3500 }
3501 return 0;
3502 }
3503
3504 int kvm_arch_release_virq_post(int virq)
3505 {
3506 MSIRouteEntry *entry, *next;
3507 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3508 if (entry->virq == virq) {
3509 trace_kvm_x86_remove_msi_route(virq);
3510 QLIST_REMOVE(entry, list);
3511 break;
3512 }
3513 }
3514 return 0;
3515 }
3516
3517 int kvm_arch_msi_data_to_gsi(uint32_t data)
3518 {
3519 abort();
3520 }
Eric Blake's pending patches to qemu